arch/powerpc/platforms/powermac/pic.c

   1 /*
   2  *  Support for the interrupt controllers found on Power Macintosh,
   3  *  currently Apple's "Grand Central" interrupt controller in all
   4  *  it's incarnations. OpenPIC support used on newer machines is
   5  *  in a separate file
   6  *
   7  *  Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
   8  *  Copyright (C) 2005 Benjamin Herrenschmidt (benh@kernel.crashing.org)
   9  *                     IBM, Corp.
  10  *
  11  *  This program is free software; you can redistribute it and/or
  12  *  modify it under the terms of the GNU General Public License
  13  *  as published by the Free Software Foundation; either version
  14  *  2 of the License, or (at your option) any later version.
  15  *
  16  */
  17
  18 #include <linux/stddef.h>
  19 #include <linux/init.h>
  20 #include <linux/sched.h>
  21 #include <linux/signal.h>
  22 #include <linux/pci.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/sysdev.h>
  25 #include <linux/adb.h>
  26 #include <linux/pmu.h>
  27 #include <linux/module.h>
  28
  29 #include <asm/sections.h>
  30 #include <asm/io.h>
  31 #include <asm/smp.h>
  32 #include <asm/prom.h>
  33 #include <asm/pci-bridge.h>
  34 #include <asm/time.h>
  35 #include <asm/pmac_feature.h>
  36 #include <asm/mpic.h>
  37 #include <asm/xmon.h>
  38
  39 #include "pmac.h"
  40
  41 #ifdef CONFIG_PPC32
  42 struct pmac_irq_hw {
  43         unsigned int    event;
  44         unsigned int    enable;
  45         unsigned int    ack;
  46         unsigned int    level;
  47 };
  48
  49 /* Default addresses */
  50 static volatile struct pmac_irq_hw __iomem *pmac_irq_hw[4];
  51
  52 #define GC_LEVEL_MASK           0x3ff00000
  53 #define OHARE_LEVEL_MASK        0x1ff00000
  54 #define HEATHROW_LEVEL_MASK     0x1ff00000
  55
  56 static int max_irqs;
  57 static int max_real_irqs;
  58 static u32 level_mask[4];
  59
  60 static DEFINE_SPINLOCK(pmac_pic_lock);
  61
  62 #define NR_MASK_WORDS   ((NR_IRQS + 31) / 32)
  63 static unsigned long ppc_lost_interrupts[NR_MASK_WORDS];
  64 static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
  65 static int pmac_irq_cascade = -1;
  66 static struct irq_host *pmac_pic_host;
  67
  68 static void __pmac_retrigger(unsigned int irq_nr)
  69 {
  70         if (irq_nr >= max_real_irqs && pmac_irq_cascade > 0) {
  71                 __set_bit(irq_nr, ppc_lost_interrupts);
  72                 irq_nr = pmac_irq_cascade;
  73                 mb();
  74         }
  75         if (!__test_and_set_bit(irq_nr, ppc_lost_interrupts)) {
  76                 atomic_inc(&ppc_n_lost_interrupts);
  77                 set_dec(1);
  78         }
  79 }
  80
  81 static void pmac_mask_and_ack_irq(unsigned int virq)
  82 {
  83         unsigned int src = irq_map[virq].hwirq;
  84         unsigned long bit = 1UL << (src & 0x1f);
  85         int i = src >> 5;
  86         unsigned long flags;
  87
  88         spin_lock_irqsave(&pmac_pic_lock, flags);
  89         __clear_bit(src, ppc_cached_irq_mask);
  90         if (__test_and_clear_bit(src, ppc_lost_interrupts))
  91                 atomic_dec(&ppc_n_lost_interrupts);
  92         out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
  93         out_le32(&pmac_irq_hw[i]->ack, bit);
  94         do {
  95                 /* make sure ack gets to controller before we enable
  96                    interrupts */
  97                 mb();
  98         } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
  99                 != (ppc_cached_irq_mask[i] & bit));
 100         spin_unlock_irqrestore(&pmac_pic_lock, flags);
 101 }
 102
 103 static void pmac_ack_irq(unsigned int virq)
 104 {
 105         unsigned int src = irq_map[virq].hwirq;
 106         unsigned long bit = 1UL << (src & 0x1f);
 107         int i = src >> 5;
 108         unsigned long flags;
 109
 110         spin_lock_irqsave(&pmac_pic_lock, flags);
 111         if (__test_and_clear_bit(src, ppc_lost_interrupts))
 112                 atomic_dec(&ppc_n_lost_interrupts);
 113         out_le32(&pmac_irq_hw[i]->ack, bit);
 114         (void)in_le32(&pmac_irq_hw[i]->ack);
 115         spin_unlock_irqrestore(&pmac_pic_lock, flags);
 116 }
 117
 118 static void __pmac_set_irq_mask(unsigned int irq_nr, int nokicklost)
 119 {
 120         unsigned long bit = 1UL << (irq_nr & 0x1f);
 121         int i = irq_nr >> 5;
 122
 123         if ((unsigned)irq_nr >= max_irqs)
 124                 return;
 125
 126         /* enable unmasked interrupts */
 127         out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
 128
 129         do {
 130                 /* make sure mask gets to controller before we
 131                    return to user */
 132                 mb();
 133         } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
 134                 != (ppc_cached_irq_mask[i] & bit));
 135
 136         /*
 137          * Unfortunately, setting the bit in the enable register
 138          * when the device interrupt is already on *doesn't* set
 139          * the bit in the flag register or request another interrupt.
 140          */
 141         if (bit & ppc_cached_irq_mask[i] & in_le32(&pmac_irq_hw[i]->level))
 142                 __pmac_retrigger(irq_nr);
 143 }
 144
 145 /* When an irq gets requested for the first client, if it's an
 146  * edge interrupt, we clear any previous one on the controller
 147  */
 148 static unsigned int pmac_startup_irq(unsigned int virq)
 149 {
 150         unsigned long flags;
 151         unsigned int src = irq_map[virq].hwirq;
 152         unsigned long bit = 1UL << (src & 0x1f);
 153         int i = src >> 5;
 154
 155         spin_lock_irqsave(&pmac_pic_lock, flags);
 156         if ((irq_desc[virq].status & IRQ_LEVEL) == 0)
 157                 out_le32(&pmac_irq_hw[i]->ack, bit);
 158         __set_bit(src, ppc_cached_irq_mask);
 159         __pmac_set_irq_mask(src, 0);
 160         spin_unlock_irqrestore(&pmac_pic_lock, flags);
 161
 162         return 0;
 163 }
 164
 165 static void pmac_mask_irq(unsigned int virq)
 166 {
 167         unsigned long flags;
 168         unsigned int src = irq_map[virq].hwirq;
 169
 170         spin_lock_irqsave(&pmac_pic_lock, flags);
 171         __clear_bit(src, ppc_cached_irq_mask);
 172         __pmac_set_irq_mask(src, 1);
 173         spin_unlock_irqrestore(&pmac_pic_lock, flags);
 174 }
 175
 176 static void pmac_unmask_irq(unsigned int virq)
 177 {
 178         unsigned long flags;
 179         unsigned int src = irq_map[virq].hwirq;
 180
 181         spin_lock_irqsave(&pmac_pic_lock, flags);
 182         __set_bit(src, ppc_cached_irq_mask);
 183         __pmac_set_irq_mask(src, 0);
 184         spin_unlock_irqrestore(&pmac_pic_lock, flags);
 185 }
 186
 187 static int pmac_retrigger(unsigned int virq)
 188 {
 189         unsigned long flags;
 190
 191         spin_lock_irqsave(&pmac_pic_lock, flags);
 192         __pmac_retrigger(irq_map[virq].hwirq);
 193         spin_unlock_irqrestore(&pmac_pic_lock, flags);
 194         return 1;
 195 }
 196
 197 static struct irq_chip pmac_pic = {
 198         .typename       = " PMAC-PIC ",
 199         .startup        = pmac_startup_irq,
 200         .mask           = pmac_mask_irq,
 201         .ack            = pmac_ack_irq,
 202         .mask_ack       = pmac_mask_and_ack_irq,
 203         .unmask         = pmac_unmask_irq,
 204         .retrigger      = pmac_retrigger,
 205 };
 206
 207 static irqreturn_t gatwick_action(int cpl, void *dev_id)
 208 {
 209         unsigned long flags;
 210         int irq, bits;
 211         int rc = IRQ_NONE;
 212
 213         spin_lock_irqsave(&pmac_pic_lock, flags);
 214         for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) {
 215                 int i = irq >> 5;
 216                 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
 217                 /* We must read level interrupts from the level register */
 218                 bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
 219                 bits &= ppc_cached_irq_mask[i];
 220                 if (bits == 0)
 221                         continue;
 222                 irq += __ilog2(bits);
 223                 spin_unlock_irqrestore(&pmac_pic_lock, flags);
 224                 generic_handle_irq(irq);
 225                 spin_lock_irqsave(&pmac_pic_lock, flags);
 226                 rc = IRQ_HANDLED;
 227         }
 228         spin_unlock_irqrestore(&pmac_pic_lock, flags);
 229         return rc;
 230 }
 231
 232 static unsigned int pmac_pic_get_irq(void)
 233 {
 234         int irq;
 235         unsigned long bits = 0;
 236         unsigned long flags;
 237
 238 #ifdef CONFIG_SMP
 239         void psurge_smp_message_recv(void);
 240
 241         /* IPI's are a hack on the powersurge -- Cort */
 242         if ( smp_processor_id() != 0 ) {
 243                 psurge_smp_message_recv();
 244                 return NO_IRQ_IGNORE;   /* ignore, already handled */
 245         }
 246 #endif /* CONFIG_SMP */
 247         spin_lock_irqsave(&pmac_pic_lock, flags);
 248         for (irq = max_real_irqs; (irq -= 32) >= 0; ) {
 249                 int i = irq >> 5;
 250                 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
 251                 /* We must read level interrupts from the level register */
 252                 bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
 253                 bits &= ppc_cached_irq_mask[i];
 254                 if (bits == 0)
 255                         continue;
 256                 irq += __ilog2(bits);
 257                 break;
 258         }
 259         spin_unlock_irqrestore(&pmac_pic_lock, flags);
 260         if (unlikely(irq < 0))
 261                 return NO_IRQ;
 262         return irq_linear_revmap(pmac_pic_host, irq);
 263 }
 264
 265 #ifdef CONFIG_XMON
 266 static struct irqaction xmon_action = {
 267         .handler        = xmon_irq,
 268         .flags          = 0,
 269         .name           = "NMI - XMON"
 270 };
 271 #endif
 272
 273 static struct irqaction gatwick_cascade_action = {
 274         .handler        = gatwick_action,
 275         .flags          = IRQF_DISABLED,
 276         .name           = "cascade",
 277 };
 278
 279 static int pmac_pic_host_match(struct irq_host *h, struct device_node *node)
 280 {
 281         /* We match all, we don't always have a node anyway */
 282         return 1;
 283 }
 284
 285 static int pmac_pic_host_map(struct irq_host *h, unsigned int virq,
 286                              irq_hw_number_t hw)
 287 {
 288         struct irq_desc *desc = get_irq_desc(virq);
 289         int level;
 290
 291         if (hw >= max_irqs)
 292                 return -EINVAL;
 293
 294         /* Mark level interrupts, set delayed disable for edge ones and set
 295          * handlers
 296          */
 297         level = !!(level_mask[hw >> 5] & (1UL << (hw & 0x1f)));
 298         if (level)
 299                 desc->status |= IRQ_LEVEL;
 300         set_irq_chip_and_handler(virq, &pmac_pic, level ?
 301                                  handle_level_irq : handle_edge_irq);
 302         return 0;
 303 }
 304
 305 static int pmac_pic_host_xlate(struct irq_host *h, struct device_node *ct,
 306                                u32 *intspec, unsigned int intsize,
 307                                irq_hw_number_t *out_hwirq,
 308                                unsigned int *out_flags)
 309
 310 {
 311         *out_flags = IRQ_TYPE_NONE;
 312         *out_hwirq = *intspec;
 313         return 0;
 314 }
 315
 316 static struct irq_host_ops pmac_pic_host_ops = {
 317         .match = pmac_pic_host_match,
 318         .map = pmac_pic_host_map,
 319         .xlate = pmac_pic_host_xlate,
 320 };
 321
 322 static void __init pmac_pic_probe_oldstyle(void)
 323 {
 324         int i;
 325         struct device_node *master = NULL;
 326         struct device_node *slave = NULL;
 327         u8 __iomem *addr;
 328         struct resource r;
 329
 330         /* Set our get_irq function */
 331         ppc_md.get_irq = pmac_pic_get_irq;
 332
 333         /*
 334          * Find the interrupt controller type & node
 335          */
 336
 337         if ((master = of_find_node_by_name(NULL, "gc")) != NULL) {
 338                 max_irqs = max_real_irqs = 32;
 339                 level_mask[0] = GC_LEVEL_MASK;
 340         } else if ((master = of_find_node_by_name(NULL, "ohare")) != NULL) {
 341                 max_irqs = max_real_irqs = 32;
 342                 level_mask[0] = OHARE_LEVEL_MASK;
 343
 344                 /* We might have a second cascaded ohare */
 345                 slave = of_find_node_by_name(NULL, "pci106b,7");
 346                 if (slave) {
 347                         max_irqs = 64;
 348                         level_mask[1] = OHARE_LEVEL_MASK;
 349                 }
 350         } else if ((master = of_find_node_by_name(NULL, "mac-io")) != NULL) {
 351                 max_irqs = max_real_irqs = 64;
 352                 level_mask[0] = HEATHROW_LEVEL_MASK;
 353                 level_mask[1] = 0;
 354
 355                 /* We might have a second cascaded heathrow */
 356                 slave = of_find_node_by_name(master, "mac-io");
 357
 358                 /* Check ordering of master & slave */
 359                 if (of_device_is_compatible(master, "gatwick")) {
 360                         struct device_node *tmp;
 361                         BUG_ON(slave == NULL);
 362                         tmp = master;
 363                         master = slave;
 364                         slave = tmp;
 365                 }
 366
 367                 /* We found a slave */
 368                 if (slave) {
 369                         max_irqs = 128;
 370                         level_mask[2] = HEATHROW_LEVEL_MASK;
 371                         level_mask[3] = 0;
 372                 }
 373         }
 374         BUG_ON(master == NULL);
 375
 376         /*
 377          * Allocate an irq host
 378          */
 379         pmac_pic_host = irq_alloc_host(master, IRQ_HOST_MAP_LINEAR, max_irqs,
 380                                        &pmac_pic_host_ops,
 381                                        max_irqs);
 382         BUG_ON(pmac_pic_host == NULL);
 383         irq_set_default_host(pmac_pic_host);
 384
 385         /* Get addresses of first controller if we have a node for it */
 386         BUG_ON(of_address_to_resource(master, 0, &r));
 387
 388         /* Map interrupts of primary controller */
 389         addr = (u8 __iomem *) ioremap(r.start, 0x40);
 390         i = 0;
 391         pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
 392                 (addr + 0x20);
 393         if (max_real_irqs > 32)
 394                 pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
 395                         (addr + 0x10);
 396         of_node_put(master);
 397
 398         printk(KERN_INFO "irq: Found primary Apple PIC %s for %d irqs\n",
 399                master->full_name, max_real_irqs);
 400
 401         /* Map interrupts of cascaded controller */
 402         if (slave && !of_address_to_resource(slave, 0, &r)) {
 403                 addr = (u8 __iomem *)ioremap(r.start, 0x40);
 404                 pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
 405                         (addr + 0x20);
 406                 if (max_irqs > 64)
 407                         pmac_irq_hw[i++] =
 408                                 (volatile struct pmac_irq_hw __iomem *)
 409                                 (addr + 0x10);
 410                 pmac_irq_cascade = irq_of_parse_and_map(slave, 0);
 411
 412                 printk(KERN_INFO "irq: Found slave Apple PIC %s for %d irqs"
 413                        " cascade: %d\n", slave->full_name,
 414                        max_irqs - max_real_irqs, pmac_irq_cascade);
 415         }
 416         of_node_put(slave);
 417
 418         /* Disable all interrupts in all controllers */
 419         for (i = 0; i * 32 < max_irqs; ++i)
 420                 out_le32(&pmac_irq_hw[i]->enable, 0);
 421
 422         /* Hookup cascade irq */
 423         if (slave && pmac_irq_cascade != NO_IRQ)
 424                 setup_irq(pmac_irq_cascade, &gatwick_cascade_action);
 425
 426         printk(KERN_INFO "irq: System has %d possible interrupts\n", max_irqs);
 427 #ifdef CONFIG_XMON
 428         setup_irq(irq_create_mapping(NULL, 20), &xmon_action);
 429 #endif
 430 }
 431 #endif /* CONFIG_PPC32 */
 432
 433 static void pmac_u3_cascade(unsigned int irq, struct irq_desc *desc)
 434 {
 435         struct mpic *mpic = desc->handler_data;
 436
 437         unsigned int cascade_irq = mpic_get_one_irq(mpic);
 438         if (cascade_irq != NO_IRQ)
 439                 generic_handle_irq(cascade_irq);
 440         desc->chip->eoi(irq);
 441 }
 442
 443 static void __init pmac_pic_setup_mpic_nmi(struct mpic *mpic)
 444 {
 445 #if defined(CONFIG_XMON) && defined(CONFIG_PPC32)
 446         struct device_node* pswitch;
 447         int nmi_irq;
 448
 449         pswitch = of_find_node_by_name(NULL, "programmer-switch");
 450         if (pswitch) {
 451                 nmi_irq = irq_of_parse_and_map(pswitch, 0);
 452                 if (nmi_irq != NO_IRQ) {
 453                         mpic_irq_set_priority(nmi_irq, 9);
 454                         setup_irq(nmi_irq, &xmon_action);
 455                 }
 456                 of_node_put(pswitch);
 457         }
 458 #endif  /* defined(CONFIG_XMON) && defined(CONFIG_PPC32) */
 459 }
 460
 461 static struct mpic * __init pmac_setup_one_mpic(struct device_node *np,
 462                                                 int master)
 463 {
 464         const char *name = master ? " MPIC 1   " : " MPIC 2   ";
 465         struct resource r;
 466         struct mpic *mpic;
 467         unsigned int flags = master ? MPIC_PRIMARY : 0;
 468         int rc;
 469
 470         rc = of_address_to_resource(np, 0, &r);
 471         if (rc)
 472                 return NULL;
 473
 474         pmac_call_feature(PMAC_FTR_ENABLE_MPIC, np, 0, 0);
 475
 476         flags |= MPIC_WANTS_RESET;
 477         if (of_get_property(np, "big-endian", NULL))
 478                 flags |= MPIC_BIG_ENDIAN;
 479
 480         /* Primary Big Endian means HT interrupts. This is quite dodgy
 481          * but works until I find a better way
 482          */
 483         if (master && (flags & MPIC_BIG_ENDIAN))
 484                 flags |= MPIC_U3_HT_IRQS;
 485
 486         mpic = mpic_alloc(np, r.start, flags, 0, 0, name);
 487         if (mpic == NULL)
 488                 return NULL;
 489
 490         mpic_init(mpic);
 491
 492         return mpic;
 493  }
 494
 495 static int __init pmac_pic_probe_mpic(void)
 496 {
 497         struct mpic *mpic1, *mpic2;
 498         struct device_node *np, *master = NULL, *slave = NULL;
 499         unsigned int cascade;
 500
 501         /* We can have up to 2 MPICs cascaded */
 502         for (np = NULL; (np = of_find_node_by_type(np, "open-pic"))
 503                      != NULL;) {
 504                 if (master == NULL &&
 505                     of_get_property(np, "interrupts", NULL) == NULL)
 506                         master = of_node_get(np);
 507                 else if (slave == NULL)
 508                         slave = of_node_get(np);
 509                 if (master && slave)
 510                         break;
 511         }
 512
 513         /* Check for bogus setups */
 514         if (master == NULL && slave != NULL) {
 515                 master = slave;
 516                 slave = NULL;
 517         }
 518
 519         /* Not found, default to good old pmac pic */
 520         if (master == NULL)
 521                 return -ENODEV;
 522
 523         /* Set master handler */
 524         ppc_md.get_irq = mpic_get_irq;
 525
 526         /* Setup master */
 527         mpic1 = pmac_setup_one_mpic(master, 1);
 528         BUG_ON(mpic1 == NULL);
 529
 530         /* Install NMI if any */
 531         pmac_pic_setup_mpic_nmi(mpic1);
 532
 533         of_node_put(master);
 534
 535         /* No slave, let's go out */
 536         if (slave == NULL)
 537                 return 0;
 538
 539         /* Get/Map slave interrupt */
 540         cascade = irq_of_parse_and_map(slave, 0);
 541         if (cascade == NO_IRQ) {
 542                 printk(KERN_ERR "Failed to map cascade IRQ\n");
 543                 return 0;
 544         }
 545
 546         mpic2 = pmac_setup_one_mpic(slave, 0);
 547         if (mpic2 == NULL) {
 548                 printk(KERN_ERR "Failed to setup slave MPIC\n");
 549                 of_node_put(slave);
 550                 return 0;
 551         }
 552         set_irq_data(cascade, mpic2);
 553         set_irq_chained_handler(cascade, pmac_u3_cascade);
 554
 555         of_node_put(slave);
 556         return 0;
 557 }
 558
 559
 560 void __init pmac_pic_init(void)
 561 {
 562         unsigned int flags = 0;
 563
 564         /* We configure the OF parsing based on our oldworld vs. newworld
 565          * platform type and wether we were booted by BootX.
 566          */
 567 #ifdef CONFIG_PPC32
 568         if (!pmac_newworld)
 569                 flags |= OF_IMAP_OLDWORLD_MAC;
 570         if (of_get_property(of_chosen, "linux,bootx", NULL) != NULL)
 571                 flags |= OF_IMAP_NO_PHANDLE;
 572 #endif /* CONFIG_PPC_32 */
 573
 574         of_irq_map_init(flags);
 575
 576         /* We first try to detect Apple's new Core99 chipset, since mac-io
 577          * is quite different on those machines and contains an IBM MPIC2.
 578          */
 579         if (pmac_pic_probe_mpic() == 0)
 580                 return;
 581
 582 #ifdef CONFIG_PPC32
 583         pmac_pic_probe_oldstyle();
 584 #endif
 585 }
 586
 587 #if defined(CONFIG_PM) && defined(CONFIG_PPC32)
 588 /*
 589  * These procedures are used in implementing sleep on the powerbooks.
 590  * sleep_save_intrs() saves the states of all interrupt enables
 591  * and disables all interrupts except for the nominated one.
 592  * sleep_restore_intrs() restores the states of all interrupt enables.
 593  */
 594 unsigned long sleep_save_mask[2];
 595
 596 /* This used to be passed by the PMU driver but that link got
 597  * broken with the new driver model. We use this tweak for now...
 598  * We really want to do things differently though...
 599  */
 600 static int pmacpic_find_viaint(void)
 601 {
 602         int viaint = -1;
 603
 604 #ifdef CONFIG_ADB_PMU
 605         struct device_node *np;
 606
 607         if (pmu_get_model() != PMU_OHARE_BASED)
 608                 goto not_found;
 609         np = of_find_node_by_name(NULL, "via-pmu");
 610         if (np == NULL)
 611                 goto not_found;
 612         viaint = irq_of_parse_and_map(np, 0);
 613
 614 not_found:
 615 #endif /* CONFIG_ADB_PMU */
 616         return viaint;
 617 }
 618
 619 static int pmacpic_suspend(struct sys_device *sysdev, pm_message_t state)
 620 {
 621         int viaint = pmacpic_find_viaint();
 622
 623         sleep_save_mask[0] = ppc_cached_irq_mask[0];
 624         sleep_save_mask[1] = ppc_cached_irq_mask[1];
 625         ppc_cached_irq_mask[0] = 0;
 626         ppc_cached_irq_mask[1] = 0;
 627         if (viaint > 0)
 628                 set_bit(viaint, ppc_cached_irq_mask);
 629         out_le32(&pmac_irq_hw[0]->enable, ppc_cached_irq_mask[0]);
 630         if (max_real_irqs > 32)
 631                 out_le32(&pmac_irq_hw[1]->enable, ppc_cached_irq_mask[1]);
 632         (void)in_le32(&pmac_irq_hw[0]->event);
 633         /* make sure mask gets to controller before we return to caller */
 634         mb();
 635         (void)in_le32(&pmac_irq_hw[0]->enable);
 636
 637         return 0;
 638 }
 639
 640 static int pmacpic_resume(struct sys_device *sysdev)
 641 {
 642         int i;
 643
 644         out_le32(&pmac_irq_hw[0]->enable, 0);
 645         if (max_real_irqs > 32)
 646                 out_le32(&pmac_irq_hw[1]->enable, 0);
 647         mb();
 648         for (i = 0; i < max_real_irqs; ++i)
 649                 if (test_bit(i, sleep_save_mask))
 650                         pmac_unmask_irq(i);
 651
 652         return 0;
 653 }
 654
 655 #endif /* CONFIG_PM && CONFIG_PPC32 */
 656
 657 static struct sysdev_class pmacpic_sysclass = {
 658         .name = "pmac_pic",
 659 };
 660
 661 static struct sys_device device_pmacpic = {
 662         .id             = 0,
 663         .cls            = &pmacpic_sysclass,
 664 };
 665
 666 static struct sysdev_driver driver_pmacpic = {
 667 #if defined(CONFIG_PM) && defined(CONFIG_PPC32)
 668         .suspend        = &pmacpic_suspend,
 669         .resume         = &pmacpic_resume,
 670 #endif /* CONFIG_PM && CONFIG_PPC32 */
 671 };
 672
 673 static int __init init_pmacpic_sysfs(void)
 674 {
 675 #ifdef CONFIG_PPC32
 676         if (max_irqs == 0)
 677                 return -ENODEV;
 678 #endif
 679         printk(KERN_DEBUG "Registering pmac pic with sysfs...\n");
 680         sysdev_class_register(&pmacpic_sysclass);
 681         sysdev_register(&device_pmacpic);
 682         sysdev_driver_register(&pmacpic_sysclass, &driver_pmacpic);
 683         return 0;
 684 }
 685 machine_subsys_initcall(powermac, init_pmacpic_sysfs);
 686