2 * SMP support for power macintosh.
4 * We support both the old "powersurge" SMP architecture
5 * and the current Core99 (G4 PowerMac) machines.
7 * Note that we don't support the very first rev. of
8 * Apple/DayStar 2 CPUs board, the one with the funky
9 * watchdog. Hopefully, none of these should be there except
10 * maybe internally to Apple. I should probably still add some
11 * code to detect this card though and disable SMP. --BenH.
13 * Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net)
14 * and Ben Herrenschmidt <benh@kernel.crashing.org>.
16 * Support for DayStar quad CPU cards
17 * Copyright (C) XLR8, Inc. 1994-2000
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version
22 * 2 of the License, or (at your option) any later version.
24 #include <linux/kernel.h>
25 #include <linux/sched.h>
26 #include <linux/smp.h>
27 #include <linux/interrupt.h>
28 #include <linux/kernel_stat.h>
29 #include <linux/delay.h>
30 #include <linux/init.h>
31 #include <linux/spinlock.h>
32 #include <linux/errno.h>
33 #include <linux/hardirq.h>
34 #include <linux/cpu.h>
35 #include <linux/compiler.h>
37 #include <asm/ptrace.h>
38 #include <asm/atomic.h>
39 #include <asm/code-patching.h>
42 #include <asm/pgtable.h>
43 #include <asm/sections.h>
47 #include <asm/machdep.h>
48 #include <asm/pmac_feature.h>
51 #include <asm/cacheflush.h>
52 #include <asm/keylargo.h>
53 #include <asm/pmac_low_i2c.h>
54 #include <asm/pmac_pfunc.h>
59 #define DBG(fmt...) udbg_printf(fmt)
64 extern void __secondary_start_pmac_0(void);
65 extern int pmac_pfunc_base_install(void);
67 static void (*pmac_tb_freeze
)(int freeze
);
74 * Powersurge (old powermac SMP) support.
77 /* Addresses for powersurge registers */
78 #define HAMMERHEAD_BASE 0xf8000000
79 #define HHEAD_CONFIG 0x90
80 #define HHEAD_SEC_INTR 0xc0
82 /* register for interrupting the primary processor on the powersurge */
83 /* N.B. this is actually the ethernet ROM! */
84 #define PSURGE_PRI_INTR 0xf3019000
86 /* register for storing the start address for the secondary processor */
87 /* N.B. this is the PCI config space address register for the 1st bridge */
88 #define PSURGE_START 0xf2800000
90 /* Daystar/XLR8 4-CPU card */
91 #define PSURGE_QUAD_REG_ADDR 0xf8800000
93 #define PSURGE_QUAD_IRQ_SET 0
94 #define PSURGE_QUAD_IRQ_CLR 1
95 #define PSURGE_QUAD_IRQ_PRIMARY 2
96 #define PSURGE_QUAD_CKSTOP_CTL 3
97 #define PSURGE_QUAD_PRIMARY_ARB 4
98 #define PSURGE_QUAD_BOARD_ID 6
99 #define PSURGE_QUAD_WHICH_CPU 7
100 #define PSURGE_QUAD_CKSTOP_RDBK 8
101 #define PSURGE_QUAD_RESET_CTL 11
103 #define PSURGE_QUAD_OUT(r, v) (out_8(quad_base + ((r) << 4) + 4, (v)))
104 #define PSURGE_QUAD_IN(r) (in_8(quad_base + ((r) << 4) + 4) & 0x0f)
105 #define PSURGE_QUAD_BIS(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) | (v)))
106 #define PSURGE_QUAD_BIC(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v)))
108 /* virtual addresses for the above */
109 static volatile u8 __iomem
*hhead_base
;
110 static volatile u8 __iomem
*quad_base
;
111 static volatile u32 __iomem
*psurge_pri_intr
;
112 static volatile u8 __iomem
*psurge_sec_intr
;
113 static volatile u32 __iomem
*psurge_start
;
115 /* values for psurge_type */
116 #define PSURGE_NONE -1
117 #define PSURGE_DUAL 0
118 #define PSURGE_QUAD_OKEE 1
119 #define PSURGE_QUAD_COTTON 2
120 #define PSURGE_QUAD_ICEGRASS 3
122 /* what sort of powersurge board we have */
123 static int psurge_type
= PSURGE_NONE
;
126 * Set and clear IPIs for powersurge.
128 static inline void psurge_set_ipi(int cpu
)
130 if (psurge_type
== PSURGE_NONE
)
133 in_be32(psurge_pri_intr
);
134 else if (psurge_type
== PSURGE_DUAL
)
135 out_8(psurge_sec_intr
, 0);
137 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_SET
, 1 << cpu
);
140 static inline void psurge_clr_ipi(int cpu
)
143 switch(psurge_type
) {
145 out_8(psurge_sec_intr
, ~0);
149 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR
, 1 << cpu
);
155 * On powersurge (old SMP powermac architecture) we don't have
156 * separate IPIs for separate messages like openpic does. Instead
157 * we have a bitmap for each processor, where a 1 bit means that
158 * the corresponding message is pending for that processor.
159 * Ideally each cpu's entry would be in a different cache line.
162 static unsigned long psurge_smp_message
[NR_CPUS
];
164 void psurge_smp_message_recv(void)
166 int cpu
= smp_processor_id();
169 /* clear interrupt */
172 if (num_online_cpus() < 2)
175 /* make sure there is a message there */
176 for (msg
= 0; msg
< 4; msg
++)
177 if (test_and_clear_bit(msg
, &psurge_smp_message
[cpu
]))
178 smp_message_recv(msg
);
181 irqreturn_t
psurge_primary_intr(int irq
, void *d
)
183 psurge_smp_message_recv();
187 static void smp_psurge_message_pass(int target
, int msg
)
191 if (num_online_cpus() < 2)
194 for_each_online_cpu(i
) {
195 if (target
== MSG_ALL
196 || (target
== MSG_ALL_BUT_SELF
&& i
!= smp_processor_id())
198 set_bit(msg
, &psurge_smp_message
[i
]);
205 * Determine a quad card presence. We read the board ID register, we
206 * force the data bus to change to something else, and we read it again.
207 * It it's stable, then the register probably exist (ugh !)
209 static int __init
psurge_quad_probe(void)
214 type
= PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID
);
215 if (type
< PSURGE_QUAD_OKEE
|| type
> PSURGE_QUAD_ICEGRASS
216 || type
!= PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID
))
219 /* looks OK, try a slightly more rigorous test */
220 /* bogus is not necessarily cacheline-aligned,
221 though I don't suppose that really matters. -- paulus */
222 for (i
= 0; i
< 100; i
++) {
223 volatile u32 bogus
[8];
224 bogus
[(0+i
)%8] = 0x00000000;
225 bogus
[(1+i
)%8] = 0x55555555;
226 bogus
[(2+i
)%8] = 0xFFFFFFFF;
227 bogus
[(3+i
)%8] = 0xAAAAAAAA;
228 bogus
[(4+i
)%8] = 0x33333333;
229 bogus
[(5+i
)%8] = 0xCCCCCCCC;
230 bogus
[(6+i
)%8] = 0xCCCCCCCC;
231 bogus
[(7+i
)%8] = 0x33333333;
233 asm volatile("dcbf 0,%0" : : "r" (bogus
) : "memory");
235 if (type
!= PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID
))
241 static void __init
psurge_quad_init(void)
245 if (ppc_md
.progress
) ppc_md
.progress("psurge_quad_init", 0x351);
246 procbits
= ~PSURGE_QUAD_IN(PSURGE_QUAD_WHICH_CPU
);
247 if (psurge_type
== PSURGE_QUAD_ICEGRASS
)
248 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL
, procbits
);
250 PSURGE_QUAD_BIC(PSURGE_QUAD_CKSTOP_CTL
, procbits
);
252 out_8(psurge_sec_intr
, ~0);
253 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR
, procbits
);
254 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL
, procbits
);
255 if (psurge_type
!= PSURGE_QUAD_ICEGRASS
)
256 PSURGE_QUAD_BIS(PSURGE_QUAD_CKSTOP_CTL
, procbits
);
257 PSURGE_QUAD_BIC(PSURGE_QUAD_PRIMARY_ARB
, procbits
);
259 PSURGE_QUAD_BIC(PSURGE_QUAD_RESET_CTL
, procbits
);
261 PSURGE_QUAD_BIS(PSURGE_QUAD_PRIMARY_ARB
, procbits
);
265 static int __init
smp_psurge_probe(void)
268 struct device_node
*dn
;
270 /* We don't do SMP on the PPC601 -- paulus */
271 if (PVR_VER(mfspr(SPRN_PVR
)) == 1)
275 * The powersurge cpu board can be used in the generation
276 * of powermacs that have a socket for an upgradeable cpu card,
277 * including the 7500, 8500, 9500, 9600.
278 * The device tree doesn't tell you if you have 2 cpus because
279 * OF doesn't know anything about the 2nd processor.
280 * Instead we look for magic bits in magic registers,
281 * in the hammerhead memory controller in the case of the
282 * dual-cpu powersurge board. -- paulus.
284 dn
= of_find_node_by_name(NULL
, "hammerhead");
289 hhead_base
= ioremap(HAMMERHEAD_BASE
, 0x800);
290 quad_base
= ioremap(PSURGE_QUAD_REG_ADDR
, 1024);
291 psurge_sec_intr
= hhead_base
+ HHEAD_SEC_INTR
;
293 psurge_type
= psurge_quad_probe();
294 if (psurge_type
!= PSURGE_DUAL
) {
296 /* All released cards using this HW design have 4 CPUs */
298 /* No sure how timebase sync works on those, let's use SW */
299 smp_ops
->give_timebase
= smp_generic_give_timebase
;
300 smp_ops
->take_timebase
= smp_generic_take_timebase
;
303 if ((in_8(hhead_base
+ HHEAD_CONFIG
) & 0x02) == 0) {
304 /* not a dual-cpu card */
306 psurge_type
= PSURGE_NONE
;
312 psurge_start
= ioremap(PSURGE_START
, 4);
313 psurge_pri_intr
= ioremap(PSURGE_PRI_INTR
, 4);
315 /* This is necessary because OF doesn't know about the
316 * secondary cpu(s), and thus there aren't nodes in the
317 * device tree for them, and smp_setup_cpu_maps hasn't
318 * set their bits in cpu_present_map.
322 for (i
= 1; i
< ncpus
; ++i
)
323 cpu_set(i
, cpu_present_map
);
325 if (ppc_md
.progress
) ppc_md
.progress("smp_psurge_probe - done", 0x352);
330 static void __init
smp_psurge_kick_cpu(int nr
)
332 unsigned long start
= __pa(__secondary_start_pmac_0
) + nr
* 8;
333 unsigned long a
, flags
;
336 /* Defining this here is evil ... but I prefer hiding that
337 * crap to avoid giving people ideas that they can do the
340 extern volatile unsigned int cpu_callin_map
[NR_CPUS
];
342 /* may need to flush here if secondary bats aren't setup */
343 for (a
= KERNELBASE
; a
< KERNELBASE
+ 0x800000; a
+= 32)
344 asm volatile("dcbf 0,%0" : : "r" (a
) : "memory");
345 asm volatile("sync");
347 if (ppc_md
.progress
) ppc_md
.progress("smp_psurge_kick_cpu", 0x353);
349 /* This is going to freeze the timeebase, we disable interrupts */
350 local_irq_save(flags
);
352 out_be32(psurge_start
, start
);
358 * We can't use udelay here because the timebase is now frozen.
360 for (i
= 0; i
< 2000; ++i
)
361 asm volatile("nop" : : : "memory");
365 * Also, because the timebase is frozen, we must not return to the
366 * caller which will try to do udelay's etc... Instead, we wait -here-
367 * for the CPU to callin.
369 for (i
= 0; i
< 100000 && !cpu_callin_map
[nr
]; ++i
) {
370 for (j
= 1; j
< 10000; j
++)
371 asm volatile("nop" : : : "memory");
372 asm volatile("sync" : : : "memory");
374 if (!cpu_callin_map
[nr
])
377 /* And we do the TB sync here too for standard dual CPU cards */
378 if (psurge_type
== PSURGE_DUAL
) {
390 /* now interrupt the secondary, restarting both TBs */
391 if (psurge_type
== PSURGE_DUAL
)
394 if (ppc_md
.progress
) ppc_md
.progress("smp_psurge_kick_cpu - done", 0x354);
397 static struct irqaction psurge_irqaction
= {
398 .handler
= psurge_primary_intr
,
399 .flags
= IRQF_DISABLED
,
400 .name
= "primary IPI",
403 static void __init
smp_psurge_setup_cpu(int cpu_nr
)
408 /* reset the entry point so if we get another intr we won't
409 * try to startup again */
410 out_be32(psurge_start
, 0x100);
411 if (setup_irq(30, &psurge_irqaction
))
412 printk(KERN_ERR
"Couldn't get primary IPI interrupt");
415 void __init
smp_psurge_take_timebase(void)
417 if (psurge_type
!= PSURGE_DUAL
)
425 set_tb(timebase
>> 32, timebase
& 0xffffffff);
428 set_dec(tb_ticks_per_jiffy
/2);
431 void __init
smp_psurge_give_timebase(void)
433 /* Nothing to do here */
436 /* PowerSurge-style Macs */
437 struct smp_ops_t psurge_smp_ops
= {
438 .message_pass
= smp_psurge_message_pass
,
439 .probe
= smp_psurge_probe
,
440 .kick_cpu
= smp_psurge_kick_cpu
,
441 .setup_cpu
= smp_psurge_setup_cpu
,
442 .give_timebase
= smp_psurge_give_timebase
,
443 .take_timebase
= smp_psurge_take_timebase
,
445 #endif /* CONFIG_PPC32 - actually powersurge support */
448 * Core 99 and later support
452 static void smp_core99_give_timebase(void)
456 local_irq_save(flags
);
461 (*pmac_tb_freeze
)(1);
468 (*pmac_tb_freeze
)(0);
471 local_irq_restore(flags
);
475 static void __devinit
smp_core99_take_timebase(void)
479 local_irq_save(flags
);
486 set_tb(timebase
>> 32, timebase
& 0xffffffff);
490 local_irq_restore(flags
);
495 * G5s enable/disable the timebase via an i2c-connected clock chip.
497 static struct pmac_i2c_bus
*pmac_tb_clock_chip_host
;
498 static u8 pmac_tb_pulsar_addr
;
500 static void smp_core99_cypress_tb_freeze(int freeze
)
505 /* Strangely, the device-tree says address is 0xd2, but darwin
508 pmac_i2c_setmode(pmac_tb_clock_chip_host
,
509 pmac_i2c_mode_combined
);
510 rc
= pmac_i2c_xfer(pmac_tb_clock_chip_host
,
511 0xd0 | pmac_i2c_read
,
516 data
= (data
& 0xf3) | (freeze
? 0x00 : 0x0c);
518 pmac_i2c_setmode(pmac_tb_clock_chip_host
, pmac_i2c_mode_stdsub
);
519 rc
= pmac_i2c_xfer(pmac_tb_clock_chip_host
,
520 0xd0 | pmac_i2c_write
,
525 printk("Cypress Timebase %s rc: %d\n",
526 freeze
? "freeze" : "unfreeze", rc
);
527 panic("Timebase freeze failed !\n");
532 static void smp_core99_pulsar_tb_freeze(int freeze
)
537 pmac_i2c_setmode(pmac_tb_clock_chip_host
,
538 pmac_i2c_mode_combined
);
539 rc
= pmac_i2c_xfer(pmac_tb_clock_chip_host
,
540 pmac_tb_pulsar_addr
| pmac_i2c_read
,
545 data
= (data
& 0x88) | (freeze
? 0x11 : 0x22);
547 pmac_i2c_setmode(pmac_tb_clock_chip_host
, pmac_i2c_mode_stdsub
);
548 rc
= pmac_i2c_xfer(pmac_tb_clock_chip_host
,
549 pmac_tb_pulsar_addr
| pmac_i2c_write
,
553 printk(KERN_ERR
"Pulsar Timebase %s rc: %d\n",
554 freeze
? "freeze" : "unfreeze", rc
);
555 panic("Timebase freeze failed !\n");
559 static void __init
smp_core99_setup_i2c_hwsync(int ncpus
)
561 struct device_node
*cc
= NULL
;
562 struct device_node
*p
;
563 const char *name
= NULL
;
567 /* Look for the clock chip */
568 while ((cc
= of_find_node_by_name(cc
, "i2c-hwclock")) != NULL
) {
569 p
= of_get_parent(cc
);
570 ok
= p
&& of_device_is_compatible(p
, "uni-n-i2c");
575 pmac_tb_clock_chip_host
= pmac_i2c_find_bus(cc
);
576 if (pmac_tb_clock_chip_host
== NULL
)
578 reg
= of_get_property(cc
, "reg", NULL
);
583 if (of_device_is_compatible(cc
,"pulsar-legacy-slewing")) {
584 pmac_tb_freeze
= smp_core99_pulsar_tb_freeze
;
585 pmac_tb_pulsar_addr
= 0xd2;
587 } else if (of_device_is_compatible(cc
, "cy28508")) {
588 pmac_tb_freeze
= smp_core99_cypress_tb_freeze
;
593 pmac_tb_freeze
= smp_core99_pulsar_tb_freeze
;
594 pmac_tb_pulsar_addr
= 0xd4;
598 if (pmac_tb_freeze
!= NULL
)
601 if (pmac_tb_freeze
!= NULL
) {
602 /* Open i2c bus for synchronous access */
603 if (pmac_i2c_open(pmac_tb_clock_chip_host
, 1)) {
604 printk(KERN_ERR
"Failed top open i2c bus for clock"
605 " sync, fallback to software sync !\n");
608 printk(KERN_INFO
"Processor timebase sync using %s i2c clock\n",
613 pmac_tb_freeze
= NULL
;
614 pmac_tb_clock_chip_host
= NULL
;
620 * Newer G5s uses a platform function
623 static void smp_core99_pfunc_tb_freeze(int freeze
)
625 struct device_node
*cpus
;
626 struct pmf_args args
;
628 cpus
= of_find_node_by_path("/cpus");
629 BUG_ON(cpus
== NULL
);
631 args
.u
[0].v
= !freeze
;
632 pmf_call_function(cpus
, "cpu-timebase", &args
);
636 #else /* CONFIG_PPC64 */
639 * SMP G4 use a GPIO to enable/disable the timebase.
642 static unsigned int core99_tb_gpio
; /* Timebase freeze GPIO */
644 static void smp_core99_gpio_tb_freeze(int freeze
)
647 pmac_call_feature(PMAC_FTR_WRITE_GPIO
, NULL
, core99_tb_gpio
, 4);
649 pmac_call_feature(PMAC_FTR_WRITE_GPIO
, NULL
, core99_tb_gpio
, 0);
650 pmac_call_feature(PMAC_FTR_READ_GPIO
, NULL
, core99_tb_gpio
, 0);
654 #endif /* !CONFIG_PPC64 */
656 /* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */
657 volatile static long int core99_l2_cache
;
658 volatile static long int core99_l3_cache
;
660 static void __devinit
core99_init_caches(int cpu
)
663 if (!cpu_has_feature(CPU_FTR_L2CR
))
667 core99_l2_cache
= _get_L2CR();
668 printk("CPU0: L2CR is %lx\n", core99_l2_cache
);
670 printk("CPU%d: L2CR was %lx\n", cpu
, _get_L2CR());
672 _set_L2CR(core99_l2_cache
);
673 printk("CPU%d: L2CR set to %lx\n", cpu
, core99_l2_cache
);
676 if (!cpu_has_feature(CPU_FTR_L3CR
))
680 core99_l3_cache
= _get_L3CR();
681 printk("CPU0: L3CR is %lx\n", core99_l3_cache
);
683 printk("CPU%d: L3CR was %lx\n", cpu
, _get_L3CR());
685 _set_L3CR(core99_l3_cache
);
686 printk("CPU%d: L3CR set to %lx\n", cpu
, core99_l3_cache
);
688 #endif /* !CONFIG_PPC64 */
691 static void __init
smp_core99_setup(int ncpus
)
695 /* i2c based HW sync on some G5s */
696 if (machine_is_compatible("PowerMac7,2") ||
697 machine_is_compatible("PowerMac7,3") ||
698 machine_is_compatible("RackMac3,1"))
699 smp_core99_setup_i2c_hwsync(ncpus
);
701 /* pfunc based HW sync on recent G5s */
702 if (pmac_tb_freeze
== NULL
) {
703 struct device_node
*cpus
=
704 of_find_node_by_path("/cpus");
706 of_get_property(cpus
, "platform-cpu-timebase", NULL
)) {
707 pmac_tb_freeze
= smp_core99_pfunc_tb_freeze
;
708 printk(KERN_INFO
"Processor timebase sync using"
709 " platform function\n");
713 #else /* CONFIG_PPC64 */
715 /* GPIO based HW sync on ppc32 Core99 */
716 if (pmac_tb_freeze
== NULL
&& !machine_is_compatible("MacRISC4")) {
717 struct device_node
*cpu
;
718 const u32
*tbprop
= NULL
;
720 core99_tb_gpio
= KL_GPIO_TB_ENABLE
; /* default value */
721 cpu
= of_find_node_by_type(NULL
, "cpu");
723 tbprop
= of_get_property(cpu
, "timebase-enable", NULL
);
725 core99_tb_gpio
= *tbprop
;
728 pmac_tb_freeze
= smp_core99_gpio_tb_freeze
;
729 printk(KERN_INFO
"Processor timebase sync using"
730 " GPIO 0x%02x\n", core99_tb_gpio
);
733 #endif /* CONFIG_PPC64 */
735 /* No timebase sync, fallback to software */
736 if (pmac_tb_freeze
== NULL
) {
737 smp_ops
->give_timebase
= smp_generic_give_timebase
;
738 smp_ops
->take_timebase
= smp_generic_take_timebase
;
739 printk(KERN_INFO
"Processor timebase sync using software\n");
746 /* XXX should get this from reg properties */
747 for (i
= 1; i
< ncpus
; ++i
)
748 set_hard_smp_processor_id(i
, i
);
752 /* 32 bits SMP can't NAP */
753 if (!machine_is_compatible("MacRISC4"))
757 static int __init
smp_core99_probe(void)
759 struct device_node
*cpus
;
762 if (ppc_md
.progress
) ppc_md
.progress("smp_core99_probe", 0x345);
764 /* Count CPUs in the device-tree */
765 for (cpus
= NULL
; (cpus
= of_find_node_by_type(cpus
, "cpu")) != NULL
;)
768 printk(KERN_INFO
"PowerMac SMP probe found %d cpus\n", ncpus
);
770 /* Nothing more to do if less than 2 of them */
774 /* We need to perform some early initialisations before we can start
775 * setting up SMP as we are running before initcalls
777 pmac_pfunc_base_install();
780 /* Setup various bits like timebase sync method, ability to nap, ... */
781 smp_core99_setup(ncpus
);
786 /* Collect l2cr and l3cr values from CPU 0 */
787 core99_init_caches(0);
792 static void __devinit
smp_core99_kick_cpu(int nr
)
794 unsigned int save_vector
;
795 unsigned long target
, flags
;
796 unsigned int *vector
= (unsigned int *)(PAGE_OFFSET
+0x100);
798 if (nr
< 0 || nr
> 3)
802 ppc_md
.progress("smp_core99_kick_cpu", 0x346);
804 local_irq_save(flags
);
806 /* Save reset vector */
807 save_vector
= *vector
;
809 /* Setup fake reset vector that does
810 * b __secondary_start_pmac_0 + nr*8
812 target
= (unsigned long) __secondary_start_pmac_0
+ nr
* 8;
813 patch_branch(vector
, target
, BRANCH_SET_LINK
);
815 /* Put some life in our friend */
816 pmac_call_feature(PMAC_FTR_RESET_CPU
, NULL
, nr
, 0);
818 /* FIXME: We wait a bit for the CPU to take the exception, I should
819 * instead wait for the entry code to set something for me. Well,
820 * ideally, all that crap will be done in prom.c and the CPU left
821 * in a RAM-based wait loop like CHRP.
825 /* Restore our exception vector */
826 *vector
= save_vector
;
827 flush_icache_range((unsigned long) vector
, (unsigned long) vector
+ 4);
829 local_irq_restore(flags
);
830 if (ppc_md
.progress
) ppc_md
.progress("smp_core99_kick_cpu done", 0x347);
833 static void __devinit
smp_core99_setup_cpu(int cpu_nr
)
837 core99_init_caches(cpu_nr
);
840 mpic_setup_this_cpu();
844 extern void g5_phy_disable_cpu1(void);
846 /* Close i2c bus if it was used for tb sync */
847 if (pmac_tb_clock_chip_host
) {
848 pmac_i2c_close(pmac_tb_clock_chip_host
);
849 pmac_tb_clock_chip_host
= NULL
;
852 /* If we didn't start the second CPU, we must take
855 if (machine_is_compatible("MacRISC4") &&
856 num_online_cpus() < 2)
857 g5_phy_disable_cpu1();
858 #endif /* CONFIG_PPC64 */
861 ppc_md
.progress("core99_setup_cpu 0 done", 0x349);
866 #if defined(CONFIG_HOTPLUG_CPU) && defined(CONFIG_PPC32)
868 int smp_core99_cpu_disable(void)
870 cpu_clear(smp_processor_id(), cpu_online_map
);
872 /* XXX reset cpu affinity here */
873 mpic_cpu_set_priority(0xf);
874 asm volatile("mtdec %0" : : "r" (0x7fffffff));
877 asm volatile("mtdec %0" : : "r" (0x7fffffff));
881 extern void low_cpu_die(void) __attribute__((noreturn
)); /* in sleep.S */
882 static int cpu_dead
[NR_CPUS
];
887 cpu_dead
[smp_processor_id()] = 1;
892 void smp_core99_cpu_die(unsigned int cpu
)
897 while (!cpu_dead
[cpu
]) {
898 if (--timeout
== 0) {
899 printk("CPU %u refused to die!\n", cpu
);
907 #endif /* CONFIG_HOTPLUG_CPU && CONFIG_PP32 */
909 /* Core99 Macs (dual G4s and G5s) */
910 struct smp_ops_t core99_smp_ops
= {
911 .message_pass
= smp_mpic_message_pass
,
912 .probe
= smp_core99_probe
,
913 .kick_cpu
= smp_core99_kick_cpu
,
914 .setup_cpu
= smp_core99_setup_cpu
,
915 .give_timebase
= smp_core99_give_timebase
,
916 .take_timebase
= smp_core99_take_timebase
,
917 #if defined(CONFIG_HOTPLUG_CPU)
918 # if defined(CONFIG_PPC32)
919 .cpu_disable
= smp_core99_cpu_disable
,
920 .cpu_die
= smp_core99_cpu_die
,
922 # if defined(CONFIG_PPC64)
923 .cpu_disable
= generic_cpu_disable
,
924 .cpu_die
= generic_cpu_die
,
925 /* intentionally do *NOT* assign cpu_enable,
926 * the generic code will use kick_cpu then! */
931 void __init
pmac_setup_smp(void)
933 struct device_node
*np
;
935 /* Check for Core99 */
936 np
= of_find_node_by_name(NULL
, "uni-n");
938 np
= of_find_node_by_name(NULL
, "u3");
940 np
= of_find_node_by_name(NULL
, "u4");
943 smp_ops
= &core99_smp_ops
;
947 /* We have to set bits in cpu_possible_map here since the
948 * secondary CPU(s) aren't in the device tree. Various
949 * things won't be initialized for CPUs not in the possible
950 * map, so we really need to fix it up here.
954 for (cpu
= 1; cpu
< 4 && cpu
< NR_CPUS
; ++cpu
)
955 cpu_set(cpu
, cpu_possible_map
);
956 smp_ops
= &psurge_smp_ops
;
958 #endif /* CONFIG_PPC32 */