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acpi_pad: build only on X86
[linux-2.6/linux-acpi-2.6.git] / arch / x86 / kernel / amd_iommu_init.c
blobc1b17e97252e08f89f2221c2228642e0ff3dad81
1 /*
2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/gfp.h>
23 #include <linux/list.h>
24 #include <linux/sysdev.h>
25 #include <linux/interrupt.h>
26 #include <linux/msi.h>
27 #include <asm/pci-direct.h>
28 #include <asm/amd_iommu_types.h>
29 #include <asm/amd_iommu.h>
30 #include <asm/iommu.h>
31 #include <asm/gart.h>
32
33 /*
34 * definitions for the ACPI scanning code
35 */
36 #define IVRS_HEADER_LENGTH 48
37
38 #define ACPI_IVHD_TYPE 0x10
39 #define ACPI_IVMD_TYPE_ALL 0x20
40 #define ACPI_IVMD_TYPE 0x21
41 #define ACPI_IVMD_TYPE_RANGE 0x22
42
43 #define IVHD_DEV_ALL 0x01
44 #define IVHD_DEV_SELECT 0x02
45 #define IVHD_DEV_SELECT_RANGE_START 0x03
46 #define IVHD_DEV_RANGE_END 0x04
47 #define IVHD_DEV_ALIAS 0x42
48 #define IVHD_DEV_ALIAS_RANGE 0x43
49 #define IVHD_DEV_EXT_SELECT 0x46
50 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
51
52 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
53 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
54 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
55 #define IVHD_FLAG_ISOC_EN_MASK 0x08
56
57 #define IVMD_FLAG_EXCL_RANGE 0x08
58 #define IVMD_FLAG_UNITY_MAP 0x01
59
60 #define ACPI_DEVFLAG_INITPASS 0x01
61 #define ACPI_DEVFLAG_EXTINT 0x02
62 #define ACPI_DEVFLAG_NMI 0x04
63 #define ACPI_DEVFLAG_SYSMGT1 0x10
64 #define ACPI_DEVFLAG_SYSMGT2 0x20
65 #define ACPI_DEVFLAG_LINT0 0x40
66 #define ACPI_DEVFLAG_LINT1 0x80
67 #define ACPI_DEVFLAG_ATSDIS 0x10000000
68
69 /*
70 * ACPI table definitions
71 *
72 * These data structures are laid over the table to parse the important values
73 * out of it.
74 */
75
76 /*
77 * structure describing one IOMMU in the ACPI table. Typically followed by one
78 * or more ivhd_entrys.
79 */
80 struct ivhd_header {
81 u8 type;
82 u8 flags;
83 u16 length;
84 u16 devid;
85 u16 cap_ptr;
86 u64 mmio_phys;
87 u16 pci_seg;
88 u16 info;
89 u32 reserved;
90 } __attribute__((packed));
91
92 /*
93 * A device entry describing which devices a specific IOMMU translates and
94 * which requestor ids they use.
95 */
96 struct ivhd_entry {
97 u8 type;
98 u16 devid;
99 u8 flags;
100 u32 ext;
101 } __attribute__((packed));
102
103 /*
104 * An AMD IOMMU memory definition structure. It defines things like exclusion
105 * ranges for devices and regions that should be unity mapped.
106 */
107 struct ivmd_header {
108 u8 type;
109 u8 flags;
110 u16 length;
111 u16 devid;
112 u16 aux;
113 u64 resv;
114 u64 range_start;
115 u64 range_length;
116 } __attribute__((packed));
117
118 bool amd_iommu_dump;
119
120 static int __initdata amd_iommu_detected;
121
122 u16 amd_iommu_last_bdf; /* largest PCI device id we have
123 to handle */
124 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
125 we find in ACPI */
126 #ifdef CONFIG_IOMMU_STRESS
127 bool amd_iommu_isolate = false;
128 #else
129 bool amd_iommu_isolate = true; /* if true, device isolation is
130 enabled */
131 #endif
132
133 bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
134
135 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
136 system */
137
138 /*
139 * Pointer to the device table which is shared by all AMD IOMMUs
140 * it is indexed by the PCI device id or the HT unit id and contains
141 * information about the domain the device belongs to as well as the
142 * page table root pointer.
143 */
144 struct dev_table_entry *amd_iommu_dev_table;
145
146 /*
147 * The alias table is a driver specific data structure which contains the
148 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
149 * More than one device can share the same requestor id.
150 */
151 u16 *amd_iommu_alias_table;
152
153 /*
154 * The rlookup table is used to find the IOMMU which is responsible
155 * for a specific device. It is also indexed by the PCI device id.
156 */
157 struct amd_iommu **amd_iommu_rlookup_table;
158
159 /*
160 * The pd table (protection domain table) is used to find the protection domain
161 * data structure a device belongs to. Indexed with the PCI device id too.
162 */
163 struct protection_domain **amd_iommu_pd_table;
164
165 /*
166 * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap
167 * to know which ones are already in use.
168 */
169 unsigned long *amd_iommu_pd_alloc_bitmap;
170
171 static u32 dev_table_size; /* size of the device table */
172 static u32 alias_table_size; /* size of the alias table */
173 static u32 rlookup_table_size; /* size if the rlookup table */
174
175 static inline void update_last_devid(u16 devid)
176 {
177 if (devid > amd_iommu_last_bdf)
178 amd_iommu_last_bdf = devid;
179 }
180
181 static inline unsigned long tbl_size(int entry_size)
182 {
183 unsigned shift = PAGE_SHIFT +
184 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
185
186 return 1UL << shift;
187 }
188
189 /****************************************************************************
190 *
191 * AMD IOMMU MMIO register space handling functions
192 *
193 * These functions are used to program the IOMMU device registers in
194 * MMIO space required for that driver.
195 *
196 ****************************************************************************/
197
198 /*
199 * This function set the exclusion range in the IOMMU. DMA accesses to the
200 * exclusion range are passed through untranslated
201 */
202 static void iommu_set_exclusion_range(struct amd_iommu *iommu)
203 {
204 u64 start = iommu->exclusion_start & PAGE_MASK;
205 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
206 u64 entry;
207
208 if (!iommu->exclusion_start)
209 return;
210
211 entry = start | MMIO_EXCL_ENABLE_MASK;
212 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
213 &entry, sizeof(entry));
214
215 entry = limit;
216 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
217 &entry, sizeof(entry));
218 }
219
220 /* Programs the physical address of the device table into the IOMMU hardware */
221 static void __init iommu_set_device_table(struct amd_iommu *iommu)
222 {
223 u64 entry;
224
225 BUG_ON(iommu->mmio_base == NULL);
226
227 entry = virt_to_phys(amd_iommu_dev_table);
228 entry |= (dev_table_size >> 12) - 1;
229 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
230 &entry, sizeof(entry));
231 }
232
233 /* Generic functions to enable/disable certain features of the IOMMU. */
234 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
235 {
236 u32 ctrl;
237
238 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
239 ctrl |= (1 << bit);
240 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
241 }
242
243 static void __init iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
244 {
245 u32 ctrl;
246
247 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
248 ctrl &= ~(1 << bit);
249 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
250 }
251
252 /* Function to enable the hardware */
253 static void iommu_enable(struct amd_iommu *iommu)
254 {
255 printk(KERN_INFO "AMD IOMMU: Enabling IOMMU at %s cap 0x%hx\n",
256 dev_name(&iommu->dev->dev), iommu->cap_ptr);
257
258 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
259 }
260
261 static void iommu_disable(struct amd_iommu *iommu)
262 {
263 /* Disable command buffer */
264 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
265
266 /* Disable event logging and event interrupts */
267 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
268 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
269
270 /* Disable IOMMU hardware itself */
271 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
272 }
273
274 /*
275 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
276 * the system has one.
277 */
278 static u8 * __init iommu_map_mmio_space(u64 address)
279 {
280 u8 *ret;
281
282 if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu"))
283 return NULL;
284
285 ret = ioremap_nocache(address, MMIO_REGION_LENGTH);
286 if (ret != NULL)
287 return ret;
288
289 release_mem_region(address, MMIO_REGION_LENGTH);
290
291 return NULL;
292 }
293
294 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
295 {
296 if (iommu->mmio_base)
297 iounmap(iommu->mmio_base);
298 release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH);
299 }
300
301 /****************************************************************************
302 *
303 * The functions below belong to the first pass of AMD IOMMU ACPI table
304 * parsing. In this pass we try to find out the highest device id this
305 * code has to handle. Upon this information the size of the shared data
306 * structures is determined later.
307 *
308 ****************************************************************************/
309
310 /*
311 * This function calculates the length of a given IVHD entry
312 */
313 static inline int ivhd_entry_length(u8 *ivhd)
314 {
315 return 0x04 << (*ivhd >> 6);
316 }
317
318 /*
319 * This function reads the last device id the IOMMU has to handle from the PCI
320 * capability header for this IOMMU
321 */
322 static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
323 {
324 u32 cap;
325
326 cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
327 update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));
328
329 return 0;
330 }
331
332 /*
333 * After reading the highest device id from the IOMMU PCI capability header
334 * this function looks if there is a higher device id defined in the ACPI table
335 */
336 static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
337 {
338 u8 *p = (void *)h, *end = (void *)h;
339 struct ivhd_entry *dev;
340
341 p += sizeof(*h);
342 end += h->length;
343
344 find_last_devid_on_pci(PCI_BUS(h->devid),
345 PCI_SLOT(h->devid),
346 PCI_FUNC(h->devid),
347 h->cap_ptr);
348
349 while (p < end) {
350 dev = (struct ivhd_entry *)p;
351 switch (dev->type) {
352 case IVHD_DEV_SELECT:
353 case IVHD_DEV_RANGE_END:
354 case IVHD_DEV_ALIAS:
355 case IVHD_DEV_EXT_SELECT:
356 /* all the above subfield types refer to device ids */
357 update_last_devid(dev->devid);
358 break;
359 default:
360 break;
361 }
362 p += ivhd_entry_length(p);
363 }
364
365 WARN_ON(p != end);
366
367 return 0;
368 }
369
370 /*
371 * Iterate over all IVHD entries in the ACPI table and find the highest device
372 * id which we need to handle. This is the first of three functions which parse
373 * the ACPI table. So we check the checksum here.
374 */
375 static int __init find_last_devid_acpi(struct acpi_table_header *table)
376 {
377 int i;
378 u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
379 struct ivhd_header *h;
380
381 /*
382 * Validate checksum here so we don't need to do it when
383 * we actually parse the table
384 */
385 for (i = 0; i < table->length; ++i)
386 checksum += p[i];
387 if (checksum != 0)
388 /* ACPI table corrupt */
389 return -ENODEV;
390
391 p += IVRS_HEADER_LENGTH;
392
393 end += table->length;
394 while (p < end) {
395 h = (struct ivhd_header *)p;
396 switch (h->type) {
397 case ACPI_IVHD_TYPE:
398 find_last_devid_from_ivhd(h);
399 break;
400 default:
401 break;
402 }
403 p += h->length;
404 }
405 WARN_ON(p != end);
406
407 return 0;
408 }
409
410 /****************************************************************************
411 *
412 * The following functions belong the the code path which parses the ACPI table
413 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
414 * data structures, initialize the device/alias/rlookup table and also
415 * basically initialize the hardware.
416 *
417 ****************************************************************************/
418
419 /*
420 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
421 * write commands to that buffer later and the IOMMU will execute them
422 * asynchronously
423 */
424 static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
425 {
426 u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
427 get_order(CMD_BUFFER_SIZE));
428
429 if (cmd_buf == NULL)
430 return NULL;
431
432 iommu->cmd_buf_size = CMD_BUFFER_SIZE;
433
434 return cmd_buf;
435 }
436
437 /*
438 * This function writes the command buffer address to the hardware and
439 * enables it.
440 */
441 static void iommu_enable_command_buffer(struct amd_iommu *iommu)
442 {
443 u64 entry;
444
445 BUG_ON(iommu->cmd_buf == NULL);
446
447 entry = (u64)virt_to_phys(iommu->cmd_buf);
448 entry |= MMIO_CMD_SIZE_512;
449
450 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
451 &entry, sizeof(entry));
452
453 /* set head and tail to zero manually */
454 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
455 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
456
457 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
458 }
459
460 static void __init free_command_buffer(struct amd_iommu *iommu)
461 {
462 free_pages((unsigned long)iommu->cmd_buf,
463 get_order(iommu->cmd_buf_size));
464 }
465
466 /* allocates the memory where the IOMMU will log its events to */
467 static u8 * __init alloc_event_buffer(struct amd_iommu *iommu)
468 {
469 iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
470 get_order(EVT_BUFFER_SIZE));
471
472 if (iommu->evt_buf == NULL)
473 return NULL;
474
475 iommu->evt_buf_size = EVT_BUFFER_SIZE;
476
477 return iommu->evt_buf;
478 }
479
480 static void iommu_enable_event_buffer(struct amd_iommu *iommu)
481 {
482 u64 entry;
483
484 BUG_ON(iommu->evt_buf == NULL);
485
486 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
487
488 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
489 &entry, sizeof(entry));
490
491 /* set head and tail to zero manually */
492 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
493 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
494
495 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
496 }
497
498 static void __init free_event_buffer(struct amd_iommu *iommu)
499 {
500 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
501 }
502
503 /* sets a specific bit in the device table entry. */
504 static void set_dev_entry_bit(u16 devid, u8 bit)
505 {
506 int i = (bit >> 5) & 0x07;
507 int _bit = bit & 0x1f;
508
509 amd_iommu_dev_table[devid].data[i] |= (1 << _bit);
510 }
511
512 /* Writes the specific IOMMU for a device into the rlookup table */
513 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
514 {
515 amd_iommu_rlookup_table[devid] = iommu;
516 }
517
518 /*
519 * This function takes the device specific flags read from the ACPI
520 * table and sets up the device table entry with that information
521 */
522 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
523 u16 devid, u32 flags, u32 ext_flags)
524 {
525 if (flags & ACPI_DEVFLAG_INITPASS)
526 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
527 if (flags & ACPI_DEVFLAG_EXTINT)
528 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
529 if (flags & ACPI_DEVFLAG_NMI)
530 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
531 if (flags & ACPI_DEVFLAG_SYSMGT1)
532 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
533 if (flags & ACPI_DEVFLAG_SYSMGT2)
534 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
535 if (flags & ACPI_DEVFLAG_LINT0)
536 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
537 if (flags & ACPI_DEVFLAG_LINT1)
538 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
539
540 set_iommu_for_device(iommu, devid);
541 }
542
543 /*
544 * Reads the device exclusion range from ACPI and initialize IOMMU with
545 * it
546 */
547 static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
548 {
549 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
550
551 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
552 return;
553
554 if (iommu) {
555 /*
556 * We only can configure exclusion ranges per IOMMU, not
557 * per device. But we can enable the exclusion range per
558 * device. This is done here
559 */
560 set_dev_entry_bit(m->devid, DEV_ENTRY_EX);
561 iommu->exclusion_start = m->range_start;
562 iommu->exclusion_length = m->range_length;
563 }
564 }
565
566 /*
567 * This function reads some important data from the IOMMU PCI space and
568 * initializes the driver data structure with it. It reads the hardware
569 * capabilities and the first/last device entries
570 */
571 static void __init init_iommu_from_pci(struct amd_iommu *iommu)
572 {
573 int cap_ptr = iommu->cap_ptr;
574 u32 range, misc;
575
576 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
577 &iommu->cap);
578 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
579 &range);
580 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
581 &misc);
582
583 iommu->first_device = calc_devid(MMIO_GET_BUS(range),
584 MMIO_GET_FD(range));
585 iommu->last_device = calc_devid(MMIO_GET_BUS(range),
586 MMIO_GET_LD(range));
587 iommu->evt_msi_num = MMIO_MSI_NUM(misc);
588 }
589
590 /*
591 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
592 * initializes the hardware and our data structures with it.
593 */
594 static void __init init_iommu_from_acpi(struct amd_iommu *iommu,
595 struct ivhd_header *h)
596 {
597 u8 *p = (u8 *)h;
598 u8 *end = p, flags = 0;
599 u16 dev_i, devid = 0, devid_start = 0, devid_to = 0;
600 u32 ext_flags = 0;
601 bool alias = false;
602 struct ivhd_entry *e;
603
604 /*
605 * First set the recommended feature enable bits from ACPI
606 * into the IOMMU control registers
607 */
608 h->flags & IVHD_FLAG_HT_TUN_EN_MASK ?
609 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
610 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
611
612 h->flags & IVHD_FLAG_PASSPW_EN_MASK ?
613 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
614 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
615
616 h->flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
617 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
618 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
619
620 h->flags & IVHD_FLAG_ISOC_EN_MASK ?
621 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
622 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
623
624 /*
625 * make IOMMU memory accesses cache coherent
626 */
627 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
628
629 /*
630 * Done. Now parse the device entries
631 */
632 p += sizeof(struct ivhd_header);
633 end += h->length;
634
635
636 while (p < end) {
637 e = (struct ivhd_entry *)p;
638 switch (e->type) {
639 case IVHD_DEV_ALL:
640
641 DUMP_printk(" DEV_ALL\t\t\t first devid: %02x:%02x.%x"
642 " last device %02x:%02x.%x flags: %02x\n",
643 PCI_BUS(iommu->first_device),
644 PCI_SLOT(iommu->first_device),
645 PCI_FUNC(iommu->first_device),
646 PCI_BUS(iommu->last_device),
647 PCI_SLOT(iommu->last_device),
648 PCI_FUNC(iommu->last_device),
649 e->flags);
650
651 for (dev_i = iommu->first_device;
652 dev_i <= iommu->last_device; ++dev_i)
653 set_dev_entry_from_acpi(iommu, dev_i,
654 e->flags, 0);
655 break;
656 case IVHD_DEV_SELECT:
657
658 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
659 "flags: %02x\n",
660 PCI_BUS(e->devid),
661 PCI_SLOT(e->devid),
662 PCI_FUNC(e->devid),
663 e->flags);
664
665 devid = e->devid;
666 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
667 break;
668 case IVHD_DEV_SELECT_RANGE_START:
669
670 DUMP_printk(" DEV_SELECT_RANGE_START\t "
671 "devid: %02x:%02x.%x flags: %02x\n",
672 PCI_BUS(e->devid),
673 PCI_SLOT(e->devid),
674 PCI_FUNC(e->devid),
675 e->flags);
676
677 devid_start = e->devid;
678 flags = e->flags;
679 ext_flags = 0;
680 alias = false;
681 break;
682 case IVHD_DEV_ALIAS:
683
684 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
685 "flags: %02x devid_to: %02x:%02x.%x\n",
686 PCI_BUS(e->devid),
687 PCI_SLOT(e->devid),
688 PCI_FUNC(e->devid),
689 e->flags,
690 PCI_BUS(e->ext >> 8),
691 PCI_SLOT(e->ext >> 8),
692 PCI_FUNC(e->ext >> 8));
693
694 devid = e->devid;
695 devid_to = e->ext >> 8;
696 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
697 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
698 amd_iommu_alias_table[devid] = devid_to;
699 break;
700 case IVHD_DEV_ALIAS_RANGE:
701
702 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
703 "devid: %02x:%02x.%x flags: %02x "
704 "devid_to: %02x:%02x.%x\n",
705 PCI_BUS(e->devid),
706 PCI_SLOT(e->devid),
707 PCI_FUNC(e->devid),
708 e->flags,
709 PCI_BUS(e->ext >> 8),
710 PCI_SLOT(e->ext >> 8),
711 PCI_FUNC(e->ext >> 8));
712
713 devid_start = e->devid;
714 flags = e->flags;
715 devid_to = e->ext >> 8;
716 ext_flags = 0;
717 alias = true;
718 break;
719 case IVHD_DEV_EXT_SELECT:
720
721 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
722 "flags: %02x ext: %08x\n",
723 PCI_BUS(e->devid),
724 PCI_SLOT(e->devid),
725 PCI_FUNC(e->devid),
726 e->flags, e->ext);
727
728 devid = e->devid;
729 set_dev_entry_from_acpi(iommu, devid, e->flags,
730 e->ext);
731 break;
732 case IVHD_DEV_EXT_SELECT_RANGE:
733
734 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
735 "%02x:%02x.%x flags: %02x ext: %08x\n",
736 PCI_BUS(e->devid),
737 PCI_SLOT(e->devid),
738 PCI_FUNC(e->devid),
739 e->flags, e->ext);
740
741 devid_start = e->devid;
742 flags = e->flags;
743 ext_flags = e->ext;
744 alias = false;
745 break;
746 case IVHD_DEV_RANGE_END:
747
748 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
749 PCI_BUS(e->devid),
750 PCI_SLOT(e->devid),
751 PCI_FUNC(e->devid));
752
753 devid = e->devid;
754 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
755 if (alias) {
756 amd_iommu_alias_table[dev_i] = devid_to;
757 set_dev_entry_from_acpi(iommu,
758 devid_to, flags, ext_flags);
759 }
760 set_dev_entry_from_acpi(iommu, dev_i,
761 flags, ext_flags);
762 }
763 break;
764 default:
765 break;
766 }
767
768 p += ivhd_entry_length(p);
769 }
770 }
771
772 /* Initializes the device->iommu mapping for the driver */
773 static int __init init_iommu_devices(struct amd_iommu *iommu)
774 {
775 u16 i;
776
777 for (i = iommu->first_device; i <= iommu->last_device; ++i)
778 set_iommu_for_device(iommu, i);
779
780 return 0;
781 }
782
783 static void __init free_iommu_one(struct amd_iommu *iommu)
784 {
785 free_command_buffer(iommu);
786 free_event_buffer(iommu);
787 iommu_unmap_mmio_space(iommu);
788 }
789
790 static void __init free_iommu_all(void)
791 {
792 struct amd_iommu *iommu, *next;
793
794 for_each_iommu_safe(iommu, next) {
795 list_del(&iommu->list);
796 free_iommu_one(iommu);
797 kfree(iommu);
798 }
799 }
800
801 /*
802 * This function clues the initialization function for one IOMMU
803 * together and also allocates the command buffer and programs the
804 * hardware. It does NOT enable the IOMMU. This is done afterwards.
805 */
806 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
807 {
808 spin_lock_init(&iommu->lock);
809 list_add_tail(&iommu->list, &amd_iommu_list);
810
811 /*
812 * Copy data from ACPI table entry to the iommu struct
813 */
814 iommu->dev = pci_get_bus_and_slot(PCI_BUS(h->devid), h->devid & 0xff);
815 if (!iommu->dev)
816 return 1;
817
818 iommu->cap_ptr = h->cap_ptr;
819 iommu->pci_seg = h->pci_seg;
820 iommu->mmio_phys = h->mmio_phys;
821 iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys);
822 if (!iommu->mmio_base)
823 return -ENOMEM;
824
825 iommu->cmd_buf = alloc_command_buffer(iommu);
826 if (!iommu->cmd_buf)
827 return -ENOMEM;
828
829 iommu->evt_buf = alloc_event_buffer(iommu);
830 if (!iommu->evt_buf)
831 return -ENOMEM;
832
833 iommu->int_enabled = false;
834
835 init_iommu_from_pci(iommu);
836 init_iommu_from_acpi(iommu, h);
837 init_iommu_devices(iommu);
838
839 return pci_enable_device(iommu->dev);
840 }
841
842 /*
843 * Iterates over all IOMMU entries in the ACPI table, allocates the
844 * IOMMU structure and initializes it with init_iommu_one()
845 */
846 static int __init init_iommu_all(struct acpi_table_header *table)
847 {
848 u8 *p = (u8 *)table, *end = (u8 *)table;
849 struct ivhd_header *h;
850 struct amd_iommu *iommu;
851 int ret;
852
853 end += table->length;
854 p += IVRS_HEADER_LENGTH;
855
856 while (p < end) {
857 h = (struct ivhd_header *)p;
858 switch (*p) {
859 case ACPI_IVHD_TYPE:
860
861 DUMP_printk("IOMMU: device: %02x:%02x.%01x cap: %04x "
862 "seg: %d flags: %01x info %04x\n",
863 PCI_BUS(h->devid), PCI_SLOT(h->devid),
864 PCI_FUNC(h->devid), h->cap_ptr,
865 h->pci_seg, h->flags, h->info);
866 DUMP_printk(" mmio-addr: %016llx\n",
867 h->mmio_phys);
868
869 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
870 if (iommu == NULL)
871 return -ENOMEM;
872 ret = init_iommu_one(iommu, h);
873 if (ret)
874 return ret;
875 break;
876 default:
877 break;
878 }
879 p += h->length;
880
881 }
882 WARN_ON(p != end);
883
884 return 0;
885 }
886
887 /****************************************************************************
888 *
889 * The following functions initialize the MSI interrupts for all IOMMUs
890 * in the system. Its a bit challenging because there could be multiple
891 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
892 * pci_dev.
893 *
894 ****************************************************************************/
895
896 static int __init iommu_setup_msi(struct amd_iommu *iommu)
897 {
898 int r;
899
900 if (pci_enable_msi(iommu->dev))
901 return 1;
902
903 r = request_irq(iommu->dev->irq, amd_iommu_int_handler,
904 IRQF_SAMPLE_RANDOM,
905 "AMD IOMMU",
906 NULL);
907
908 if (r) {
909 pci_disable_msi(iommu->dev);
910 return 1;
911 }
912
913 iommu->int_enabled = true;
914 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
915
916 return 0;
917 }
918
919 static int iommu_init_msi(struct amd_iommu *iommu)
920 {
921 if (iommu->int_enabled)
922 return 0;
923
924 if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI))
925 return iommu_setup_msi(iommu);
926
927 return 1;
928 }
929
930 /****************************************************************************
931 *
932 * The next functions belong to the third pass of parsing the ACPI
933 * table. In this last pass the memory mapping requirements are
934 * gathered (like exclusion and unity mapping reanges).
935 *
936 ****************************************************************************/
937
938 static void __init free_unity_maps(void)
939 {
940 struct unity_map_entry *entry, *next;
941
942 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
943 list_del(&entry->list);
944 kfree(entry);
945 }
946 }
947
948 /* called when we find an exclusion range definition in ACPI */
949 static int __init init_exclusion_range(struct ivmd_header *m)
950 {
951 int i;
952
953 switch (m->type) {
954 case ACPI_IVMD_TYPE:
955 set_device_exclusion_range(m->devid, m);
956 break;
957 case ACPI_IVMD_TYPE_ALL:
958 for (i = 0; i <= amd_iommu_last_bdf; ++i)
959 set_device_exclusion_range(i, m);
960 break;
961 case ACPI_IVMD_TYPE_RANGE:
962 for (i = m->devid; i <= m->aux; ++i)
963 set_device_exclusion_range(i, m);
964 break;
965 default:
966 break;
967 }
968
969 return 0;
970 }
971
972 /* called for unity map ACPI definition */
973 static int __init init_unity_map_range(struct ivmd_header *m)
974 {
975 struct unity_map_entry *e = 0;
976 char *s;
977
978 e = kzalloc(sizeof(*e), GFP_KERNEL);
979 if (e == NULL)
980 return -ENOMEM;
981
982 switch (m->type) {
983 default:
984 kfree(e);
985 return 0;
986 case ACPI_IVMD_TYPE:
987 s = "IVMD_TYPEi\t\t\t";
988 e->devid_start = e->devid_end = m->devid;
989 break;
990 case ACPI_IVMD_TYPE_ALL:
991 s = "IVMD_TYPE_ALL\t\t";
992 e->devid_start = 0;
993 e->devid_end = amd_iommu_last_bdf;
994 break;
995 case ACPI_IVMD_TYPE_RANGE:
996 s = "IVMD_TYPE_RANGE\t\t";
997 e->devid_start = m->devid;
998 e->devid_end = m->aux;
999 break;
1000 }
1001 e->address_start = PAGE_ALIGN(m->range_start);
1002 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
1003 e->prot = m->flags >> 1;
1004
1005 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1006 " range_start: %016llx range_end: %016llx flags: %x\n", s,
1007 PCI_BUS(e->devid_start), PCI_SLOT(e->devid_start),
1008 PCI_FUNC(e->devid_start), PCI_BUS(e->devid_end),
1009 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
1010 e->address_start, e->address_end, m->flags);
1011
1012 list_add_tail(&e->list, &amd_iommu_unity_map);
1013
1014 return 0;
1015 }
1016
1017 /* iterates over all memory definitions we find in the ACPI table */
1018 static int __init init_memory_definitions(struct acpi_table_header *table)
1019 {
1020 u8 *p = (u8 *)table, *end = (u8 *)table;
1021 struct ivmd_header *m;
1022
1023 end += table->length;
1024 p += IVRS_HEADER_LENGTH;
1025
1026 while (p < end) {
1027 m = (struct ivmd_header *)p;
1028 if (m->flags & IVMD_FLAG_EXCL_RANGE)
1029 init_exclusion_range(m);
1030 else if (m->flags & IVMD_FLAG_UNITY_MAP)
1031 init_unity_map_range(m);
1032
1033 p += m->length;
1034 }
1035
1036 return 0;
1037 }
1038
1039 /*
1040 * Init the device table to not allow DMA access for devices and
1041 * suppress all page faults
1042 */
1043 static void init_device_table(void)
1044 {
1045 u16 devid;
1046
1047 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1048 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
1049 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
1050 }
1051 }
1052
1053 /*
1054 * This function finally enables all IOMMUs found in the system after
1055 * they have been initialized
1056 */
1057 static void enable_iommus(void)
1058 {
1059 struct amd_iommu *iommu;
1060
1061 for_each_iommu(iommu) {
1062 iommu_disable(iommu);
1063 iommu_set_device_table(iommu);
1064 iommu_enable_command_buffer(iommu);
1065 iommu_enable_event_buffer(iommu);
1066 iommu_set_exclusion_range(iommu);
1067 iommu_init_msi(iommu);
1068 iommu_enable(iommu);
1069 }
1070 }
1071
1072 static void disable_iommus(void)
1073 {
1074 struct amd_iommu *iommu;
1075
1076 for_each_iommu(iommu)
1077 iommu_disable(iommu);
1078 }
1079
1080 /*
1081 * Suspend/Resume support
1082 * disable suspend until real resume implemented
1083 */
1084
1085 static int amd_iommu_resume(struct sys_device *dev)
1086 {
1087 /* re-load the hardware */
1088 enable_iommus();
1089
1090 /*
1091 * we have to flush after the IOMMUs are enabled because a
1092 * disabled IOMMU will never execute the commands we send
1093 */
1094 amd_iommu_flush_all_devices();
1095 amd_iommu_flush_all_domains();
1096
1097 return 0;
1098 }
1099
1100 static int amd_iommu_suspend(struct sys_device *dev, pm_message_t state)
1101 {
1102 /* disable IOMMUs to go out of the way for BIOS */
1103 disable_iommus();
1104
1105 return 0;
1106 }
1107
1108 static struct sysdev_class amd_iommu_sysdev_class = {
1109 .name = "amd_iommu",
1110 .suspend = amd_iommu_suspend,
1111 .resume = amd_iommu_resume,
1112 };
1113
1114 static struct sys_device device_amd_iommu = {
1115 .id = 0,
1116 .cls = &amd_iommu_sysdev_class,
1117 };
1118
1119 /*
1120 * This is the core init function for AMD IOMMU hardware in the system.
1121 * This function is called from the generic x86 DMA layer initialization
1122 * code.
1123 *
1124 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
1125 * three times:
1126 *
1127 * 1 pass) Find the highest PCI device id the driver has to handle.
1128 * Upon this information the size of the data structures is
1129 * determined that needs to be allocated.
1130 *
1131 * 2 pass) Initialize the data structures just allocated with the
1132 * information in the ACPI table about available AMD IOMMUs
1133 * in the system. It also maps the PCI devices in the
1134 * system to specific IOMMUs
1135 *
1136 * 3 pass) After the basic data structures are allocated and
1137 * initialized we update them with information about memory
1138 * remapping requirements parsed out of the ACPI table in
1139 * this last pass.
1140 *
1141 * After that the hardware is initialized and ready to go. In the last
1142 * step we do some Linux specific things like registering the driver in
1143 * the dma_ops interface and initializing the suspend/resume support
1144 * functions. Finally it prints some information about AMD IOMMUs and
1145 * the driver state and enables the hardware.
1146 */
1147 int __init amd_iommu_init(void)
1148 {
1149 int i, ret = 0;
1150
1151
1152 if (no_iommu) {
1153 printk(KERN_INFO "AMD IOMMU disabled by kernel command line\n");
1154 return 0;
1155 }
1156
1157 if (!amd_iommu_detected)
1158 return -ENODEV;
1159
1160 /*
1161 * First parse ACPI tables to find the largest Bus/Dev/Func
1162 * we need to handle. Upon this information the shared data
1163 * structures for the IOMMUs in the system will be allocated
1164 */
1165 if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0)
1166 return -ENODEV;
1167
1168 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
1169 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
1170 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
1171
1172 ret = -ENOMEM;
1173
1174 /* Device table - directly used by all IOMMUs */
1175 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
1176 get_order(dev_table_size));
1177 if (amd_iommu_dev_table == NULL)
1178 goto out;
1179
1180 /*
1181 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
1182 * IOMMU see for that device
1183 */
1184 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
1185 get_order(alias_table_size));
1186 if (amd_iommu_alias_table == NULL)
1187 goto free;
1188
1189 /* IOMMU rlookup table - find the IOMMU for a specific device */
1190 amd_iommu_rlookup_table = (void *)__get_free_pages(
1191 GFP_KERNEL | __GFP_ZERO,
1192 get_order(rlookup_table_size));
1193 if (amd_iommu_rlookup_table == NULL)
1194 goto free;
1195
1196 /*
1197 * Protection Domain table - maps devices to protection domains
1198 * This table has the same size as the rlookup_table
1199 */
1200 amd_iommu_pd_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
1201 get_order(rlookup_table_size));
1202 if (amd_iommu_pd_table == NULL)
1203 goto free;
1204
1205 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
1206 GFP_KERNEL | __GFP_ZERO,
1207 get_order(MAX_DOMAIN_ID/8));
1208 if (amd_iommu_pd_alloc_bitmap == NULL)
1209 goto free;
1210
1211 /* init the device table */
1212 init_device_table();
1213
1214 /*
1215 * let all alias entries point to itself
1216 */
1217 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1218 amd_iommu_alias_table[i] = i;
1219
1220 /*
1221 * never allocate domain 0 because its used as the non-allocated and
1222 * error value placeholder
1223 */
1224 amd_iommu_pd_alloc_bitmap[0] = 1;
1225
1226 /*
1227 * now the data structures are allocated and basically initialized
1228 * start the real acpi table scan
1229 */
1230 ret = -ENODEV;
1231 if (acpi_table_parse("IVRS", init_iommu_all) != 0)
1232 goto free;
1233
1234 if (acpi_table_parse("IVRS", init_memory_definitions) != 0)
1235 goto free;
1236
1237 ret = sysdev_class_register(&amd_iommu_sysdev_class);
1238 if (ret)
1239 goto free;
1240
1241 ret = sysdev_register(&device_amd_iommu);
1242 if (ret)
1243 goto free;
1244
1245 ret = amd_iommu_init_dma_ops();
1246 if (ret)
1247 goto free;
1248
1249 enable_iommus();
1250
1251 printk(KERN_INFO "AMD IOMMU: device isolation ");
1252 if (amd_iommu_isolate)
1253 printk("enabled\n");
1254 else
1255 printk("disabled\n");
1256
1257 if (amd_iommu_unmap_flush)
1258 printk(KERN_INFO "AMD IOMMU: IO/TLB flush on unmap enabled\n");
1259 else
1260 printk(KERN_INFO "AMD IOMMU: Lazy IO/TLB flushing enabled\n");
1261
1262 out:
1263 return ret;
1264
1265 free:
1266 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
1267 get_order(MAX_DOMAIN_ID/8));
1268
1269 free_pages((unsigned long)amd_iommu_pd_table,
1270 get_order(rlookup_table_size));
1271
1272 free_pages((unsigned long)amd_iommu_rlookup_table,
1273 get_order(rlookup_table_size));
1274
1275 free_pages((unsigned long)amd_iommu_alias_table,
1276 get_order(alias_table_size));
1277
1278 free_pages((unsigned long)amd_iommu_dev_table,
1279 get_order(dev_table_size));
1280
1281 free_iommu_all();
1282
1283 free_unity_maps();
1284
1285 goto out;
1286 }
1287
1288 void amd_iommu_shutdown(void)
1289 {
1290 disable_iommus();
1291 }
1292
1293 /****************************************************************************
1294 *
1295 * Early detect code. This code runs at IOMMU detection time in the DMA
1296 * layer. It just looks if there is an IVRS ACPI table to detect AMD
1297 * IOMMUs
1298 *
1299 ****************************************************************************/
1300 static int __init early_amd_iommu_detect(struct acpi_table_header *table)
1301 {
1302 return 0;
1303 }
1304
1305 void __init amd_iommu_detect(void)
1306 {
1307 if (swiotlb || no_iommu || (iommu_detected && !gart_iommu_aperture))
1308 return;
1309
1310 if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) {
1311 iommu_detected = 1;
1312 amd_iommu_detected = 1;
1313 #ifdef CONFIG_GART_IOMMU
1314 gart_iommu_aperture_disabled = 1;
1315 gart_iommu_aperture = 0;
1316 #endif
1317 }
1318 }
1319
1320 /****************************************************************************
1321 *
1322 * Parsing functions for the AMD IOMMU specific kernel command line
1323 * options.
1324 *
1325 ****************************************************************************/
1326
1327 static int __init parse_amd_iommu_dump(char *str)
1328 {
1329 amd_iommu_dump = true;
1330
1331 return 1;
1332 }
1333
1334 static int __init parse_amd_iommu_options(char *str)
1335 {
1336 for (; *str; ++str) {
1337 if (strncmp(str, "isolate", 7) == 0)
1338 amd_iommu_isolate = true;
1339 if (strncmp(str, "share", 5) == 0)
1340 amd_iommu_isolate = false;
1341 if (strncmp(str, "fullflush", 9) == 0)
1342 amd_iommu_unmap_flush = true;
1343 }
1344
1345 return 1;
1346 }
1347
1348 __setup("amd_iommu_dump", parse_amd_iommu_dump);
1349 __setup("amd_iommu=", parse_amd_iommu_options);
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