drivers/pci/pcie/aer/aerdrv.h

   1 /*
   2  * Copyright (C) 2006 Intel Corp.
   3  *      Tom Long Nguyen (tom.l.nguyen@intel.com)
   4  *      Zhang Yanmin (yanmin.zhang@intel.com)
   5  *
   6  */
   7
   8 #ifndef _AERDRV_H_
   9 #define _AERDRV_H_
  10
  11 #include <linux/workqueue.h>
  12 #include <linux/pcieport_if.h>
  13 #include <linux/aer.h>
  14 #include <linux/interrupt.h>
  15
  16 #define AER_NONFATAL                    0
  17 #define AER_FATAL                       1
  18 #define AER_CORRECTABLE                 2
  19 #define AER_UNCORRECTABLE               4
  20 #define AER_ERROR_MASK                  0x001fffff
  21 #define AER_ERROR(d)                    (d & AER_ERROR_MASK)
  22
  23 /* Root Error Status Register Bits */
  24 #define ROOT_ERR_STATUS_MASKS                   0x0f
  25
  26 #define SYSTEM_ERROR_INTR_ON_MESG_MASK  (PCI_EXP_RTCTL_SECEE|   \
  27                                         PCI_EXP_RTCTL_SENFEE|   \
  28                                         PCI_EXP_RTCTL_SEFEE)
  29 #define ROOT_PORT_INTR_ON_MESG_MASK     (PCI_ERR_ROOT_CMD_COR_EN|       \
  30                                         PCI_ERR_ROOT_CMD_NONFATAL_EN|   \
  31                                         PCI_ERR_ROOT_CMD_FATAL_EN)
  32 #define ERR_COR_ID(d)                   (d & 0xffff)
  33 #define ERR_UNCOR_ID(d)                 (d >> 16)
  34
  35 #define AER_SUCCESS                     0
  36 #define AER_UNSUCCESS                   1
  37 #define AER_ERROR_SOURCES_MAX           100
  38
  39 #define AER_LOG_TLP_MASKS               (PCI_ERR_UNC_POISON_TLP|        \
  40                                         PCI_ERR_UNC_ECRC|               \
  41                                         PCI_ERR_UNC_UNSUP|              \
  42                                         PCI_ERR_UNC_COMP_ABORT|         \
  43                                         PCI_ERR_UNC_UNX_COMP|           \
  44                                         PCI_ERR_UNC_MALF_TLP)
  45
  46 /* AER Error Info Flags */
  47 #define AER_TLP_HEADER_VALID_FLAG       0x00000001
  48 #define AER_MULTI_ERROR_VALID_FLAG      0x00000002
  49
  50 #define ERR_CORRECTABLE_ERROR_MASK      0x000031c1
  51 #define ERR_UNCORRECTABLE_ERROR_MASK    0x001ff010
  52
  53 struct header_log_regs {
  54         unsigned int dw0;
  55         unsigned int dw1;
  56         unsigned int dw2;
  57         unsigned int dw3;
  58 };
  59
  60 #define AER_MAX_MULTI_ERR_DEVICES       5       /* Not likely to have more */
  61 struct aer_err_info {
  62         struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
  63         int error_dev_num;
  64         u16 id;
  65         int severity;                   /* 0:NONFATAL | 1:FATAL | 2:COR */
  66         int flags;
  67         unsigned int status;            /* COR/UNCOR Error Status */
  68         struct header_log_regs tlp;     /* TLP Header */
  69 };
  70
  71 struct aer_err_source {
  72         unsigned int status;
  73         unsigned int id;
  74 };
  75
  76 struct aer_rpc {
  77         struct pcie_device *rpd;        /* Root Port device */
  78         struct work_struct dpc_handler;
  79         struct aer_err_source e_sources[AER_ERROR_SOURCES_MAX];
  80         unsigned short prod_idx;        /* Error Producer Index */
  81         unsigned short cons_idx;        /* Error Consumer Index */
  82         int isr;
  83         spinlock_t e_lock;              /*
  84                                          * Lock access to Error Status/ID Regs
  85                                          * and error producer/consumer index
  86                                          */
  87         struct mutex rpc_mutex;         /*
  88                                          * only one thread could do
  89                                          * recovery on the same
  90                                          * root port hierarchy
  91                                          */
  92         wait_queue_head_t wait_release;
  93 };
  94
  95 struct aer_broadcast_data {
  96         enum pci_channel_state state;
  97         enum pci_ers_result result;
  98 };
  99
 100 static inline pci_ers_result_t merge_result(enum pci_ers_result orig,
 101                 enum pci_ers_result new)
 102 {
 103         if (new == PCI_ERS_RESULT_NONE)
 104                 return orig;
 105
 106         switch (orig) {
 107         case PCI_ERS_RESULT_CAN_RECOVER:
 108         case PCI_ERS_RESULT_RECOVERED:
 109                 orig = new;
 110                 break;
 111         case PCI_ERS_RESULT_DISCONNECT:
 112                 if (new == PCI_ERS_RESULT_NEED_RESET)
 113                         orig = new;
 114                 break;
 115         default:
 116                 break;
 117         }
 118
 119         return orig;
 120 }
 121
 122 extern struct bus_type pcie_port_bus_type;
 123 extern void aer_enable_rootport(struct aer_rpc *rpc);
 124 extern void aer_delete_rootport(struct aer_rpc *rpc);
 125 extern int aer_init(struct pcie_device *dev);
 126 extern void aer_isr(struct work_struct *work);
 127 extern void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
 128 extern irqreturn_t aer_irq(int irq, void *context);
 129
 130 #ifdef CONFIG_ACPI
 131 extern int aer_osc_setup(struct pcie_device *pciedev);
 132 #else
 133 static inline int aer_osc_setup(struct pcie_device *pciedev)
 134 {
 135         return 0;
 136 }
 137 #endif
 138
 139 #endif //_AERDRV_H_