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ACPI: pci_root: simplify list traversals
[linux-2.6/linux-acpi-2.6.git] / drivers / serial / 8250.c
bloba0127e93ade0a424c6125383150dd342e61710fc
1 /*
2 * linux/drivers/char/8250.c
3 *
4 * Driver for 8250/16550-type serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * A note about mapbase / membase
16 *
17 * mapbase is the physical address of the IO port.
18 * membase is an 'ioremapped' cookie.
19 */
20
21 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22 #define SUPPORT_SYSRQ
23 #endif
24
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/ioport.h>
28 #include <linux/init.h>
29 #include <linux/console.h>
30 #include <linux/sysrq.h>
31 #include <linux/delay.h>
32 #include <linux/platform_device.h>
33 #include <linux/tty.h>
34 #include <linux/tty_flip.h>
35 #include <linux/serial_reg.h>
36 #include <linux/serial_core.h>
37 #include <linux/serial.h>
38 #include <linux/serial_8250.h>
39 #include <linux/nmi.h>
40 #include <linux/mutex.h>
41
42 #include <asm/io.h>
43 #include <asm/irq.h>
44
45 #include "8250.h"
46
47 #ifdef CONFIG_SPARC
48 #include "suncore.h"
49 #endif
50
51 /*
52 * Configuration:
53 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
54 * is unsafe when used on edge-triggered interrupts.
55 */
56 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
57
58 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
59
60 static struct uart_driver serial8250_reg;
61
62 static int serial_index(struct uart_port *port)
63 {
64 return (serial8250_reg.minor - 64) + port->line;
65 }
66
67 /*
68 * Debugging.
69 */
70 #if 0
71 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
72 #else
73 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
74 #endif
75
76 #if 0
77 #define DEBUG_INTR(fmt...) printk(fmt)
78 #else
79 #define DEBUG_INTR(fmt...) do { } while (0)
80 #endif
81
82 #define PASS_LIMIT 256
83
84 /*
85 * We default to IRQ0 for the "no irq" hack. Some
86 * machine types want others as well - they're free
87 * to redefine this in their header file.
88 */
89 #define is_real_interrupt(irq) ((irq) != 0)
90
91 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
92 #define CONFIG_SERIAL_DETECT_IRQ 1
93 #endif
94 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
95 #define CONFIG_SERIAL_MANY_PORTS 1
96 #endif
97
98 /*
99 * HUB6 is always on. This will be removed once the header
100 * files have been cleaned.
101 */
102 #define CONFIG_HUB6 1
103
104 #include <asm/serial.h>
105 /*
106 * SERIAL_PORT_DFNS tells us about built-in ports that have no
107 * standard enumeration mechanism. Platforms that can find all
108 * serial ports via mechanisms like ACPI or PCI need not supply it.
109 */
110 #ifndef SERIAL_PORT_DFNS
111 #define SERIAL_PORT_DFNS
112 #endif
113
114 static const struct old_serial_port old_serial_port[] = {
115 SERIAL_PORT_DFNS /* defined in asm/serial.h */
116 };
117
118 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
119
120 #ifdef CONFIG_SERIAL_8250_RSA
121
122 #define PORT_RSA_MAX 4
123 static unsigned long probe_rsa[PORT_RSA_MAX];
124 static unsigned int probe_rsa_count;
125 #endif /* CONFIG_SERIAL_8250_RSA */
126
127 struct uart_8250_port {
128 struct uart_port port;
129 struct timer_list timer; /* "no irq" timer */
130 struct list_head list; /* ports on this IRQ */
131 unsigned short capabilities; /* port capabilities */
132 unsigned short bugs; /* port bugs */
133 unsigned int tx_loadsz; /* transmit fifo load size */
134 unsigned char acr;
135 unsigned char ier;
136 unsigned char lcr;
137 unsigned char mcr;
138 unsigned char mcr_mask; /* mask of user bits */
139 unsigned char mcr_force; /* mask of forced bits */
140 unsigned char cur_iotype; /* Running I/O type */
141
142 /*
143 * Some bits in registers are cleared on a read, so they must
144 * be saved whenever the register is read but the bits will not
145 * be immediately processed.
146 */
147 #define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
148 unsigned char lsr_saved_flags;
149 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
150 unsigned char msr_saved_flags;
151
152 /*
153 * We provide a per-port pm hook.
154 */
155 void (*pm)(struct uart_port *port,
156 unsigned int state, unsigned int old);
157 };
158
159 struct irq_info {
160 struct hlist_node node;
161 int irq;
162 spinlock_t lock; /* Protects list not the hash */
163 struct list_head *head;
164 };
165
166 #define NR_IRQ_HASH 32 /* Can be adjusted later */
167 static struct hlist_head irq_lists[NR_IRQ_HASH];
168 static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
169
170 /*
171 * Here we define the default xmit fifo size used for each type of UART.
172 */
173 static const struct serial8250_config uart_config[] = {
174 [PORT_UNKNOWN] = {
175 .name = "unknown",
176 .fifo_size = 1,
177 .tx_loadsz = 1,
178 },
179 [PORT_8250] = {
180 .name = "8250",
181 .fifo_size = 1,
182 .tx_loadsz = 1,
183 },
184 [PORT_16450] = {
185 .name = "16450",
186 .fifo_size = 1,
187 .tx_loadsz = 1,
188 },
189 [PORT_16550] = {
190 .name = "16550",
191 .fifo_size = 1,
192 .tx_loadsz = 1,
193 },
194 [PORT_16550A] = {
195 .name = "16550A",
196 .fifo_size = 16,
197 .tx_loadsz = 16,
198 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
199 .flags = UART_CAP_FIFO,
200 },
201 [PORT_CIRRUS] = {
202 .name = "Cirrus",
203 .fifo_size = 1,
204 .tx_loadsz = 1,
205 },
206 [PORT_16650] = {
207 .name = "ST16650",
208 .fifo_size = 1,
209 .tx_loadsz = 1,
210 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
211 },
212 [PORT_16650V2] = {
213 .name = "ST16650V2",
214 .fifo_size = 32,
215 .tx_loadsz = 16,
216 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
217 UART_FCR_T_TRIG_00,
218 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
219 },
220 [PORT_16750] = {
221 .name = "TI16750",
222 .fifo_size = 64,
223 .tx_loadsz = 64,
224 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
225 UART_FCR7_64BYTE,
226 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
227 },
228 [PORT_STARTECH] = {
229 .name = "Startech",
230 .fifo_size = 1,
231 .tx_loadsz = 1,
232 },
233 [PORT_16C950] = {
234 .name = "16C950/954",
235 .fifo_size = 128,
236 .tx_loadsz = 128,
237 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
238 .flags = UART_CAP_FIFO,
239 },
240 [PORT_16654] = {
241 .name = "ST16654",
242 .fifo_size = 64,
243 .tx_loadsz = 32,
244 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
245 UART_FCR_T_TRIG_10,
246 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
247 },
248 [PORT_16850] = {
249 .name = "XR16850",
250 .fifo_size = 128,
251 .tx_loadsz = 128,
252 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
253 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
254 },
255 [PORT_RSA] = {
256 .name = "RSA",
257 .fifo_size = 2048,
258 .tx_loadsz = 2048,
259 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
260 .flags = UART_CAP_FIFO,
261 },
262 [PORT_NS16550A] = {
263 .name = "NS16550A",
264 .fifo_size = 16,
265 .tx_loadsz = 16,
266 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
267 .flags = UART_CAP_FIFO | UART_NATSEMI,
268 },
269 [PORT_XSCALE] = {
270 .name = "XScale",
271 .fifo_size = 32,
272 .tx_loadsz = 32,
273 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
274 .flags = UART_CAP_FIFO | UART_CAP_UUE,
275 },
276 [PORT_RM9000] = {
277 .name = "RM9000",
278 .fifo_size = 16,
279 .tx_loadsz = 16,
280 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
281 .flags = UART_CAP_FIFO,
282 },
283 [PORT_OCTEON] = {
284 .name = "OCTEON",
285 .fifo_size = 64,
286 .tx_loadsz = 64,
287 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
288 .flags = UART_CAP_FIFO,
289 },
290 };
291
292 #if defined (CONFIG_SERIAL_8250_AU1X00)
293
294 /* Au1x00 UART hardware has a weird register layout */
295 static const u8 au_io_in_map[] = {
296 [UART_RX] = 0,
297 [UART_IER] = 2,
298 [UART_IIR] = 3,
299 [UART_LCR] = 5,
300 [UART_MCR] = 6,
301 [UART_LSR] = 7,
302 [UART_MSR] = 8,
303 };
304
305 static const u8 au_io_out_map[] = {
306 [UART_TX] = 1,
307 [UART_IER] = 2,
308 [UART_FCR] = 4,
309 [UART_LCR] = 5,
310 [UART_MCR] = 6,
311 };
312
313 /* sane hardware needs no mapping */
314 static inline int map_8250_in_reg(struct uart_port *p, int offset)
315 {
316 if (p->iotype != UPIO_AU)
317 return offset;
318 return au_io_in_map[offset];
319 }
320
321 static inline int map_8250_out_reg(struct uart_port *p, int offset)
322 {
323 if (p->iotype != UPIO_AU)
324 return offset;
325 return au_io_out_map[offset];
326 }
327
328 #elif defined(CONFIG_SERIAL_8250_RM9K)
329
330 static const u8
331 regmap_in[8] = {
332 [UART_RX] = 0x00,
333 [UART_IER] = 0x0c,
334 [UART_IIR] = 0x14,
335 [UART_LCR] = 0x1c,
336 [UART_MCR] = 0x20,
337 [UART_LSR] = 0x24,
338 [UART_MSR] = 0x28,
339 [UART_SCR] = 0x2c
340 },
341 regmap_out[8] = {
342 [UART_TX] = 0x04,
343 [UART_IER] = 0x0c,
344 [UART_FCR] = 0x18,
345 [UART_LCR] = 0x1c,
346 [UART_MCR] = 0x20,
347 [UART_LSR] = 0x24,
348 [UART_MSR] = 0x28,
349 [UART_SCR] = 0x2c
350 };
351
352 static inline int map_8250_in_reg(struct uart_port *p, int offset)
353 {
354 if (p->iotype != UPIO_RM9000)
355 return offset;
356 return regmap_in[offset];
357 }
358
359 static inline int map_8250_out_reg(struct uart_port *p, int offset)
360 {
361 if (p->iotype != UPIO_RM9000)
362 return offset;
363 return regmap_out[offset];
364 }
365
366 #else
367
368 /* sane hardware needs no mapping */
369 #define map_8250_in_reg(up, offset) (offset)
370 #define map_8250_out_reg(up, offset) (offset)
371
372 #endif
373
374 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
375 {
376 offset = map_8250_in_reg(p, offset) << p->regshift;
377 outb(p->hub6 - 1 + offset, p->iobase);
378 return inb(p->iobase + 1);
379 }
380
381 static void hub6_serial_out(struct uart_port *p, int offset, int value)
382 {
383 offset = map_8250_out_reg(p, offset) << p->regshift;
384 outb(p->hub6 - 1 + offset, p->iobase);
385 outb(value, p->iobase + 1);
386 }
387
388 static unsigned int mem_serial_in(struct uart_port *p, int offset)
389 {
390 offset = map_8250_in_reg(p, offset) << p->regshift;
391 return readb(p->membase + offset);
392 }
393
394 static void mem_serial_out(struct uart_port *p, int offset, int value)
395 {
396 offset = map_8250_out_reg(p, offset) << p->regshift;
397 writeb(value, p->membase + offset);
398 }
399
400 static void mem32_serial_out(struct uart_port *p, int offset, int value)
401 {
402 offset = map_8250_out_reg(p, offset) << p->regshift;
403 writel(value, p->membase + offset);
404 }
405
406 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
407 {
408 offset = map_8250_in_reg(p, offset) << p->regshift;
409 return readl(p->membase + offset);
410 }
411
412 #ifdef CONFIG_SERIAL_8250_AU1X00
413 static unsigned int au_serial_in(struct uart_port *p, int offset)
414 {
415 offset = map_8250_in_reg(p, offset) << p->regshift;
416 return __raw_readl(p->membase + offset);
417 }
418
419 static void au_serial_out(struct uart_port *p, int offset, int value)
420 {
421 offset = map_8250_out_reg(p, offset) << p->regshift;
422 __raw_writel(value, p->membase + offset);
423 }
424 #endif
425
426 static unsigned int tsi_serial_in(struct uart_port *p, int offset)
427 {
428 unsigned int tmp;
429 offset = map_8250_in_reg(p, offset) << p->regshift;
430 if (offset == UART_IIR) {
431 tmp = readl(p->membase + (UART_IIR & ~3));
432 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
433 } else
434 return readb(p->membase + offset);
435 }
436
437 static void tsi_serial_out(struct uart_port *p, int offset, int value)
438 {
439 offset = map_8250_out_reg(p, offset) << p->regshift;
440 if (!((offset == UART_IER) && (value & UART_IER_UUE)))
441 writeb(value, p->membase + offset);
442 }
443
444 static void dwapb_serial_out(struct uart_port *p, int offset, int value)
445 {
446 int save_offset = offset;
447 offset = map_8250_out_reg(p, offset) << p->regshift;
448 /* Save the LCR value so it can be re-written when a
449 * Busy Detect interrupt occurs. */
450 if (save_offset == UART_LCR) {
451 struct uart_8250_port *up = (struct uart_8250_port *)p;
452 up->lcr = value;
453 }
454 writeb(value, p->membase + offset);
455 /* Read the IER to ensure any interrupt is cleared before
456 * returning from ISR. */
457 if (save_offset == UART_TX || save_offset == UART_IER)
458 value = p->serial_in(p, UART_IER);
459 }
460
461 static unsigned int io_serial_in(struct uart_port *p, int offset)
462 {
463 offset = map_8250_in_reg(p, offset) << p->regshift;
464 return inb(p->iobase + offset);
465 }
466
467 static void io_serial_out(struct uart_port *p, int offset, int value)
468 {
469 offset = map_8250_out_reg(p, offset) << p->regshift;
470 outb(value, p->iobase + offset);
471 }
472
473 static void set_io_from_upio(struct uart_port *p)
474 {
475 struct uart_8250_port *up = (struct uart_8250_port *)p;
476 switch (p->iotype) {
477 case UPIO_HUB6:
478 p->serial_in = hub6_serial_in;
479 p->serial_out = hub6_serial_out;
480 break;
481
482 case UPIO_MEM:
483 p->serial_in = mem_serial_in;
484 p->serial_out = mem_serial_out;
485 break;
486
487 case UPIO_RM9000:
488 case UPIO_MEM32:
489 p->serial_in = mem32_serial_in;
490 p->serial_out = mem32_serial_out;
491 break;
492
493 #ifdef CONFIG_SERIAL_8250_AU1X00
494 case UPIO_AU:
495 p->serial_in = au_serial_in;
496 p->serial_out = au_serial_out;
497 break;
498 #endif
499 case UPIO_TSI:
500 p->serial_in = tsi_serial_in;
501 p->serial_out = tsi_serial_out;
502 break;
503
504 case UPIO_DWAPB:
505 p->serial_in = mem_serial_in;
506 p->serial_out = dwapb_serial_out;
507 break;
508
509 default:
510 p->serial_in = io_serial_in;
511 p->serial_out = io_serial_out;
512 break;
513 }
514 /* Remember loaded iotype */
515 up->cur_iotype = p->iotype;
516 }
517
518 static void
519 serial_out_sync(struct uart_8250_port *up, int offset, int value)
520 {
521 struct uart_port *p = &up->port;
522 switch (p->iotype) {
523 case UPIO_MEM:
524 case UPIO_MEM32:
525 #ifdef CONFIG_SERIAL_8250_AU1X00
526 case UPIO_AU:
527 #endif
528 case UPIO_DWAPB:
529 p->serial_out(p, offset, value);
530 p->serial_in(p, UART_LCR); /* safe, no side-effects */
531 break;
532 default:
533 p->serial_out(p, offset, value);
534 }
535 }
536
537 #define serial_in(up, offset) \
538 (up->port.serial_in(&(up)->port, (offset)))
539 #define serial_out(up, offset, value) \
540 (up->port.serial_out(&(up)->port, (offset), (value)))
541 /*
542 * We used to support using pause I/O for certain machines. We
543 * haven't supported this for a while, but just in case it's badly
544 * needed for certain old 386 machines, I've left these #define's
545 * in....
546 */
547 #define serial_inp(up, offset) serial_in(up, offset)
548 #define serial_outp(up, offset, value) serial_out(up, offset, value)
549
550 /* Uart divisor latch read */
551 static inline int _serial_dl_read(struct uart_8250_port *up)
552 {
553 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
554 }
555
556 /* Uart divisor latch write */
557 static inline void _serial_dl_write(struct uart_8250_port *up, int value)
558 {
559 serial_outp(up, UART_DLL, value & 0xff);
560 serial_outp(up, UART_DLM, value >> 8 & 0xff);
561 }
562
563 #if defined(CONFIG_SERIAL_8250_AU1X00)
564 /* Au1x00 haven't got a standard divisor latch */
565 static int serial_dl_read(struct uart_8250_port *up)
566 {
567 if (up->port.iotype == UPIO_AU)
568 return __raw_readl(up->port.membase + 0x28);
569 else
570 return _serial_dl_read(up);
571 }
572
573 static void serial_dl_write(struct uart_8250_port *up, int value)
574 {
575 if (up->port.iotype == UPIO_AU)
576 __raw_writel(value, up->port.membase + 0x28);
577 else
578 _serial_dl_write(up, value);
579 }
580 #elif defined(CONFIG_SERIAL_8250_RM9K)
581 static int serial_dl_read(struct uart_8250_port *up)
582 {
583 return (up->port.iotype == UPIO_RM9000) ?
584 (((__raw_readl(up->port.membase + 0x10) << 8) |
585 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
586 _serial_dl_read(up);
587 }
588
589 static void serial_dl_write(struct uart_8250_port *up, int value)
590 {
591 if (up->port.iotype == UPIO_RM9000) {
592 __raw_writel(value, up->port.membase + 0x08);
593 __raw_writel(value >> 8, up->port.membase + 0x10);
594 } else {
595 _serial_dl_write(up, value);
596 }
597 }
598 #else
599 #define serial_dl_read(up) _serial_dl_read(up)
600 #define serial_dl_write(up, value) _serial_dl_write(up, value)
601 #endif
602
603 /*
604 * For the 16C950
605 */
606 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
607 {
608 serial_out(up, UART_SCR, offset);
609 serial_out(up, UART_ICR, value);
610 }
611
612 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
613 {
614 unsigned int value;
615
616 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
617 serial_out(up, UART_SCR, offset);
618 value = serial_in(up, UART_ICR);
619 serial_icr_write(up, UART_ACR, up->acr);
620
621 return value;
622 }
623
624 /*
625 * FIFO support.
626 */
627 static void serial8250_clear_fifos(struct uart_8250_port *p)
628 {
629 if (p->capabilities & UART_CAP_FIFO) {
630 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
631 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
632 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
633 serial_outp(p, UART_FCR, 0);
634 }
635 }
636
637 /*
638 * IER sleep support. UARTs which have EFRs need the "extended
639 * capability" bit enabled. Note that on XR16C850s, we need to
640 * reset LCR to write to IER.
641 */
642 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
643 {
644 if (p->capabilities & UART_CAP_SLEEP) {
645 if (p->capabilities & UART_CAP_EFR) {
646 serial_outp(p, UART_LCR, 0xBF);
647 serial_outp(p, UART_EFR, UART_EFR_ECB);
648 serial_outp(p, UART_LCR, 0);
649 }
650 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
651 if (p->capabilities & UART_CAP_EFR) {
652 serial_outp(p, UART_LCR, 0xBF);
653 serial_outp(p, UART_EFR, 0);
654 serial_outp(p, UART_LCR, 0);
655 }
656 }
657 }
658
659 #ifdef CONFIG_SERIAL_8250_RSA
660 /*
661 * Attempts to turn on the RSA FIFO. Returns zero on failure.
662 * We set the port uart clock rate if we succeed.
663 */
664 static int __enable_rsa(struct uart_8250_port *up)
665 {
666 unsigned char mode;
667 int result;
668
669 mode = serial_inp(up, UART_RSA_MSR);
670 result = mode & UART_RSA_MSR_FIFO;
671
672 if (!result) {
673 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
674 mode = serial_inp(up, UART_RSA_MSR);
675 result = mode & UART_RSA_MSR_FIFO;
676 }
677
678 if (result)
679 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
680
681 return result;
682 }
683
684 static void enable_rsa(struct uart_8250_port *up)
685 {
686 if (up->port.type == PORT_RSA) {
687 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
688 spin_lock_irq(&up->port.lock);
689 __enable_rsa(up);
690 spin_unlock_irq(&up->port.lock);
691 }
692 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
693 serial_outp(up, UART_RSA_FRR, 0);
694 }
695 }
696
697 /*
698 * Attempts to turn off the RSA FIFO. Returns zero on failure.
699 * It is unknown why interrupts were disabled in here. However,
700 * the caller is expected to preserve this behaviour by grabbing
701 * the spinlock before calling this function.
702 */
703 static void disable_rsa(struct uart_8250_port *up)
704 {
705 unsigned char mode;
706 int result;
707
708 if (up->port.type == PORT_RSA &&
709 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
710 spin_lock_irq(&up->port.lock);
711
712 mode = serial_inp(up, UART_RSA_MSR);
713 result = !(mode & UART_RSA_MSR_FIFO);
714
715 if (!result) {
716 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
717 mode = serial_inp(up, UART_RSA_MSR);
718 result = !(mode & UART_RSA_MSR_FIFO);
719 }
720
721 if (result)
722 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
723 spin_unlock_irq(&up->port.lock);
724 }
725 }
726 #endif /* CONFIG_SERIAL_8250_RSA */
727
728 /*
729 * This is a quickie test to see how big the FIFO is.
730 * It doesn't work at all the time, more's the pity.
731 */
732 static int size_fifo(struct uart_8250_port *up)
733 {
734 unsigned char old_fcr, old_mcr, old_lcr;
735 unsigned short old_dl;
736 int count;
737
738 old_lcr = serial_inp(up, UART_LCR);
739 serial_outp(up, UART_LCR, 0);
740 old_fcr = serial_inp(up, UART_FCR);
741 old_mcr = serial_inp(up, UART_MCR);
742 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
743 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
744 serial_outp(up, UART_MCR, UART_MCR_LOOP);
745 serial_outp(up, UART_LCR, UART_LCR_DLAB);
746 old_dl = serial_dl_read(up);
747 serial_dl_write(up, 0x0001);
748 serial_outp(up, UART_LCR, 0x03);
749 for (count = 0; count < 256; count++)
750 serial_outp(up, UART_TX, count);
751 mdelay(20);/* FIXME - schedule_timeout */
752 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
753 (count < 256); count++)
754 serial_inp(up, UART_RX);
755 serial_outp(up, UART_FCR, old_fcr);
756 serial_outp(up, UART_MCR, old_mcr);
757 serial_outp(up, UART_LCR, UART_LCR_DLAB);
758 serial_dl_write(up, old_dl);
759 serial_outp(up, UART_LCR, old_lcr);
760
761 return count;
762 }
763
764 /*
765 * Read UART ID using the divisor method - set DLL and DLM to zero
766 * and the revision will be in DLL and device type in DLM. We
767 * preserve the device state across this.
768 */
769 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
770 {
771 unsigned char old_dll, old_dlm, old_lcr;
772 unsigned int id;
773
774 old_lcr = serial_inp(p, UART_LCR);
775 serial_outp(p, UART_LCR, UART_LCR_DLAB);
776
777 old_dll = serial_inp(p, UART_DLL);
778 old_dlm = serial_inp(p, UART_DLM);
779
780 serial_outp(p, UART_DLL, 0);
781 serial_outp(p, UART_DLM, 0);
782
783 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
784
785 serial_outp(p, UART_DLL, old_dll);
786 serial_outp(p, UART_DLM, old_dlm);
787 serial_outp(p, UART_LCR, old_lcr);
788
789 return id;
790 }
791
792 /*
793 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
794 * When this function is called we know it is at least a StarTech
795 * 16650 V2, but it might be one of several StarTech UARTs, or one of
796 * its clones. (We treat the broken original StarTech 16650 V1 as a
797 * 16550, and why not? Startech doesn't seem to even acknowledge its
798 * existence.)
799 *
800 * What evil have men's minds wrought...
801 */
802 static void autoconfig_has_efr(struct uart_8250_port *up)
803 {
804 unsigned int id1, id2, id3, rev;
805
806 /*
807 * Everything with an EFR has SLEEP
808 */
809 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
810
811 /*
812 * First we check to see if it's an Oxford Semiconductor UART.
813 *
814 * If we have to do this here because some non-National
815 * Semiconductor clone chips lock up if you try writing to the
816 * LSR register (which serial_icr_read does)
817 */
818
819 /*
820 * Check for Oxford Semiconductor 16C950.
821 *
822 * EFR [4] must be set else this test fails.
823 *
824 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
825 * claims that it's needed for 952 dual UART's (which are not
826 * recommended for new designs).
827 */
828 up->acr = 0;
829 serial_out(up, UART_LCR, 0xBF);
830 serial_out(up, UART_EFR, UART_EFR_ECB);
831 serial_out(up, UART_LCR, 0x00);
832 id1 = serial_icr_read(up, UART_ID1);
833 id2 = serial_icr_read(up, UART_ID2);
834 id3 = serial_icr_read(up, UART_ID3);
835 rev = serial_icr_read(up, UART_REV);
836
837 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
838
839 if (id1 == 0x16 && id2 == 0xC9 &&
840 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
841 up->port.type = PORT_16C950;
842
843 /*
844 * Enable work around for the Oxford Semiconductor 952 rev B
845 * chip which causes it to seriously miscalculate baud rates
846 * when DLL is 0.
847 */
848 if (id3 == 0x52 && rev == 0x01)
849 up->bugs |= UART_BUG_QUOT;
850 return;
851 }
852
853 /*
854 * We check for a XR16C850 by setting DLL and DLM to 0, and then
855 * reading back DLL and DLM. The chip type depends on the DLM
856 * value read back:
857 * 0x10 - XR16C850 and the DLL contains the chip revision.
858 * 0x12 - XR16C2850.
859 * 0x14 - XR16C854.
860 */
861 id1 = autoconfig_read_divisor_id(up);
862 DEBUG_AUTOCONF("850id=%04x ", id1);
863
864 id2 = id1 >> 8;
865 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
866 up->port.type = PORT_16850;
867 return;
868 }
869
870 /*
871 * It wasn't an XR16C850.
872 *
873 * We distinguish between the '654 and the '650 by counting
874 * how many bytes are in the FIFO. I'm using this for now,
875 * since that's the technique that was sent to me in the
876 * serial driver update, but I'm not convinced this works.
877 * I've had problems doing this in the past. -TYT
878 */
879 if (size_fifo(up) == 64)
880 up->port.type = PORT_16654;
881 else
882 up->port.type = PORT_16650V2;
883 }
884
885 /*
886 * We detected a chip without a FIFO. Only two fall into
887 * this category - the original 8250 and the 16450. The
888 * 16450 has a scratch register (accessible with LCR=0)
889 */
890 static void autoconfig_8250(struct uart_8250_port *up)
891 {
892 unsigned char scratch, status1, status2;
893
894 up->port.type = PORT_8250;
895
896 scratch = serial_in(up, UART_SCR);
897 serial_outp(up, UART_SCR, 0xa5);
898 status1 = serial_in(up, UART_SCR);
899 serial_outp(up, UART_SCR, 0x5a);
900 status2 = serial_in(up, UART_SCR);
901 serial_outp(up, UART_SCR, scratch);
902
903 if (status1 == 0xa5 && status2 == 0x5a)
904 up->port.type = PORT_16450;
905 }
906
907 static int broken_efr(struct uart_8250_port *up)
908 {
909 /*
910 * Exar ST16C2550 "A2" devices incorrectly detect as
911 * having an EFR, and report an ID of 0x0201. See
912 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
913 */
914 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
915 return 1;
916
917 return 0;
918 }
919
920 /*
921 * We know that the chip has FIFOs. Does it have an EFR? The
922 * EFR is located in the same register position as the IIR and
923 * we know the top two bits of the IIR are currently set. The
924 * EFR should contain zero. Try to read the EFR.
925 */
926 static void autoconfig_16550a(struct uart_8250_port *up)
927 {
928 unsigned char status1, status2;
929 unsigned int iersave;
930
931 up->port.type = PORT_16550A;
932 up->capabilities |= UART_CAP_FIFO;
933
934 /*
935 * Check for presence of the EFR when DLAB is set.
936 * Only ST16C650V1 UARTs pass this test.
937 */
938 serial_outp(up, UART_LCR, UART_LCR_DLAB);
939 if (serial_in(up, UART_EFR) == 0) {
940 serial_outp(up, UART_EFR, 0xA8);
941 if (serial_in(up, UART_EFR) != 0) {
942 DEBUG_AUTOCONF("EFRv1 ");
943 up->port.type = PORT_16650;
944 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
945 } else {
946 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
947 }
948 serial_outp(up, UART_EFR, 0);
949 return;
950 }
951
952 /*
953 * Maybe it requires 0xbf to be written to the LCR.
954 * (other ST16C650V2 UARTs, TI16C752A, etc)
955 */
956 serial_outp(up, UART_LCR, 0xBF);
957 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
958 DEBUG_AUTOCONF("EFRv2 ");
959 autoconfig_has_efr(up);
960 return;
961 }
962
963 /*
964 * Check for a National Semiconductor SuperIO chip.
965 * Attempt to switch to bank 2, read the value of the LOOP bit
966 * from EXCR1. Switch back to bank 0, change it in MCR. Then
967 * switch back to bank 2, read it from EXCR1 again and check
968 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
969 */
970 serial_outp(up, UART_LCR, 0);
971 status1 = serial_in(up, UART_MCR);
972 serial_outp(up, UART_LCR, 0xE0);
973 status2 = serial_in(up, 0x02); /* EXCR1 */
974
975 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
976 serial_outp(up, UART_LCR, 0);
977 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
978 serial_outp(up, UART_LCR, 0xE0);
979 status2 = serial_in(up, 0x02); /* EXCR1 */
980 serial_outp(up, UART_LCR, 0);
981 serial_outp(up, UART_MCR, status1);
982
983 if ((status2 ^ status1) & UART_MCR_LOOP) {
984 unsigned short quot;
985
986 serial_outp(up, UART_LCR, 0xE0);
987
988 quot = serial_dl_read(up);
989 quot <<= 3;
990
991 status1 = serial_in(up, 0x04); /* EXCR2 */
992 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
993 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
994 serial_outp(up, 0x04, status1);
995
996 serial_dl_write(up, quot);
997
998 serial_outp(up, UART_LCR, 0);
999
1000 up->port.uartclk = 921600*16;
1001 up->port.type = PORT_NS16550A;
1002 up->capabilities |= UART_NATSEMI;
1003 return;
1004 }
1005 }
1006
1007 /*
1008 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1009 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1010 * Try setting it with and without DLAB set. Cheap clones
1011 * set bit 5 without DLAB set.
1012 */
1013 serial_outp(up, UART_LCR, 0);
1014 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1015 status1 = serial_in(up, UART_IIR) >> 5;
1016 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1017 serial_outp(up, UART_LCR, UART_LCR_DLAB);
1018 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1019 status2 = serial_in(up, UART_IIR) >> 5;
1020 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1021 serial_outp(up, UART_LCR, 0);
1022
1023 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1024
1025 if (status1 == 6 && status2 == 7) {
1026 up->port.type = PORT_16750;
1027 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1028 return;
1029 }
1030
1031 /*
1032 * Try writing and reading the UART_IER_UUE bit (b6).
1033 * If it works, this is probably one of the Xscale platform's
1034 * internal UARTs.
1035 * We're going to explicitly set the UUE bit to 0 before
1036 * trying to write and read a 1 just to make sure it's not
1037 * already a 1 and maybe locked there before we even start start.
1038 */
1039 iersave = serial_in(up, UART_IER);
1040 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1041 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1042 /*
1043 * OK it's in a known zero state, try writing and reading
1044 * without disturbing the current state of the other bits.
1045 */
1046 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
1047 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1048 /*
1049 * It's an Xscale.
1050 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1051 */
1052 DEBUG_AUTOCONF("Xscale ");
1053 up->port.type = PORT_XSCALE;
1054 up->capabilities |= UART_CAP_UUE;
1055 return;
1056 }
1057 } else {
1058 /*
1059 * If we got here we couldn't force the IER_UUE bit to 0.
1060 * Log it and continue.
1061 */
1062 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1063 }
1064 serial_outp(up, UART_IER, iersave);
1065 }
1066
1067 /*
1068 * This routine is called by rs_init() to initialize a specific serial
1069 * port. It determines what type of UART chip this serial port is
1070 * using: 8250, 16450, 16550, 16550A. The important question is
1071 * whether or not this UART is a 16550A or not, since this will
1072 * determine whether or not we can use its FIFO features or not.
1073 */
1074 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1075 {
1076 unsigned char status1, scratch, scratch2, scratch3;
1077 unsigned char save_lcr, save_mcr;
1078 unsigned long flags;
1079
1080 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1081 return;
1082
1083 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ",
1084 serial_index(&up->port), up->port.iobase, up->port.membase);
1085
1086 /*
1087 * We really do need global IRQs disabled here - we're going to
1088 * be frobbing the chips IRQ enable register to see if it exists.
1089 */
1090 spin_lock_irqsave(&up->port.lock, flags);
1091
1092 up->capabilities = 0;
1093 up->bugs = 0;
1094
1095 if (!(up->port.flags & UPF_BUGGY_UART)) {
1096 /*
1097 * Do a simple existence test first; if we fail this,
1098 * there's no point trying anything else.
1099 *
1100 * 0x80 is used as a nonsense port to prevent against
1101 * false positives due to ISA bus float. The
1102 * assumption is that 0x80 is a non-existent port;
1103 * which should be safe since include/asm/io.h also
1104 * makes this assumption.
1105 *
1106 * Note: this is safe as long as MCR bit 4 is clear
1107 * and the device is in "PC" mode.
1108 */
1109 scratch = serial_inp(up, UART_IER);
1110 serial_outp(up, UART_IER, 0);
1111 #ifdef __i386__
1112 outb(0xff, 0x080);
1113 #endif
1114 /*
1115 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1116 * 16C754B) allow only to modify them if an EFR bit is set.
1117 */
1118 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1119 serial_outp(up, UART_IER, 0x0F);
1120 #ifdef __i386__
1121 outb(0, 0x080);
1122 #endif
1123 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1124 serial_outp(up, UART_IER, scratch);
1125 if (scratch2 != 0 || scratch3 != 0x0F) {
1126 /*
1127 * We failed; there's nothing here
1128 */
1129 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1130 scratch2, scratch3);
1131 goto out;
1132 }
1133 }
1134
1135 save_mcr = serial_in(up, UART_MCR);
1136 save_lcr = serial_in(up, UART_LCR);
1137
1138 /*
1139 * Check to see if a UART is really there. Certain broken
1140 * internal modems based on the Rockwell chipset fail this
1141 * test, because they apparently don't implement the loopback
1142 * test mode. So this test is skipped on the COM 1 through
1143 * COM 4 ports. This *should* be safe, since no board
1144 * manufacturer would be stupid enough to design a board
1145 * that conflicts with COM 1-4 --- we hope!
1146 */
1147 if (!(up->port.flags & UPF_SKIP_TEST)) {
1148 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1149 status1 = serial_inp(up, UART_MSR) & 0xF0;
1150 serial_outp(up, UART_MCR, save_mcr);
1151 if (status1 != 0x90) {
1152 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1153 status1);
1154 goto out;
1155 }
1156 }
1157
1158 /*
1159 * We're pretty sure there's a port here. Lets find out what
1160 * type of port it is. The IIR top two bits allows us to find
1161 * out if it's 8250 or 16450, 16550, 16550A or later. This
1162 * determines what we test for next.
1163 *
1164 * We also initialise the EFR (if any) to zero for later. The
1165 * EFR occupies the same register location as the FCR and IIR.
1166 */
1167 serial_outp(up, UART_LCR, 0xBF);
1168 serial_outp(up, UART_EFR, 0);
1169 serial_outp(up, UART_LCR, 0);
1170
1171 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1172 scratch = serial_in(up, UART_IIR) >> 6;
1173
1174 DEBUG_AUTOCONF("iir=%d ", scratch);
1175
1176 switch (scratch) {
1177 case 0:
1178 autoconfig_8250(up);
1179 break;
1180 case 1:
1181 up->port.type = PORT_UNKNOWN;
1182 break;
1183 case 2:
1184 up->port.type = PORT_16550;
1185 break;
1186 case 3:
1187 autoconfig_16550a(up);
1188 break;
1189 }
1190
1191 #ifdef CONFIG_SERIAL_8250_RSA
1192 /*
1193 * Only probe for RSA ports if we got the region.
1194 */
1195 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1196 int i;
1197
1198 for (i = 0 ; i < probe_rsa_count; ++i) {
1199 if (probe_rsa[i] == up->port.iobase &&
1200 __enable_rsa(up)) {
1201 up->port.type = PORT_RSA;
1202 break;
1203 }
1204 }
1205 }
1206 #endif
1207
1208 #ifdef CONFIG_SERIAL_8250_AU1X00
1209 /* if access method is AU, it is a 16550 with a quirk */
1210 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
1211 up->bugs |= UART_BUG_NOMSR;
1212 #endif
1213
1214 serial_outp(up, UART_LCR, save_lcr);
1215
1216 if (up->capabilities != uart_config[up->port.type].flags) {
1217 printk(KERN_WARNING
1218 "ttyS%d: detected caps %08x should be %08x\n",
1219 serial_index(&up->port), up->capabilities,
1220 uart_config[up->port.type].flags);
1221 }
1222
1223 up->port.fifosize = uart_config[up->port.type].fifo_size;
1224 up->capabilities = uart_config[up->port.type].flags;
1225 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1226
1227 if (up->port.type == PORT_UNKNOWN)
1228 goto out;
1229
1230 /*
1231 * Reset the UART.
1232 */
1233 #ifdef CONFIG_SERIAL_8250_RSA
1234 if (up->port.type == PORT_RSA)
1235 serial_outp(up, UART_RSA_FRR, 0);
1236 #endif
1237 serial_outp(up, UART_MCR, save_mcr);
1238 serial8250_clear_fifos(up);
1239 serial_in(up, UART_RX);
1240 if (up->capabilities & UART_CAP_UUE)
1241 serial_outp(up, UART_IER, UART_IER_UUE);
1242 else
1243 serial_outp(up, UART_IER, 0);
1244
1245 out:
1246 spin_unlock_irqrestore(&up->port.lock, flags);
1247 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1248 }
1249
1250 static void autoconfig_irq(struct uart_8250_port *up)
1251 {
1252 unsigned char save_mcr, save_ier;
1253 unsigned char save_ICP = 0;
1254 unsigned int ICP = 0;
1255 unsigned long irqs;
1256 int irq;
1257
1258 if (up->port.flags & UPF_FOURPORT) {
1259 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1260 save_ICP = inb_p(ICP);
1261 outb_p(0x80, ICP);
1262 (void) inb_p(ICP);
1263 }
1264
1265 /* forget possible initially masked and pending IRQ */
1266 probe_irq_off(probe_irq_on());
1267 save_mcr = serial_inp(up, UART_MCR);
1268 save_ier = serial_inp(up, UART_IER);
1269 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1270
1271 irqs = probe_irq_on();
1272 serial_outp(up, UART_MCR, 0);
1273 udelay(10);
1274 if (up->port.flags & UPF_FOURPORT) {
1275 serial_outp(up, UART_MCR,
1276 UART_MCR_DTR | UART_MCR_RTS);
1277 } else {
1278 serial_outp(up, UART_MCR,
1279 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1280 }
1281 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1282 (void)serial_inp(up, UART_LSR);
1283 (void)serial_inp(up, UART_RX);
1284 (void)serial_inp(up, UART_IIR);
1285 (void)serial_inp(up, UART_MSR);
1286 serial_outp(up, UART_TX, 0xFF);
1287 udelay(20);
1288 irq = probe_irq_off(irqs);
1289
1290 serial_outp(up, UART_MCR, save_mcr);
1291 serial_outp(up, UART_IER, save_ier);
1292
1293 if (up->port.flags & UPF_FOURPORT)
1294 outb_p(save_ICP, ICP);
1295
1296 up->port.irq = (irq > 0) ? irq : 0;
1297 }
1298
1299 static inline void __stop_tx(struct uart_8250_port *p)
1300 {
1301 if (p->ier & UART_IER_THRI) {
1302 p->ier &= ~UART_IER_THRI;
1303 serial_out(p, UART_IER, p->ier);
1304 }
1305 }
1306
1307 static void serial8250_stop_tx(struct uart_port *port)
1308 {
1309 struct uart_8250_port *up = (struct uart_8250_port *)port;
1310
1311 __stop_tx(up);
1312
1313 /*
1314 * We really want to stop the transmitter from sending.
1315 */
1316 if (up->port.type == PORT_16C950) {
1317 up->acr |= UART_ACR_TXDIS;
1318 serial_icr_write(up, UART_ACR, up->acr);
1319 }
1320 }
1321
1322 static void transmit_chars(struct uart_8250_port *up);
1323
1324 static void serial8250_start_tx(struct uart_port *port)
1325 {
1326 struct uart_8250_port *up = (struct uart_8250_port *)port;
1327
1328 if (!(up->ier & UART_IER_THRI)) {
1329 up->ier |= UART_IER_THRI;
1330 serial_out(up, UART_IER, up->ier);
1331
1332 if (up->bugs & UART_BUG_TXEN) {
1333 unsigned char lsr, iir;
1334 lsr = serial_in(up, UART_LSR);
1335 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1336 iir = serial_in(up, UART_IIR) & 0x0f;
1337 if ((up->port.type == PORT_RM9000) ?
1338 (lsr & UART_LSR_THRE &&
1339 (iir == UART_IIR_NO_INT || iir == UART_IIR_THRI)) :
1340 (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT))
1341 transmit_chars(up);
1342 }
1343 }
1344
1345 /*
1346 * Re-enable the transmitter if we disabled it.
1347 */
1348 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1349 up->acr &= ~UART_ACR_TXDIS;
1350 serial_icr_write(up, UART_ACR, up->acr);
1351 }
1352 }
1353
1354 static void serial8250_stop_rx(struct uart_port *port)
1355 {
1356 struct uart_8250_port *up = (struct uart_8250_port *)port;
1357
1358 up->ier &= ~UART_IER_RLSI;
1359 up->port.read_status_mask &= ~UART_LSR_DR;
1360 serial_out(up, UART_IER, up->ier);
1361 }
1362
1363 static void serial8250_enable_ms(struct uart_port *port)
1364 {
1365 struct uart_8250_port *up = (struct uart_8250_port *)port;
1366
1367 /* no MSR capabilities */
1368 if (up->bugs & UART_BUG_NOMSR)
1369 return;
1370
1371 up->ier |= UART_IER_MSI;
1372 serial_out(up, UART_IER, up->ier);
1373 }
1374
1375 static void
1376 receive_chars(struct uart_8250_port *up, unsigned int *status)
1377 {
1378 struct tty_struct *tty = up->port.info->port.tty;
1379 unsigned char ch, lsr = *status;
1380 int max_count = 256;
1381 char flag;
1382
1383 do {
1384 if (likely(lsr & UART_LSR_DR))
1385 ch = serial_inp(up, UART_RX);
1386 else
1387 /*
1388 * Intel 82571 has a Serial Over Lan device that will
1389 * set UART_LSR_BI without setting UART_LSR_DR when
1390 * it receives a break. To avoid reading from the
1391 * receive buffer without UART_LSR_DR bit set, we
1392 * just force the read character to be 0
1393 */
1394 ch = 0;
1395
1396 flag = TTY_NORMAL;
1397 up->port.icount.rx++;
1398
1399 lsr |= up->lsr_saved_flags;
1400 up->lsr_saved_flags = 0;
1401
1402 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1403 /*
1404 * For statistics only
1405 */
1406 if (lsr & UART_LSR_BI) {
1407 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1408 up->port.icount.brk++;
1409 /*
1410 * We do the SysRQ and SAK checking
1411 * here because otherwise the break
1412 * may get masked by ignore_status_mask
1413 * or read_status_mask.
1414 */
1415 if (uart_handle_break(&up->port))
1416 goto ignore_char;
1417 } else if (lsr & UART_LSR_PE)
1418 up->port.icount.parity++;
1419 else if (lsr & UART_LSR_FE)
1420 up->port.icount.frame++;
1421 if (lsr & UART_LSR_OE)
1422 up->port.icount.overrun++;
1423
1424 /*
1425 * Mask off conditions which should be ignored.
1426 */
1427 lsr &= up->port.read_status_mask;
1428
1429 if (lsr & UART_LSR_BI) {
1430 DEBUG_INTR("handling break....");
1431 flag = TTY_BREAK;
1432 } else if (lsr & UART_LSR_PE)
1433 flag = TTY_PARITY;
1434 else if (lsr & UART_LSR_FE)
1435 flag = TTY_FRAME;
1436 }
1437 if (uart_handle_sysrq_char(&up->port, ch))
1438 goto ignore_char;
1439
1440 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1441
1442 ignore_char:
1443 lsr = serial_inp(up, UART_LSR);
1444 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1445 spin_unlock(&up->port.lock);
1446 tty_flip_buffer_push(tty);
1447 spin_lock(&up->port.lock);
1448 *status = lsr;
1449 }
1450
1451 static void transmit_chars(struct uart_8250_port *up)
1452 {
1453 struct circ_buf *xmit = &up->port.info->xmit;
1454 int count;
1455
1456 if (up->port.x_char) {
1457 serial_outp(up, UART_TX, up->port.x_char);
1458 up->port.icount.tx++;
1459 up->port.x_char = 0;
1460 return;
1461 }
1462 if (uart_tx_stopped(&up->port)) {
1463 serial8250_stop_tx(&up->port);
1464 return;
1465 }
1466 if (uart_circ_empty(xmit)) {
1467 __stop_tx(up);
1468 return;
1469 }
1470
1471 count = up->tx_loadsz;
1472 do {
1473 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1474 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1475 up->port.icount.tx++;
1476 if (uart_circ_empty(xmit))
1477 break;
1478 } while (--count > 0);
1479
1480 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1481 uart_write_wakeup(&up->port);
1482
1483 DEBUG_INTR("THRE...");
1484
1485 if (uart_circ_empty(xmit))
1486 __stop_tx(up);
1487 }
1488
1489 static unsigned int check_modem_status(struct uart_8250_port *up)
1490 {
1491 unsigned int status = serial_in(up, UART_MSR);
1492
1493 status |= up->msr_saved_flags;
1494 up->msr_saved_flags = 0;
1495 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1496 up->port.info != NULL) {
1497 if (status & UART_MSR_TERI)
1498 up->port.icount.rng++;
1499 if (status & UART_MSR_DDSR)
1500 up->port.icount.dsr++;
1501 if (status & UART_MSR_DDCD)
1502 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1503 if (status & UART_MSR_DCTS)
1504 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1505
1506 wake_up_interruptible(&up->port.info->delta_msr_wait);
1507 }
1508
1509 return status;
1510 }
1511
1512 /*
1513 * This handles the interrupt from one port.
1514 */
1515 static void serial8250_handle_port(struct uart_8250_port *up)
1516 {
1517 unsigned int status;
1518 unsigned long flags;
1519
1520 spin_lock_irqsave(&up->port.lock, flags);
1521
1522 status = serial_inp(up, UART_LSR);
1523
1524 DEBUG_INTR("status = %x...", status);
1525
1526 if (status & (UART_LSR_DR | UART_LSR_BI))
1527 receive_chars(up, &status);
1528 check_modem_status(up);
1529 if (status & UART_LSR_THRE)
1530 transmit_chars(up);
1531
1532 spin_unlock_irqrestore(&up->port.lock, flags);
1533 }
1534
1535 /*
1536 * This is the serial driver's interrupt routine.
1537 *
1538 * Arjan thinks the old way was overly complex, so it got simplified.
1539 * Alan disagrees, saying that need the complexity to handle the weird
1540 * nature of ISA shared interrupts. (This is a special exception.)
1541 *
1542 * In order to handle ISA shared interrupts properly, we need to check
1543 * that all ports have been serviced, and therefore the ISA interrupt
1544 * line has been de-asserted.
1545 *
1546 * This means we need to loop through all ports. checking that they
1547 * don't have an interrupt pending.
1548 */
1549 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1550 {
1551 struct irq_info *i = dev_id;
1552 struct list_head *l, *end = NULL;
1553 int pass_counter = 0, handled = 0;
1554
1555 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1556
1557 spin_lock(&i->lock);
1558
1559 l = i->head;
1560 do {
1561 struct uart_8250_port *up;
1562 unsigned int iir;
1563
1564 up = list_entry(l, struct uart_8250_port, list);
1565
1566 iir = serial_in(up, UART_IIR);
1567 if (!(iir & UART_IIR_NO_INT)) {
1568 serial8250_handle_port(up);
1569
1570 handled = 1;
1571
1572 end = NULL;
1573 } else if (up->port.iotype == UPIO_DWAPB &&
1574 (iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
1575 /* The DesignWare APB UART has an Busy Detect (0x07)
1576 * interrupt meaning an LCR write attempt occured while the
1577 * UART was busy. The interrupt must be cleared by reading
1578 * the UART status register (USR) and the LCR re-written. */
1579 unsigned int status;
1580 status = *(volatile u32 *)up->port.private_data;
1581 serial_out(up, UART_LCR, up->lcr);
1582
1583 handled = 1;
1584
1585 end = NULL;
1586 } else if (end == NULL)
1587 end = l;
1588
1589 l = l->next;
1590
1591 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1592 /* If we hit this, we're dead. */
1593 printk(KERN_ERR "serial8250: too much work for "
1594 "irq%d\n", irq);
1595 break;
1596 }
1597 } while (l != end);
1598
1599 spin_unlock(&i->lock);
1600
1601 DEBUG_INTR("end.\n");
1602
1603 return IRQ_RETVAL(handled);
1604 }
1605
1606 /*
1607 * To support ISA shared interrupts, we need to have one interrupt
1608 * handler that ensures that the IRQ line has been deasserted
1609 * before returning. Failing to do this will result in the IRQ
1610 * line being stuck active, and, since ISA irqs are edge triggered,
1611 * no more IRQs will be seen.
1612 */
1613 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1614 {
1615 spin_lock_irq(&i->lock);
1616
1617 if (!list_empty(i->head)) {
1618 if (i->head == &up->list)
1619 i->head = i->head->next;
1620 list_del(&up->list);
1621 } else {
1622 BUG_ON(i->head != &up->list);
1623 i->head = NULL;
1624 }
1625 spin_unlock_irq(&i->lock);
1626 /* List empty so throw away the hash node */
1627 if (i->head == NULL) {
1628 hlist_del(&i->node);
1629 kfree(i);
1630 }
1631 }
1632
1633 static int serial_link_irq_chain(struct uart_8250_port *up)
1634 {
1635 struct hlist_head *h;
1636 struct hlist_node *n;
1637 struct irq_info *i;
1638 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1639
1640 mutex_lock(&hash_mutex);
1641
1642 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1643
1644 hlist_for_each(n, h) {
1645 i = hlist_entry(n, struct irq_info, node);
1646 if (i->irq == up->port.irq)
1647 break;
1648 }
1649
1650 if (n == NULL) {
1651 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1652 if (i == NULL) {
1653 mutex_unlock(&hash_mutex);
1654 return -ENOMEM;
1655 }
1656 spin_lock_init(&i->lock);
1657 i->irq = up->port.irq;
1658 hlist_add_head(&i->node, h);
1659 }
1660 mutex_unlock(&hash_mutex);
1661
1662 spin_lock_irq(&i->lock);
1663
1664 if (i->head) {
1665 list_add(&up->list, i->head);
1666 spin_unlock_irq(&i->lock);
1667
1668 ret = 0;
1669 } else {
1670 INIT_LIST_HEAD(&up->list);
1671 i->head = &up->list;
1672 spin_unlock_irq(&i->lock);
1673
1674 ret = request_irq(up->port.irq, serial8250_interrupt,
1675 irq_flags, "serial", i);
1676 if (ret < 0)
1677 serial_do_unlink(i, up);
1678 }
1679
1680 return ret;
1681 }
1682
1683 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1684 {
1685 struct irq_info *i;
1686 struct hlist_node *n;
1687 struct hlist_head *h;
1688
1689 mutex_lock(&hash_mutex);
1690
1691 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1692
1693 hlist_for_each(n, h) {
1694 i = hlist_entry(n, struct irq_info, node);
1695 if (i->irq == up->port.irq)
1696 break;
1697 }
1698
1699 BUG_ON(n == NULL);
1700 BUG_ON(i->head == NULL);
1701
1702 if (list_empty(i->head))
1703 free_irq(up->port.irq, i);
1704
1705 serial_do_unlink(i, up);
1706 mutex_unlock(&hash_mutex);
1707 }
1708
1709 /* Base timer interval for polling */
1710 static inline int poll_timeout(int timeout)
1711 {
1712 return timeout > 6 ? (timeout / 2 - 2) : 1;
1713 }
1714
1715 /*
1716 * This function is used to handle ports that do not have an
1717 * interrupt. This doesn't work very well for 16450's, but gives
1718 * barely passable results for a 16550A. (Although at the expense
1719 * of much CPU overhead).
1720 */
1721 static void serial8250_timeout(unsigned long data)
1722 {
1723 struct uart_8250_port *up = (struct uart_8250_port *)data;
1724 unsigned int iir;
1725
1726 iir = serial_in(up, UART_IIR);
1727 if (!(iir & UART_IIR_NO_INT))
1728 serial8250_handle_port(up);
1729 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1730 }
1731
1732 static void serial8250_backup_timeout(unsigned long data)
1733 {
1734 struct uart_8250_port *up = (struct uart_8250_port *)data;
1735 unsigned int iir, ier = 0, lsr;
1736 unsigned long flags;
1737
1738 /*
1739 * Must disable interrupts or else we risk racing with the interrupt
1740 * based handler.
1741 */
1742 if (is_real_interrupt(up->port.irq)) {
1743 ier = serial_in(up, UART_IER);
1744 serial_out(up, UART_IER, 0);
1745 }
1746
1747 iir = serial_in(up, UART_IIR);
1748
1749 /*
1750 * This should be a safe test for anyone who doesn't trust the
1751 * IIR bits on their UART, but it's specifically designed for
1752 * the "Diva" UART used on the management processor on many HP
1753 * ia64 and parisc boxes.
1754 */
1755 spin_lock_irqsave(&up->port.lock, flags);
1756 lsr = serial_in(up, UART_LSR);
1757 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1758 spin_unlock_irqrestore(&up->port.lock, flags);
1759 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1760 (!uart_circ_empty(&up->port.info->xmit) || up->port.x_char) &&
1761 (lsr & UART_LSR_THRE)) {
1762 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1763 iir |= UART_IIR_THRI;
1764 }
1765
1766 if (!(iir & UART_IIR_NO_INT))
1767 serial8250_handle_port(up);
1768
1769 if (is_real_interrupt(up->port.irq))
1770 serial_out(up, UART_IER, ier);
1771
1772 /* Standard timer interval plus 0.2s to keep the port running */
1773 mod_timer(&up->timer,
1774 jiffies + poll_timeout(up->port.timeout) + HZ / 5);
1775 }
1776
1777 static unsigned int serial8250_tx_empty(struct uart_port *port)
1778 {
1779 struct uart_8250_port *up = (struct uart_8250_port *)port;
1780 unsigned long flags;
1781 unsigned int lsr;
1782
1783 spin_lock_irqsave(&up->port.lock, flags);
1784 lsr = serial_in(up, UART_LSR);
1785 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1786 spin_unlock_irqrestore(&up->port.lock, flags);
1787
1788 return lsr & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
1789 }
1790
1791 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1792 {
1793 struct uart_8250_port *up = (struct uart_8250_port *)port;
1794 unsigned int status;
1795 unsigned int ret;
1796
1797 status = check_modem_status(up);
1798
1799 ret = 0;
1800 if (status & UART_MSR_DCD)
1801 ret |= TIOCM_CAR;
1802 if (status & UART_MSR_RI)
1803 ret |= TIOCM_RNG;
1804 if (status & UART_MSR_DSR)
1805 ret |= TIOCM_DSR;
1806 if (status & UART_MSR_CTS)
1807 ret |= TIOCM_CTS;
1808 return ret;
1809 }
1810
1811 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1812 {
1813 struct uart_8250_port *up = (struct uart_8250_port *)port;
1814 unsigned char mcr = 0;
1815
1816 if (mctrl & TIOCM_RTS)
1817 mcr |= UART_MCR_RTS;
1818 if (mctrl & TIOCM_DTR)
1819 mcr |= UART_MCR_DTR;
1820 if (mctrl & TIOCM_OUT1)
1821 mcr |= UART_MCR_OUT1;
1822 if (mctrl & TIOCM_OUT2)
1823 mcr |= UART_MCR_OUT2;
1824 if (mctrl & TIOCM_LOOP)
1825 mcr |= UART_MCR_LOOP;
1826
1827 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1828
1829 serial_out(up, UART_MCR, mcr);
1830 }
1831
1832 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1833 {
1834 struct uart_8250_port *up = (struct uart_8250_port *)port;
1835 unsigned long flags;
1836
1837 spin_lock_irqsave(&up->port.lock, flags);
1838 if (break_state == -1)
1839 up->lcr |= UART_LCR_SBC;
1840 else
1841 up->lcr &= ~UART_LCR_SBC;
1842 serial_out(up, UART_LCR, up->lcr);
1843 spin_unlock_irqrestore(&up->port.lock, flags);
1844 }
1845
1846 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1847
1848 /*
1849 * Wait for transmitter & holding register to empty
1850 */
1851 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1852 {
1853 unsigned int status, tmout = 10000;
1854
1855 /* Wait up to 10ms for the character(s) to be sent. */
1856 do {
1857 status = serial_in(up, UART_LSR);
1858
1859 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1860
1861 if (--tmout == 0)
1862 break;
1863 udelay(1);
1864 } while ((status & bits) != bits);
1865
1866 /* Wait up to 1s for flow control if necessary */
1867 if (up->port.flags & UPF_CONS_FLOW) {
1868 unsigned int tmout;
1869 for (tmout = 1000000; tmout; tmout--) {
1870 unsigned int msr = serial_in(up, UART_MSR);
1871 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1872 if (msr & UART_MSR_CTS)
1873 break;
1874 udelay(1);
1875 touch_nmi_watchdog();
1876 }
1877 }
1878 }
1879
1880 #ifdef CONFIG_CONSOLE_POLL
1881 /*
1882 * Console polling routines for writing and reading from the uart while
1883 * in an interrupt or debug context.
1884 */
1885
1886 static int serial8250_get_poll_char(struct uart_port *port)
1887 {
1888 struct uart_8250_port *up = (struct uart_8250_port *)port;
1889 unsigned char lsr = serial_inp(up, UART_LSR);
1890
1891 while (!(lsr & UART_LSR_DR))
1892 lsr = serial_inp(up, UART_LSR);
1893
1894 return serial_inp(up, UART_RX);
1895 }
1896
1897
1898 static void serial8250_put_poll_char(struct uart_port *port,
1899 unsigned char c)
1900 {
1901 unsigned int ier;
1902 struct uart_8250_port *up = (struct uart_8250_port *)port;
1903
1904 /*
1905 * First save the IER then disable the interrupts
1906 */
1907 ier = serial_in(up, UART_IER);
1908 if (up->capabilities & UART_CAP_UUE)
1909 serial_out(up, UART_IER, UART_IER_UUE);
1910 else
1911 serial_out(up, UART_IER, 0);
1912
1913 wait_for_xmitr(up, BOTH_EMPTY);
1914 /*
1915 * Send the character out.
1916 * If a LF, also do CR...
1917 */
1918 serial_out(up, UART_TX, c);
1919 if (c == 10) {
1920 wait_for_xmitr(up, BOTH_EMPTY);
1921 serial_out(up, UART_TX, 13);
1922 }
1923
1924 /*
1925 * Finally, wait for transmitter to become empty
1926 * and restore the IER
1927 */
1928 wait_for_xmitr(up, BOTH_EMPTY);
1929 serial_out(up, UART_IER, ier);
1930 }
1931
1932 #endif /* CONFIG_CONSOLE_POLL */
1933
1934 static int serial8250_startup(struct uart_port *port)
1935 {
1936 struct uart_8250_port *up = (struct uart_8250_port *)port;
1937 unsigned long flags;
1938 unsigned char lsr, iir;
1939 int retval;
1940
1941 up->capabilities = uart_config[up->port.type].flags;
1942 up->mcr = 0;
1943
1944 if (up->port.iotype != up->cur_iotype)
1945 set_io_from_upio(port);
1946
1947 if (up->port.type == PORT_16C950) {
1948 /* Wake up and initialize UART */
1949 up->acr = 0;
1950 serial_outp(up, UART_LCR, 0xBF);
1951 serial_outp(up, UART_EFR, UART_EFR_ECB);
1952 serial_outp(up, UART_IER, 0);
1953 serial_outp(up, UART_LCR, 0);
1954 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1955 serial_outp(up, UART_LCR, 0xBF);
1956 serial_outp(up, UART_EFR, UART_EFR_ECB);
1957 serial_outp(up, UART_LCR, 0);
1958 }
1959
1960 #ifdef CONFIG_SERIAL_8250_RSA
1961 /*
1962 * If this is an RSA port, see if we can kick it up to the
1963 * higher speed clock.
1964 */
1965 enable_rsa(up);
1966 #endif
1967
1968 /*
1969 * Clear the FIFO buffers and disable them.
1970 * (they will be reenabled in set_termios())
1971 */
1972 serial8250_clear_fifos(up);
1973
1974 /*
1975 * Clear the interrupt registers.
1976 */
1977 (void) serial_inp(up, UART_LSR);
1978 (void) serial_inp(up, UART_RX);
1979 (void) serial_inp(up, UART_IIR);
1980 (void) serial_inp(up, UART_MSR);
1981
1982 /*
1983 * At this point, there's no way the LSR could still be 0xff;
1984 * if it is, then bail out, because there's likely no UART
1985 * here.
1986 */
1987 if (!(up->port.flags & UPF_BUGGY_UART) &&
1988 (serial_inp(up, UART_LSR) == 0xff)) {
1989 printk(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
1990 serial_index(&up->port));
1991 return -ENODEV;
1992 }
1993
1994 /*
1995 * For a XR16C850, we need to set the trigger levels
1996 */
1997 if (up->port.type == PORT_16850) {
1998 unsigned char fctr;
1999
2000 serial_outp(up, UART_LCR, 0xbf);
2001
2002 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2003 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2004 serial_outp(up, UART_TRG, UART_TRG_96);
2005 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2006 serial_outp(up, UART_TRG, UART_TRG_96);
2007
2008 serial_outp(up, UART_LCR, 0);
2009 }
2010
2011 if (is_real_interrupt(up->port.irq)) {
2012 unsigned char iir1;
2013 /*
2014 * Test for UARTs that do not reassert THRE when the
2015 * transmitter is idle and the interrupt has already
2016 * been cleared. Real 16550s should always reassert
2017 * this interrupt whenever the transmitter is idle and
2018 * the interrupt is enabled. Delays are necessary to
2019 * allow register changes to become visible.
2020 */
2021 spin_lock_irqsave(&up->port.lock, flags);
2022 if (up->port.flags & UPF_SHARE_IRQ)
2023 disable_irq_nosync(up->port.irq);
2024
2025 wait_for_xmitr(up, UART_LSR_THRE);
2026 serial_out_sync(up, UART_IER, UART_IER_THRI);
2027 udelay(1); /* allow THRE to set */
2028 iir1 = serial_in(up, UART_IIR);
2029 serial_out(up, UART_IER, 0);
2030 serial_out_sync(up, UART_IER, UART_IER_THRI);
2031 udelay(1); /* allow a working UART time to re-assert THRE */
2032 iir = serial_in(up, UART_IIR);
2033 serial_out(up, UART_IER, 0);
2034
2035 if (up->port.flags & UPF_SHARE_IRQ)
2036 enable_irq(up->port.irq);
2037 spin_unlock_irqrestore(&up->port.lock, flags);
2038
2039 /*
2040 * If the interrupt is not reasserted, setup a timer to
2041 * kick the UART on a regular basis.
2042 */
2043 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
2044 up->bugs |= UART_BUG_THRE;
2045 pr_debug("ttyS%d - using backup timer\n",
2046 serial_index(port));
2047 }
2048 }
2049
2050 /*
2051 * The above check will only give an accurate result the first time
2052 * the port is opened so this value needs to be preserved.
2053 */
2054 if (up->bugs & UART_BUG_THRE) {
2055 up->timer.function = serial8250_backup_timeout;
2056 up->timer.data = (unsigned long)up;
2057 mod_timer(&up->timer, jiffies +
2058 poll_timeout(up->port.timeout) + HZ / 5);
2059 }
2060
2061 /*
2062 * If the "interrupt" for this port doesn't correspond with any
2063 * hardware interrupt, we use a timer-based system. The original
2064 * driver used to do this with IRQ0.
2065 */
2066 if (!is_real_interrupt(up->port.irq)) {
2067 up->timer.data = (unsigned long)up;
2068 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
2069 } else {
2070 retval = serial_link_irq_chain(up);
2071 if (retval)
2072 return retval;
2073 }
2074
2075 /*
2076 * Now, initialize the UART
2077 */
2078 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2079
2080 spin_lock_irqsave(&up->port.lock, flags);
2081 if (up->port.flags & UPF_FOURPORT) {
2082 if (!is_real_interrupt(up->port.irq))
2083 up->port.mctrl |= TIOCM_OUT1;
2084 } else
2085 /*
2086 * Most PC uarts need OUT2 raised to enable interrupts.
2087 */
2088 if (is_real_interrupt(up->port.irq))
2089 up->port.mctrl |= TIOCM_OUT2;
2090
2091 serial8250_set_mctrl(&up->port, up->port.mctrl);
2092
2093 /* Serial over Lan (SoL) hack:
2094 Intel 8257x Gigabit ethernet chips have a
2095 16550 emulation, to be used for Serial Over Lan.
2096 Those chips take a longer time than a normal
2097 serial device to signalize that a transmission
2098 data was queued. Due to that, the above test generally
2099 fails. One solution would be to delay the reading of
2100 iir. However, this is not reliable, since the timeout
2101 is variable. So, let's just don't test if we receive
2102 TX irq. This way, we'll never enable UART_BUG_TXEN.
2103 */
2104 if (up->port.flags & UPF_NO_TXEN_TEST)
2105 goto dont_test_tx_en;
2106
2107 /*
2108 * Do a quick test to see if we receive an
2109 * interrupt when we enable the TX irq.
2110 */
2111 serial_outp(up, UART_IER, UART_IER_THRI);
2112 lsr = serial_in(up, UART_LSR);
2113 iir = serial_in(up, UART_IIR);
2114 serial_outp(up, UART_IER, 0);
2115
2116 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2117 if (!(up->bugs & UART_BUG_TXEN)) {
2118 up->bugs |= UART_BUG_TXEN;
2119 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2120 serial_index(port));
2121 }
2122 } else {
2123 up->bugs &= ~UART_BUG_TXEN;
2124 }
2125
2126 dont_test_tx_en:
2127 spin_unlock_irqrestore(&up->port.lock, flags);
2128
2129 /*
2130 * Clear the interrupt registers again for luck, and clear the
2131 * saved flags to avoid getting false values from polling
2132 * routines or the previous session.
2133 */
2134 serial_inp(up, UART_LSR);
2135 serial_inp(up, UART_RX);
2136 serial_inp(up, UART_IIR);
2137 serial_inp(up, UART_MSR);
2138 up->lsr_saved_flags = 0;
2139 up->msr_saved_flags = 0;
2140
2141 /*
2142 * Finally, enable interrupts. Note: Modem status interrupts
2143 * are set via set_termios(), which will be occurring imminently
2144 * anyway, so we don't enable them here.
2145 */
2146 up->ier = UART_IER_RLSI | UART_IER_RDI;
2147 serial_outp(up, UART_IER, up->ier);
2148
2149 if (up->port.flags & UPF_FOURPORT) {
2150 unsigned int icp;
2151 /*
2152 * Enable interrupts on the AST Fourport board
2153 */
2154 icp = (up->port.iobase & 0xfe0) | 0x01f;
2155 outb_p(0x80, icp);
2156 (void) inb_p(icp);
2157 }
2158
2159 return 0;
2160 }
2161
2162 static void serial8250_shutdown(struct uart_port *port)
2163 {
2164 struct uart_8250_port *up = (struct uart_8250_port *)port;
2165 unsigned long flags;
2166
2167 /*
2168 * Disable interrupts from this port
2169 */
2170 up->ier = 0;
2171 serial_outp(up, UART_IER, 0);
2172
2173 spin_lock_irqsave(&up->port.lock, flags);
2174 if (up->port.flags & UPF_FOURPORT) {
2175 /* reset interrupts on the AST Fourport board */
2176 inb((up->port.iobase & 0xfe0) | 0x1f);
2177 up->port.mctrl |= TIOCM_OUT1;
2178 } else
2179 up->port.mctrl &= ~TIOCM_OUT2;
2180
2181 serial8250_set_mctrl(&up->port, up->port.mctrl);
2182 spin_unlock_irqrestore(&up->port.lock, flags);
2183
2184 /*
2185 * Disable break condition and FIFOs
2186 */
2187 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2188 serial8250_clear_fifos(up);
2189
2190 #ifdef CONFIG_SERIAL_8250_RSA
2191 /*
2192 * Reset the RSA board back to 115kbps compat mode.
2193 */
2194 disable_rsa(up);
2195 #endif
2196
2197 /*
2198 * Read data port to reset things, and then unlink from
2199 * the IRQ chain.
2200 */
2201 (void) serial_in(up, UART_RX);
2202
2203 del_timer_sync(&up->timer);
2204 up->timer.function = serial8250_timeout;
2205 if (is_real_interrupt(up->port.irq))
2206 serial_unlink_irq_chain(up);
2207 }
2208
2209 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2210 {
2211 unsigned int quot;
2212
2213 /*
2214 * Handle magic divisors for baud rates above baud_base on
2215 * SMSC SuperIO chips.
2216 */
2217 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2218 baud == (port->uartclk/4))
2219 quot = 0x8001;
2220 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2221 baud == (port->uartclk/8))
2222 quot = 0x8002;
2223 else
2224 quot = uart_get_divisor(port, baud);
2225
2226 return quot;
2227 }
2228
2229 static void
2230 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2231 struct ktermios *old)
2232 {
2233 struct uart_8250_port *up = (struct uart_8250_port *)port;
2234 unsigned char cval, fcr = 0;
2235 unsigned long flags;
2236 unsigned int baud, quot;
2237
2238 switch (termios->c_cflag & CSIZE) {
2239 case CS5:
2240 cval = UART_LCR_WLEN5;
2241 break;
2242 case CS6:
2243 cval = UART_LCR_WLEN6;
2244 break;
2245 case CS7:
2246 cval = UART_LCR_WLEN7;
2247 break;
2248 default:
2249 case CS8:
2250 cval = UART_LCR_WLEN8;
2251 break;
2252 }
2253
2254 if (termios->c_cflag & CSTOPB)
2255 cval |= UART_LCR_STOP;
2256 if (termios->c_cflag & PARENB)
2257 cval |= UART_LCR_PARITY;
2258 if (!(termios->c_cflag & PARODD))
2259 cval |= UART_LCR_EPAR;
2260 #ifdef CMSPAR
2261 if (termios->c_cflag & CMSPAR)
2262 cval |= UART_LCR_SPAR;
2263 #endif
2264
2265 /*
2266 * Ask the core to calculate the divisor for us.
2267 */
2268 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
2269 quot = serial8250_get_divisor(port, baud);
2270
2271 /*
2272 * Oxford Semi 952 rev B workaround
2273 */
2274 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2275 quot++;
2276
2277 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2278 if (baud < 2400)
2279 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2280 else
2281 fcr = uart_config[up->port.type].fcr;
2282 }
2283
2284 /*
2285 * MCR-based auto flow control. When AFE is enabled, RTS will be
2286 * deasserted when the receive FIFO contains more characters than
2287 * the trigger, or the MCR RTS bit is cleared. In the case where
2288 * the remote UART is not using CTS auto flow control, we must
2289 * have sufficient FIFO entries for the latency of the remote
2290 * UART to respond. IOW, at least 32 bytes of FIFO.
2291 */
2292 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2293 up->mcr &= ~UART_MCR_AFE;
2294 if (termios->c_cflag & CRTSCTS)
2295 up->mcr |= UART_MCR_AFE;
2296 }
2297
2298 /*
2299 * Ok, we're now changing the port state. Do it with
2300 * interrupts disabled.
2301 */
2302 spin_lock_irqsave(&up->port.lock, flags);
2303
2304 /*
2305 * Update the per-port timeout.
2306 */
2307 uart_update_timeout(port, termios->c_cflag, baud);
2308
2309 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2310 if (termios->c_iflag & INPCK)
2311 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2312 if (termios->c_iflag & (BRKINT | PARMRK))
2313 up->port.read_status_mask |= UART_LSR_BI;
2314
2315 /*
2316 * Characteres to ignore
2317 */
2318 up->port.ignore_status_mask = 0;
2319 if (termios->c_iflag & IGNPAR)
2320 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2321 if (termios->c_iflag & IGNBRK) {
2322 up->port.ignore_status_mask |= UART_LSR_BI;
2323 /*
2324 * If we're ignoring parity and break indicators,
2325 * ignore overruns too (for real raw support).
2326 */
2327 if (termios->c_iflag & IGNPAR)
2328 up->port.ignore_status_mask |= UART_LSR_OE;
2329 }
2330
2331 /*
2332 * ignore all characters if CREAD is not set
2333 */
2334 if ((termios->c_cflag & CREAD) == 0)
2335 up->port.ignore_status_mask |= UART_LSR_DR;
2336
2337 /*
2338 * CTS flow control flag and modem status interrupts
2339 */
2340 up->ier &= ~UART_IER_MSI;
2341 if (!(up->bugs & UART_BUG_NOMSR) &&
2342 UART_ENABLE_MS(&up->port, termios->c_cflag))
2343 up->ier |= UART_IER_MSI;
2344 if (up->capabilities & UART_CAP_UUE)
2345 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
2346
2347 serial_out(up, UART_IER, up->ier);
2348
2349 if (up->capabilities & UART_CAP_EFR) {
2350 unsigned char efr = 0;
2351 /*
2352 * TI16C752/Startech hardware flow control. FIXME:
2353 * - TI16C752 requires control thresholds to be set.
2354 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2355 */
2356 if (termios->c_cflag & CRTSCTS)
2357 efr |= UART_EFR_CTS;
2358
2359 serial_outp(up, UART_LCR, 0xBF);
2360 serial_outp(up, UART_EFR, efr);
2361 }
2362
2363 #ifdef CONFIG_ARCH_OMAP
2364 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2365 if (cpu_is_omap1510() && is_omap_port(up)) {
2366 if (baud == 115200) {
2367 quot = 1;
2368 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2369 } else
2370 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2371 }
2372 #endif
2373
2374 if (up->capabilities & UART_NATSEMI) {
2375 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2376 serial_outp(up, UART_LCR, 0xe0);
2377 } else {
2378 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2379 }
2380
2381 serial_dl_write(up, quot);
2382
2383 /*
2384 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2385 * is written without DLAB set, this mode will be disabled.
2386 */
2387 if (up->port.type == PORT_16750)
2388 serial_outp(up, UART_FCR, fcr);
2389
2390 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2391 up->lcr = cval; /* Save LCR */
2392 if (up->port.type != PORT_16750) {
2393 if (fcr & UART_FCR_ENABLE_FIFO) {
2394 /* emulated UARTs (Lucent Venus 167x) need two steps */
2395 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2396 }
2397 serial_outp(up, UART_FCR, fcr); /* set fcr */
2398 }
2399 serial8250_set_mctrl(&up->port, up->port.mctrl);
2400 spin_unlock_irqrestore(&up->port.lock, flags);
2401 /* Don't rewrite B0 */
2402 if (tty_termios_baud_rate(termios))
2403 tty_termios_encode_baud_rate(termios, baud, baud);
2404 }
2405
2406 static void
2407 serial8250_pm(struct uart_port *port, unsigned int state,
2408 unsigned int oldstate)
2409 {
2410 struct uart_8250_port *p = (struct uart_8250_port *)port;
2411
2412 serial8250_set_sleep(p, state != 0);
2413
2414 if (p->pm)
2415 p->pm(port, state, oldstate);
2416 }
2417
2418 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2419 {
2420 if (pt->port.iotype == UPIO_AU)
2421 return 0x100000;
2422 #ifdef CONFIG_ARCH_OMAP
2423 if (is_omap_port(pt))
2424 return 0x16 << pt->port.regshift;
2425 #endif
2426 return 8 << pt->port.regshift;
2427 }
2428
2429 /*
2430 * Resource handling.
2431 */
2432 static int serial8250_request_std_resource(struct uart_8250_port *up)
2433 {
2434 unsigned int size = serial8250_port_size(up);
2435 int ret = 0;
2436
2437 switch (up->port.iotype) {
2438 case UPIO_AU:
2439 case UPIO_TSI:
2440 case UPIO_MEM32:
2441 case UPIO_MEM:
2442 case UPIO_DWAPB:
2443 if (!up->port.mapbase)
2444 break;
2445
2446 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2447 ret = -EBUSY;
2448 break;
2449 }
2450
2451 if (up->port.flags & UPF_IOREMAP) {
2452 up->port.membase = ioremap_nocache(up->port.mapbase,
2453 size);
2454 if (!up->port.membase) {
2455 release_mem_region(up->port.mapbase, size);
2456 ret = -ENOMEM;
2457 }
2458 }
2459 break;
2460
2461 case UPIO_HUB6:
2462 case UPIO_PORT:
2463 if (!request_region(up->port.iobase, size, "serial"))
2464 ret = -EBUSY;
2465 break;
2466 }
2467 return ret;
2468 }
2469
2470 static void serial8250_release_std_resource(struct uart_8250_port *up)
2471 {
2472 unsigned int size = serial8250_port_size(up);
2473
2474 switch (up->port.iotype) {
2475 case UPIO_AU:
2476 case UPIO_TSI:
2477 case UPIO_MEM32:
2478 case UPIO_MEM:
2479 case UPIO_DWAPB:
2480 if (!up->port.mapbase)
2481 break;
2482
2483 if (up->port.flags & UPF_IOREMAP) {
2484 iounmap(up->port.membase);
2485 up->port.membase = NULL;
2486 }
2487
2488 release_mem_region(up->port.mapbase, size);
2489 break;
2490
2491 case UPIO_HUB6:
2492 case UPIO_PORT:
2493 release_region(up->port.iobase, size);
2494 break;
2495 }
2496 }
2497
2498 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2499 {
2500 unsigned long start = UART_RSA_BASE << up->port.regshift;
2501 unsigned int size = 8 << up->port.regshift;
2502 int ret = -EINVAL;
2503
2504 switch (up->port.iotype) {
2505 case UPIO_HUB6:
2506 case UPIO_PORT:
2507 start += up->port.iobase;
2508 if (request_region(start, size, "serial-rsa"))
2509 ret = 0;
2510 else
2511 ret = -EBUSY;
2512 break;
2513 }
2514
2515 return ret;
2516 }
2517
2518 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2519 {
2520 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2521 unsigned int size = 8 << up->port.regshift;
2522
2523 switch (up->port.iotype) {
2524 case UPIO_HUB6:
2525 case UPIO_PORT:
2526 release_region(up->port.iobase + offset, size);
2527 break;
2528 }
2529 }
2530
2531 static void serial8250_release_port(struct uart_port *port)
2532 {
2533 struct uart_8250_port *up = (struct uart_8250_port *)port;
2534
2535 serial8250_release_std_resource(up);
2536 if (up->port.type == PORT_RSA)
2537 serial8250_release_rsa_resource(up);
2538 }
2539
2540 static int serial8250_request_port(struct uart_port *port)
2541 {
2542 struct uart_8250_port *up = (struct uart_8250_port *)port;
2543 int ret = 0;
2544
2545 ret = serial8250_request_std_resource(up);
2546 if (ret == 0 && up->port.type == PORT_RSA) {
2547 ret = serial8250_request_rsa_resource(up);
2548 if (ret < 0)
2549 serial8250_release_std_resource(up);
2550 }
2551
2552 return ret;
2553 }
2554
2555 static void serial8250_config_port(struct uart_port *port, int flags)
2556 {
2557 struct uart_8250_port *up = (struct uart_8250_port *)port;
2558 int probeflags = PROBE_ANY;
2559 int ret;
2560
2561 /*
2562 * Find the region that we can probe for. This in turn
2563 * tells us whether we can probe for the type of port.
2564 */
2565 ret = serial8250_request_std_resource(up);
2566 if (ret < 0)
2567 return;
2568
2569 ret = serial8250_request_rsa_resource(up);
2570 if (ret < 0)
2571 probeflags &= ~PROBE_RSA;
2572
2573 if (up->port.iotype != up->cur_iotype)
2574 set_io_from_upio(port);
2575
2576 if (flags & UART_CONFIG_TYPE)
2577 autoconfig(up, probeflags);
2578 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2579 autoconfig_irq(up);
2580
2581 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2582 serial8250_release_rsa_resource(up);
2583 if (up->port.type == PORT_UNKNOWN)
2584 serial8250_release_std_resource(up);
2585 }
2586
2587 static int
2588 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2589 {
2590 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2591 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2592 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2593 ser->type == PORT_STARTECH)
2594 return -EINVAL;
2595 return 0;
2596 }
2597
2598 static const char *
2599 serial8250_type(struct uart_port *port)
2600 {
2601 int type = port->type;
2602
2603 if (type >= ARRAY_SIZE(uart_config))
2604 type = 0;
2605 return uart_config[type].name;
2606 }
2607
2608 static struct uart_ops serial8250_pops = {
2609 .tx_empty = serial8250_tx_empty,
2610 .set_mctrl = serial8250_set_mctrl,
2611 .get_mctrl = serial8250_get_mctrl,
2612 .stop_tx = serial8250_stop_tx,
2613 .start_tx = serial8250_start_tx,
2614 .stop_rx = serial8250_stop_rx,
2615 .enable_ms = serial8250_enable_ms,
2616 .break_ctl = serial8250_break_ctl,
2617 .startup = serial8250_startup,
2618 .shutdown = serial8250_shutdown,
2619 .set_termios = serial8250_set_termios,
2620 .pm = serial8250_pm,
2621 .type = serial8250_type,
2622 .release_port = serial8250_release_port,
2623 .request_port = serial8250_request_port,
2624 .config_port = serial8250_config_port,
2625 .verify_port = serial8250_verify_port,
2626 #ifdef CONFIG_CONSOLE_POLL
2627 .poll_get_char = serial8250_get_poll_char,
2628 .poll_put_char = serial8250_put_poll_char,
2629 #endif
2630 };
2631
2632 static struct uart_8250_port serial8250_ports[UART_NR];
2633
2634 static void __init serial8250_isa_init_ports(void)
2635 {
2636 struct uart_8250_port *up;
2637 static int first = 1;
2638 int i;
2639
2640 if (!first)
2641 return;
2642 first = 0;
2643
2644 for (i = 0; i < nr_uarts; i++) {
2645 struct uart_8250_port *up = &serial8250_ports[i];
2646
2647 up->port.line = i;
2648 spin_lock_init(&up->port.lock);
2649
2650 init_timer(&up->timer);
2651 up->timer.function = serial8250_timeout;
2652
2653 /*
2654 * ALPHA_KLUDGE_MCR needs to be killed.
2655 */
2656 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2657 up->mcr_force = ALPHA_KLUDGE_MCR;
2658
2659 up->port.ops = &serial8250_pops;
2660 }
2661
2662 for (i = 0, up = serial8250_ports;
2663 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2664 i++, up++) {
2665 up->port.iobase = old_serial_port[i].port;
2666 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2667 up->port.uartclk = old_serial_port[i].baud_base * 16;
2668 up->port.flags = old_serial_port[i].flags;
2669 up->port.hub6 = old_serial_port[i].hub6;
2670 up->port.membase = old_serial_port[i].iomem_base;
2671 up->port.iotype = old_serial_port[i].io_type;
2672 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2673 set_io_from_upio(&up->port);
2674 if (share_irqs)
2675 up->port.flags |= UPF_SHARE_IRQ;
2676 }
2677 }
2678
2679 static void __init
2680 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2681 {
2682 int i;
2683
2684 for (i = 0; i < nr_uarts; i++) {
2685 struct uart_8250_port *up = &serial8250_ports[i];
2686 up->cur_iotype = 0xFF;
2687 }
2688
2689 serial8250_isa_init_ports();
2690
2691 for (i = 0; i < nr_uarts; i++) {
2692 struct uart_8250_port *up = &serial8250_ports[i];
2693
2694 up->port.dev = dev;
2695 uart_add_one_port(drv, &up->port);
2696 }
2697 }
2698
2699 #ifdef CONFIG_SERIAL_8250_CONSOLE
2700
2701 static void serial8250_console_putchar(struct uart_port *port, int ch)
2702 {
2703 struct uart_8250_port *up = (struct uart_8250_port *)port;
2704
2705 wait_for_xmitr(up, UART_LSR_THRE);
2706 serial_out(up, UART_TX, ch);
2707 }
2708
2709 /*
2710 * Print a string to the serial port trying not to disturb
2711 * any possible real use of the port...
2712 *
2713 * The console_lock must be held when we get here.
2714 */
2715 static void
2716 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2717 {
2718 struct uart_8250_port *up = &serial8250_ports[co->index];
2719 unsigned long flags;
2720 unsigned int ier;
2721 int locked = 1;
2722
2723 touch_nmi_watchdog();
2724
2725 local_irq_save(flags);
2726 if (up->port.sysrq) {
2727 /* serial8250_handle_port() already took the lock */
2728 locked = 0;
2729 } else if (oops_in_progress) {
2730 locked = spin_trylock(&up->port.lock);
2731 } else
2732 spin_lock(&up->port.lock);
2733
2734 /*
2735 * First save the IER then disable the interrupts
2736 */
2737 ier = serial_in(up, UART_IER);
2738
2739 if (up->capabilities & UART_CAP_UUE)
2740 serial_out(up, UART_IER, UART_IER_UUE);
2741 else
2742 serial_out(up, UART_IER, 0);
2743
2744 uart_console_write(&up->port, s, count, serial8250_console_putchar);
2745
2746 /*
2747 * Finally, wait for transmitter to become empty
2748 * and restore the IER
2749 */
2750 wait_for_xmitr(up, BOTH_EMPTY);
2751 serial_out(up, UART_IER, ier);
2752
2753 /*
2754 * The receive handling will happen properly because the
2755 * receive ready bit will still be set; it is not cleared
2756 * on read. However, modem control will not, we must
2757 * call it if we have saved something in the saved flags
2758 * while processing with interrupts off.
2759 */
2760 if (up->msr_saved_flags)
2761 check_modem_status(up);
2762
2763 if (locked)
2764 spin_unlock(&up->port.lock);
2765 local_irq_restore(flags);
2766 }
2767
2768 static int __init serial8250_console_setup(struct console *co, char *options)
2769 {
2770 struct uart_port *port;
2771 int baud = 9600;
2772 int bits = 8;
2773 int parity = 'n';
2774 int flow = 'n';
2775
2776 /*
2777 * Check whether an invalid uart number has been specified, and
2778 * if so, search for the first available port that does have
2779 * console support.
2780 */
2781 if (co->index >= nr_uarts)
2782 co->index = 0;
2783 port = &serial8250_ports[co->index].port;
2784 if (!port->iobase && !port->membase)
2785 return -ENODEV;
2786
2787 if (options)
2788 uart_parse_options(options, &baud, &parity, &bits, &flow);
2789
2790 return uart_set_options(port, co, baud, parity, bits, flow);
2791 }
2792
2793 static int serial8250_console_early_setup(void)
2794 {
2795 return serial8250_find_port_for_earlycon();
2796 }
2797
2798 static struct console serial8250_console = {
2799 .name = "ttyS",
2800 .write = serial8250_console_write,
2801 .device = uart_console_device,
2802 .setup = serial8250_console_setup,
2803 .early_setup = serial8250_console_early_setup,
2804 .flags = CON_PRINTBUFFER,
2805 .index = -1,
2806 .data = &serial8250_reg,
2807 };
2808
2809 static int __init serial8250_console_init(void)
2810 {
2811 if (nr_uarts > UART_NR)
2812 nr_uarts = UART_NR;
2813
2814 serial8250_isa_init_ports();
2815 register_console(&serial8250_console);
2816 return 0;
2817 }
2818 console_initcall(serial8250_console_init);
2819
2820 int serial8250_find_port(struct uart_port *p)
2821 {
2822 int line;
2823 struct uart_port *port;
2824
2825 for (line = 0; line < nr_uarts; line++) {
2826 port = &serial8250_ports[line].port;
2827 if (uart_match_port(p, port))
2828 return line;
2829 }
2830 return -ENODEV;
2831 }
2832
2833 #define SERIAL8250_CONSOLE &serial8250_console
2834 #else
2835 #define SERIAL8250_CONSOLE NULL
2836 #endif
2837
2838 static struct uart_driver serial8250_reg = {
2839 .owner = THIS_MODULE,
2840 .driver_name = "serial",
2841 .dev_name = "ttyS",
2842 .major = TTY_MAJOR,
2843 .minor = 64,
2844 .cons = SERIAL8250_CONSOLE,
2845 };
2846
2847 /*
2848 * early_serial_setup - early registration for 8250 ports
2849 *
2850 * Setup an 8250 port structure prior to console initialisation. Use
2851 * after console initialisation will cause undefined behaviour.
2852 */
2853 int __init early_serial_setup(struct uart_port *port)
2854 {
2855 struct uart_port *p;
2856
2857 if (port->line >= ARRAY_SIZE(serial8250_ports))
2858 return -ENODEV;
2859
2860 serial8250_isa_init_ports();
2861 p = &serial8250_ports[port->line].port;
2862 p->iobase = port->iobase;
2863 p->membase = port->membase;
2864 p->irq = port->irq;
2865 p->uartclk = port->uartclk;
2866 p->fifosize = port->fifosize;
2867 p->regshift = port->regshift;
2868 p->iotype = port->iotype;
2869 p->flags = port->flags;
2870 p->mapbase = port->mapbase;
2871 p->private_data = port->private_data;
2872 p->type = port->type;
2873 p->line = port->line;
2874
2875 set_io_from_upio(p);
2876 if (port->serial_in)
2877 p->serial_in = port->serial_in;
2878 if (port->serial_out)
2879 p->serial_out = port->serial_out;
2880
2881 return 0;
2882 }
2883
2884 /**
2885 * serial8250_suspend_port - suspend one serial port
2886 * @line: serial line number
2887 *
2888 * Suspend one serial port.
2889 */
2890 void serial8250_suspend_port(int line)
2891 {
2892 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2893 }
2894
2895 /**
2896 * serial8250_resume_port - resume one serial port
2897 * @line: serial line number
2898 *
2899 * Resume one serial port.
2900 */
2901 void serial8250_resume_port(int line)
2902 {
2903 struct uart_8250_port *up = &serial8250_ports[line];
2904
2905 if (up->capabilities & UART_NATSEMI) {
2906 unsigned char tmp;
2907
2908 /* Ensure it's still in high speed mode */
2909 serial_outp(up, UART_LCR, 0xE0);
2910
2911 tmp = serial_in(up, 0x04); /* EXCR2 */
2912 tmp &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
2913 tmp |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
2914 serial_outp(up, 0x04, tmp);
2915
2916 serial_outp(up, UART_LCR, 0);
2917 }
2918 uart_resume_port(&serial8250_reg, &up->port);
2919 }
2920
2921 /*
2922 * Register a set of serial devices attached to a platform device. The
2923 * list is terminated with a zero flags entry, which means we expect
2924 * all entries to have at least UPF_BOOT_AUTOCONF set.
2925 */
2926 static int __devinit serial8250_probe(struct platform_device *dev)
2927 {
2928 struct plat_serial8250_port *p = dev->dev.platform_data;
2929 struct uart_port port;
2930 int ret, i;
2931
2932 memset(&port, 0, sizeof(struct uart_port));
2933
2934 for (i = 0; p && p->flags != 0; p++, i++) {
2935 port.iobase = p->iobase;
2936 port.membase = p->membase;
2937 port.irq = p->irq;
2938 port.uartclk = p->uartclk;
2939 port.regshift = p->regshift;
2940 port.iotype = p->iotype;
2941 port.flags = p->flags;
2942 port.mapbase = p->mapbase;
2943 port.hub6 = p->hub6;
2944 port.private_data = p->private_data;
2945 port.type = p->type;
2946 port.serial_in = p->serial_in;
2947 port.serial_out = p->serial_out;
2948 port.dev = &dev->dev;
2949 if (share_irqs)
2950 port.flags |= UPF_SHARE_IRQ;
2951 ret = serial8250_register_port(&port);
2952 if (ret < 0) {
2953 dev_err(&dev->dev, "unable to register port at index %d "
2954 "(IO%lx MEM%llx IRQ%d): %d\n", i,
2955 p->iobase, (unsigned long long)p->mapbase,
2956 p->irq, ret);
2957 }
2958 }
2959 return 0;
2960 }
2961
2962 /*
2963 * Remove serial ports registered against a platform device.
2964 */
2965 static int __devexit serial8250_remove(struct platform_device *dev)
2966 {
2967 int i;
2968
2969 for (i = 0; i < nr_uarts; i++) {
2970 struct uart_8250_port *up = &serial8250_ports[i];
2971
2972 if (up->port.dev == &dev->dev)
2973 serial8250_unregister_port(i);
2974 }
2975 return 0;
2976 }
2977
2978 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
2979 {
2980 int i;
2981
2982 for (i = 0; i < UART_NR; i++) {
2983 struct uart_8250_port *up = &serial8250_ports[i];
2984
2985 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
2986 uart_suspend_port(&serial8250_reg, &up->port);
2987 }
2988
2989 return 0;
2990 }
2991
2992 static int serial8250_resume(struct platform_device *dev)
2993 {
2994 int i;
2995
2996 for (i = 0; i < UART_NR; i++) {
2997 struct uart_8250_port *up = &serial8250_ports[i];
2998
2999 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3000 serial8250_resume_port(i);
3001 }
3002
3003 return 0;
3004 }
3005
3006 static struct platform_driver serial8250_isa_driver = {
3007 .probe = serial8250_probe,
3008 .remove = __devexit_p(serial8250_remove),
3009 .suspend = serial8250_suspend,
3010 .resume = serial8250_resume,
3011 .driver = {
3012 .name = "serial8250",
3013 .owner = THIS_MODULE,
3014 },
3015 };
3016
3017 /*
3018 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3019 * in the table in include/asm/serial.h
3020 */
3021 static struct platform_device *serial8250_isa_devs;
3022
3023 /*
3024 * serial8250_register_port and serial8250_unregister_port allows for
3025 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3026 * modems and PCI multiport cards.
3027 */
3028 static DEFINE_MUTEX(serial_mutex);
3029
3030 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3031 {
3032 int i;
3033
3034 /*
3035 * First, find a port entry which matches.
3036 */
3037 for (i = 0; i < nr_uarts; i++)
3038 if (uart_match_port(&serial8250_ports[i].port, port))
3039 return &serial8250_ports[i];
3040
3041 /*
3042 * We didn't find a matching entry, so look for the first
3043 * free entry. We look for one which hasn't been previously
3044 * used (indicated by zero iobase).
3045 */
3046 for (i = 0; i < nr_uarts; i++)
3047 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3048 serial8250_ports[i].port.iobase == 0)
3049 return &serial8250_ports[i];
3050
3051 /*
3052 * That also failed. Last resort is to find any entry which
3053 * doesn't have a real port associated with it.
3054 */
3055 for (i = 0; i < nr_uarts; i++)
3056 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3057 return &serial8250_ports[i];
3058
3059 return NULL;
3060 }
3061
3062 /**
3063 * serial8250_register_port - register a serial port
3064 * @port: serial port template
3065 *
3066 * Configure the serial port specified by the request. If the
3067 * port exists and is in use, it is hung up and unregistered
3068 * first.
3069 *
3070 * The port is then probed and if necessary the IRQ is autodetected
3071 * If this fails an error is returned.
3072 *
3073 * On success the port is ready to use and the line number is returned.
3074 */
3075 int serial8250_register_port(struct uart_port *port)
3076 {
3077 struct uart_8250_port *uart;
3078 int ret = -ENOSPC;
3079
3080 if (port->uartclk == 0)
3081 return -EINVAL;
3082
3083 mutex_lock(&serial_mutex);
3084
3085 uart = serial8250_find_match_or_unused(port);
3086 if (uart) {
3087 uart_remove_one_port(&serial8250_reg, &uart->port);
3088
3089 uart->port.iobase = port->iobase;
3090 uart->port.membase = port->membase;
3091 uart->port.irq = port->irq;
3092 uart->port.uartclk = port->uartclk;
3093 uart->port.fifosize = port->fifosize;
3094 uart->port.regshift = port->regshift;
3095 uart->port.iotype = port->iotype;
3096 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3097 uart->port.mapbase = port->mapbase;
3098 uart->port.private_data = port->private_data;
3099 if (port->dev)
3100 uart->port.dev = port->dev;
3101
3102 if (port->flags & UPF_FIXED_TYPE) {
3103 uart->port.type = port->type;
3104 uart->port.fifosize = uart_config[port->type].fifo_size;
3105 uart->capabilities = uart_config[port->type].flags;
3106 uart->tx_loadsz = uart_config[port->type].tx_loadsz;
3107 }
3108
3109 set_io_from_upio(&uart->port);
3110 /* Possibly override default I/O functions. */
3111 if (port->serial_in)
3112 uart->port.serial_in = port->serial_in;
3113 if (port->serial_out)
3114 uart->port.serial_out = port->serial_out;
3115
3116 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3117 if (ret == 0)
3118 ret = uart->port.line;
3119 }
3120 mutex_unlock(&serial_mutex);
3121
3122 return ret;
3123 }
3124 EXPORT_SYMBOL(serial8250_register_port);
3125
3126 /**
3127 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3128 * @line: serial line number
3129 *
3130 * Remove one serial port. This may not be called from interrupt
3131 * context. We hand the port back to the our control.
3132 */
3133 void serial8250_unregister_port(int line)
3134 {
3135 struct uart_8250_port *uart = &serial8250_ports[line];
3136
3137 mutex_lock(&serial_mutex);
3138 uart_remove_one_port(&serial8250_reg, &uart->port);
3139 if (serial8250_isa_devs) {
3140 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3141 uart->port.type = PORT_UNKNOWN;
3142 uart->port.dev = &serial8250_isa_devs->dev;
3143 uart_add_one_port(&serial8250_reg, &uart->port);
3144 } else {
3145 uart->port.dev = NULL;
3146 }
3147 mutex_unlock(&serial_mutex);
3148 }
3149 EXPORT_SYMBOL(serial8250_unregister_port);
3150
3151 static int __init serial8250_init(void)
3152 {
3153 int ret;
3154
3155 if (nr_uarts > UART_NR)
3156 nr_uarts = UART_NR;
3157
3158 printk(KERN_INFO "Serial: 8250/16550 driver, "
3159 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3160 share_irqs ? "en" : "dis");
3161
3162 #ifdef CONFIG_SPARC
3163 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3164 #else
3165 serial8250_reg.nr = UART_NR;
3166 ret = uart_register_driver(&serial8250_reg);
3167 #endif
3168 if (ret)
3169 goto out;
3170
3171 serial8250_isa_devs = platform_device_alloc("serial8250",
3172 PLAT8250_DEV_LEGACY);
3173 if (!serial8250_isa_devs) {
3174 ret = -ENOMEM;
3175 goto unreg_uart_drv;
3176 }
3177
3178 ret = platform_device_add(serial8250_isa_devs);
3179 if (ret)
3180 goto put_dev;
3181
3182 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3183
3184 ret = platform_driver_register(&serial8250_isa_driver);
3185 if (ret == 0)
3186 goto out;
3187
3188 platform_device_del(serial8250_isa_devs);
3189 put_dev:
3190 platform_device_put(serial8250_isa_devs);
3191 unreg_uart_drv:
3192 #ifdef CONFIG_SPARC
3193 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3194 #else
3195 uart_unregister_driver(&serial8250_reg);
3196 #endif
3197 out:
3198 return ret;
3199 }
3200
3201 static void __exit serial8250_exit(void)
3202 {
3203 struct platform_device *isa_dev = serial8250_isa_devs;
3204
3205 /*
3206 * This tells serial8250_unregister_port() not to re-register
3207 * the ports (thereby making serial8250_isa_driver permanently
3208 * in use.)
3209 */
3210 serial8250_isa_devs = NULL;
3211
3212 platform_driver_unregister(&serial8250_isa_driver);
3213 platform_device_unregister(isa_dev);
3214
3215 #ifdef CONFIG_SPARC
3216 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3217 #else
3218 uart_unregister_driver(&serial8250_reg);
3219 #endif
3220 }
3221
3222 module_init(serial8250_init);
3223 module_exit(serial8250_exit);
3224
3225 EXPORT_SYMBOL(serial8250_suspend_port);
3226 EXPORT_SYMBOL(serial8250_resume_port);
3227
3228 MODULE_LICENSE("GPL");
3229 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3230
3231 module_param(share_irqs, uint, 0644);
3232 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3233 " (unsafe)");
3234
3235 module_param(nr_uarts, uint, 0644);
3236 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3237
3238 #ifdef CONFIG_SERIAL_8250_RSA
3239 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3240 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3241 #endif
3242 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
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