arch/arm/mach-davinci/gpio.c

   1 /*
   2  * TI DaVinci GPIO Support
   3  *
   4  * Copyright (c) 2006-2007 David Brownell
   5  * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  */
  12
  13 #include <linux/errno.h>
  14 #include <linux/kernel.h>
  15 #include <linux/clk.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18
  19 #include <mach/gpio.h>
  20
  21 #include <asm/mach/irq.h>
  22
  23 static DEFINE_SPINLOCK(gpio_lock);
  24
  25 struct davinci_gpio {
  26         struct gpio_chip        chip;
  27         struct gpio_controller  *__iomem regs;
  28         int                     irq_base;
  29 };
  30
  31 static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
  32
  33 /* create a non-inlined version */
  34 static struct gpio_controller __iomem * __init gpio2controller(unsigned gpio)
  35 {
  36         return __gpio_to_controller(gpio);
  37 }
  38
  39 static int __init davinci_gpio_irq_setup(void);
  40
  41 /*--------------------------------------------------------------------------*/
  42
  43 /*
  44  * board setup code *MUST* set PINMUX0 and PINMUX1 as
  45  * needed, and enable the GPIO clock.
  46  */
  47
  48 static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
  49 {
  50         struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
  51         struct gpio_controller *__iomem g = d->regs;
  52         u32 temp;
  53
  54         spin_lock(&gpio_lock);
  55         temp = __raw_readl(&g->dir);
  56         temp |= (1 << offset);
  57         __raw_writel(temp, &g->dir);
  58         spin_unlock(&gpio_lock);
  59
  60         return 0;
  61 }
  62
  63 /*
  64  * Read the pin's value (works even if it's set up as output);
  65  * returns zero/nonzero.
  66  *
  67  * Note that changes are synched to the GPIO clock, so reading values back
  68  * right after you've set them may give old values.
  69  */
  70 static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
  71 {
  72         struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
  73         struct gpio_controller *__iomem g = d->regs;
  74
  75         return (1 << offset) & __raw_readl(&g->in_data);
  76 }
  77
  78 static int
  79 davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
  80 {
  81         struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
  82         struct gpio_controller *__iomem g = d->regs;
  83         u32 temp;
  84         u32 mask = 1 << offset;
  85
  86         spin_lock(&gpio_lock);
  87         temp = __raw_readl(&g->dir);
  88         temp &= ~mask;
  89         __raw_writel(mask, value ? &g->set_data : &g->clr_data);
  90         __raw_writel(temp, &g->dir);
  91         spin_unlock(&gpio_lock);
  92         return 0;
  93 }
  94
  95 /*
  96  * Assuming the pin is muxed as a gpio output, set its output value.
  97  */
  98 static void
  99 davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 100 {
 101         struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
 102         struct gpio_controller *__iomem g = d->regs;
 103
 104         __raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
 105 }
 106
 107 static int __init davinci_gpio_setup(void)
 108 {
 109         int i, base;
 110         unsigned ngpio;
 111         struct davinci_soc_info *soc_info = &davinci_soc_info;
 112
 113         /*
 114          * The gpio banks conceptually expose a segmented bitmap,
 115          * and "ngpio" is one more than the largest zero-based
 116          * bit index that's valid.
 117          */
 118         ngpio = soc_info->gpio_num;
 119         if (ngpio == 0) {
 120                 pr_err("GPIO setup:  how many GPIOs?\n");
 121                 return -EINVAL;
 122         }
 123
 124         if (WARN_ON(DAVINCI_N_GPIO < ngpio))
 125                 ngpio = DAVINCI_N_GPIO;
 126
 127         for (i = 0, base = 0; base < ngpio; i++, base += 32) {
 128                 chips[i].chip.label = "DaVinci";
 129
 130                 chips[i].chip.direction_input = davinci_direction_in;
 131                 chips[i].chip.get = davinci_gpio_get;
 132                 chips[i].chip.direction_output = davinci_direction_out;
 133                 chips[i].chip.set = davinci_gpio_set;
 134
 135                 chips[i].chip.base = base;
 136                 chips[i].chip.ngpio = ngpio - base;
 137                 if (chips[i].chip.ngpio > 32)
 138                         chips[i].chip.ngpio = 32;
 139
 140                 chips[i].regs = gpio2controller(base);
 141
 142                 gpiochip_add(&chips[i].chip);
 143         }
 144
 145         davinci_gpio_irq_setup();
 146         return 0;
 147 }
 148 pure_initcall(davinci_gpio_setup);
 149
 150 /*--------------------------------------------------------------------------*/
 151 /*
 152  * We expect irqs will normally be set up as input pins, but they can also be
 153  * used as output pins ... which is convenient for testing.
 154  *
 155  * NOTE:  The first few GPIOs also have direct INTC hookups in addition
 156  * to their GPIOBNK0 irq, with a bit less overhead.
 157  *
 158  * All those INTC hookups (direct, plus several IRQ banks) can also
 159  * serve as EDMA event triggers.
 160  */
 161
 162 static void gpio_irq_disable(unsigned irq)
 163 {
 164         struct gpio_controller *__iomem g = get_irq_chip_data(irq);
 165         u32 mask = (u32) get_irq_data(irq);
 166
 167         __raw_writel(mask, &g->clr_falling);
 168         __raw_writel(mask, &g->clr_rising);
 169 }
 170
 171 static void gpio_irq_enable(unsigned irq)
 172 {
 173         struct gpio_controller *__iomem g = get_irq_chip_data(irq);
 174         u32 mask = (u32) get_irq_data(irq);
 175         unsigned status = irq_desc[irq].status;
 176
 177         status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
 178         if (!status)
 179                 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
 180
 181         if (status & IRQ_TYPE_EDGE_FALLING)
 182                 __raw_writel(mask, &g->set_falling);
 183         if (status & IRQ_TYPE_EDGE_RISING)
 184                 __raw_writel(mask, &g->set_rising);
 185 }
 186
 187 static int gpio_irq_type(unsigned irq, unsigned trigger)
 188 {
 189         struct gpio_controller *__iomem g = get_irq_chip_data(irq);
 190         u32 mask = (u32) get_irq_data(irq);
 191
 192         if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 193                 return -EINVAL;
 194
 195         irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
 196         irq_desc[irq].status |= trigger;
 197
 198         /* don't enable the IRQ if it's currently disabled */
 199         if (irq_desc[irq].depth == 0) {
 200                 __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
 201                              ? &g->set_falling : &g->clr_falling);
 202                 __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
 203                              ? &g->set_rising : &g->clr_rising);
 204         }
 205         return 0;
 206 }
 207
 208 static struct irq_chip gpio_irqchip = {
 209         .name           = "GPIO",
 210         .enable         = gpio_irq_enable,
 211         .disable        = gpio_irq_disable,
 212         .set_type       = gpio_irq_type,
 213 };
 214
 215 static void
 216 gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 217 {
 218         struct gpio_controller *__iomem g = get_irq_chip_data(irq);
 219         u32 mask = 0xffff;
 220
 221         /* we only care about one bank */
 222         if (irq & 1)
 223                 mask <<= 16;
 224
 225         /* temporarily mask (level sensitive) parent IRQ */
 226         desc->chip->mask(irq);
 227         desc->chip->ack(irq);
 228         while (1) {
 229                 u32             status;
 230                 int             n;
 231                 int             res;
 232
 233                 /* ack any irqs */
 234                 status = __raw_readl(&g->intstat) & mask;
 235                 if (!status)
 236                         break;
 237                 __raw_writel(status, &g->intstat);
 238                 if (irq & 1)
 239                         status >>= 16;
 240
 241                 /* now demux them to the right lowlevel handler */
 242                 n = (int)get_irq_data(irq);
 243                 while (status) {
 244                         res = ffs(status);
 245                         n += res;
 246                         generic_handle_irq(n - 1);
 247                         status >>= res;
 248                 }
 249         }
 250         desc->chip->unmask(irq);
 251         /* now it may re-trigger */
 252 }
 253
 254 static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
 255 {
 256         struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
 257
 258         if (d->irq_base >= 0)
 259                 return d->irq_base + offset;
 260         else
 261                 return -ENODEV;
 262 }
 263
 264 static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
 265 {
 266         struct davinci_soc_info *soc_info = &davinci_soc_info;
 267
 268         /* NOTE:  we assume for now that only irqs in the first gpio_chip
 269          * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
 270          */
 271         if (offset < soc_info->gpio_unbanked)
 272                 return soc_info->gpio_irq + offset;
 273         else
 274                 return -ENODEV;
 275 }
 276
 277 static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger)
 278 {
 279         struct gpio_controller *__iomem g = get_irq_chip_data(irq);
 280         u32 mask = (u32) get_irq_data(irq);
 281
 282         if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 283                 return -EINVAL;
 284
 285         __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
 286                      ? &g->set_falling : &g->clr_falling);
 287         __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
 288                      ? &g->set_rising : &g->clr_rising);
 289
 290         return 0;
 291 }
 292
 293 /*
 294  * NOTE:  for suspend/resume, probably best to make a platform_device with
 295  * suspend_late/resume_resume calls hooking into results of the set_wake()
 296  * calls ... so if no gpios are wakeup events the clock can be disabled,
 297  * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
 298  * (dm6446) can be set appropriately for GPIOV33 pins.
 299  */
 300
 301 static int __init davinci_gpio_irq_setup(void)
 302 {
 303         unsigned        gpio, irq, bank;
 304         struct clk      *clk;
 305         u32             binten = 0;
 306         unsigned        ngpio, bank_irq;
 307         struct davinci_soc_info *soc_info = &davinci_soc_info;
 308         struct gpio_controller  *__iomem g;
 309
 310         ngpio = soc_info->gpio_num;
 311
 312         bank_irq = soc_info->gpio_irq;
 313         if (bank_irq == 0) {
 314                 printk(KERN_ERR "Don't know first GPIO bank IRQ.\n");
 315                 return -EINVAL;
 316         }
 317
 318         clk = clk_get(NULL, "gpio");
 319         if (IS_ERR(clk)) {
 320                 printk(KERN_ERR "Error %ld getting gpio clock?\n",
 321                        PTR_ERR(clk));
 322                 return PTR_ERR(clk);
 323         }
 324         clk_enable(clk);
 325
 326         /* Arrange gpio_to_irq() support, handling either direct IRQs or
 327          * banked IRQs.  Having GPIOs in the first GPIO bank use direct
 328          * IRQs, while the others use banked IRQs, would need some setup
 329          * tweaks to recognize hardware which can do that.
 330          */
 331         for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
 332                 chips[bank].chip.to_irq = gpio_to_irq_banked;
 333                 chips[bank].irq_base = soc_info->gpio_unbanked
 334                         ? -EINVAL
 335                         : (soc_info->intc_irq_num + gpio);
 336         }
 337
 338         /*
 339          * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
 340          * controller only handling trigger modes.  We currently assume no
 341          * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
 342          */
 343         if (soc_info->gpio_unbanked) {
 344                 static struct irq_chip gpio_irqchip_unbanked;
 345
 346                 /* pass "bank 0" GPIO IRQs to AINTC */
 347                 chips[0].chip.to_irq = gpio_to_irq_unbanked;
 348                 binten = BIT(0);
 349
 350                 /* AINTC handles mask/unmask; GPIO handles triggering */
 351                 irq = bank_irq;
 352                 gpio_irqchip_unbanked = *get_irq_desc_chip(irq_to_desc(irq));
 353                 gpio_irqchip_unbanked.name = "GPIO-AINTC";
 354                 gpio_irqchip_unbanked.set_type = gpio_irq_type_unbanked;
 355
 356                 /* default trigger: both edges */
 357                 g = gpio2controller(0);
 358                 __raw_writel(~0, &g->set_falling);
 359                 __raw_writel(~0, &g->set_rising);
 360
 361                 /* set the direct IRQs up to use that irqchip */
 362                 for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
 363                         set_irq_chip(irq, &gpio_irqchip_unbanked);
 364                         set_irq_data(irq, (void *) __gpio_mask(gpio));
 365                         set_irq_chip_data(irq, g);
 366                         irq_desc[irq].status |= IRQ_TYPE_EDGE_BOTH;
 367                 }
 368
 369                 goto done;
 370         }
 371
 372         /*
 373          * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
 374          * then chain through our own handler.
 375          */
 376         for (gpio = 0, irq = gpio_to_irq(0), bank = 0;
 377                         gpio < ngpio;
 378                         bank++, bank_irq++) {
 379                 unsigned                i;
 380
 381                 /* disabled by default, enabled only as needed */
 382                 g = gpio2controller(gpio);
 383                 __raw_writel(~0, &g->clr_falling);
 384                 __raw_writel(~0, &g->clr_rising);
 385
 386                 /* set up all irqs in this bank */
 387                 set_irq_chained_handler(bank_irq, gpio_irq_handler);
 388                 set_irq_chip_data(bank_irq, g);
 389                 set_irq_data(bank_irq, (void *)irq);
 390
 391                 for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
 392                         set_irq_chip(irq, &gpio_irqchip);
 393                         set_irq_chip_data(irq, g);
 394                         set_irq_data(irq, (void *) __gpio_mask(gpio));
 395                         set_irq_handler(irq, handle_simple_irq);
 396                         set_irq_flags(irq, IRQF_VALID);
 397                 }
 398
 399                 binten |= BIT(bank);
 400         }
 401
 402 done:
 403         /* BINTEN -- per-bank interrupt enable. genirq would also let these
 404          * bits be set/cleared dynamically.
 405          */
 406         __raw_writel(binten, soc_info->gpio_base + 0x08);
 407
 408         printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));
 409
 410         return 0;
 411 }