arch/arm/plat-omap/include/plat/mcbsp.h

   1 /*
   2  * arch/arm/plat-omap/include/mach/mcbsp.h
   3  *
   4  * Defines for Multi-Channel Buffered Serial Port
   5  *
   6  * Copyright (C) 2002 RidgeRun, Inc.
   7  * Author: Steve Johnson
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22  *
  23  */
  24 #ifndef __ASM_ARCH_OMAP_MCBSP_H
  25 #define __ASM_ARCH_OMAP_MCBSP_H
  26
  27 #include <linux/completion.h>
  28 #include <linux/spinlock.h>
  29
  30 #include <mach/hardware.h>
  31 #include <plat/clock.h>
  32
  33 #define OMAP7XX_MCBSP1_BASE     0xfffb1000
  34 #define OMAP7XX_MCBSP2_BASE     0xfffb1800
  35
  36 #define OMAP1510_MCBSP1_BASE    0xe1011800
  37 #define OMAP1510_MCBSP2_BASE    0xfffb1000
  38 #define OMAP1510_MCBSP3_BASE    0xe1017000
  39
  40 #define OMAP1610_MCBSP1_BASE    0xe1011800
  41 #define OMAP1610_MCBSP2_BASE    0xfffb1000
  42 #define OMAP1610_MCBSP3_BASE    0xe1017000
  43
  44 #define OMAP24XX_MCBSP1_BASE    0x48074000
  45 #define OMAP24XX_MCBSP2_BASE    0x48076000
  46 #define OMAP2430_MCBSP3_BASE    0x4808c000
  47 #define OMAP2430_MCBSP4_BASE    0x4808e000
  48 #define OMAP2430_MCBSP5_BASE    0x48096000
  49
  50 #define OMAP34XX_MCBSP1_BASE    0x48074000
  51 #define OMAP34XX_MCBSP2_BASE    0x49022000
  52 #define OMAP34XX_MCBSP2_ST_BASE 0x49028000
  53 #define OMAP34XX_MCBSP3_BASE    0x49024000
  54 #define OMAP34XX_MCBSP3_ST_BASE 0x4902A000
  55 #define OMAP34XX_MCBSP3_BASE    0x49024000
  56 #define OMAP34XX_MCBSP4_BASE    0x49026000
  57 #define OMAP34XX_MCBSP5_BASE    0x48096000
  58
  59 #define OMAP44XX_MCBSP1_BASE    0x49022000
  60 #define OMAP44XX_MCBSP2_BASE    0x49024000
  61 #define OMAP44XX_MCBSP3_BASE    0x49026000
  62 #define OMAP44XX_MCBSP4_BASE    0x48074000
  63
  64 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
  65
  66 #define OMAP_MCBSP_REG_DRR2     0x00
  67 #define OMAP_MCBSP_REG_DRR1     0x02
  68 #define OMAP_MCBSP_REG_DXR2     0x04
  69 #define OMAP_MCBSP_REG_DXR1     0x06
  70 #define OMAP_MCBSP_REG_SPCR2    0x08
  71 #define OMAP_MCBSP_REG_SPCR1    0x0a
  72 #define OMAP_MCBSP_REG_RCR2     0x0c
  73 #define OMAP_MCBSP_REG_RCR1     0x0e
  74 #define OMAP_MCBSP_REG_XCR2     0x10
  75 #define OMAP_MCBSP_REG_XCR1     0x12
  76 #define OMAP_MCBSP_REG_SRGR2    0x14
  77 #define OMAP_MCBSP_REG_SRGR1    0x16
  78 #define OMAP_MCBSP_REG_MCR2     0x18
  79 #define OMAP_MCBSP_REG_MCR1     0x1a
  80 #define OMAP_MCBSP_REG_RCERA    0x1c
  81 #define OMAP_MCBSP_REG_RCERB    0x1e
  82 #define OMAP_MCBSP_REG_XCERA    0x20
  83 #define OMAP_MCBSP_REG_XCERB    0x22
  84 #define OMAP_MCBSP_REG_PCR0     0x24
  85 #define OMAP_MCBSP_REG_RCERC    0x26
  86 #define OMAP_MCBSP_REG_RCERD    0x28
  87 #define OMAP_MCBSP_REG_XCERC    0x2A
  88 #define OMAP_MCBSP_REG_XCERD    0x2C
  89 #define OMAP_MCBSP_REG_RCERE    0x2E
  90 #define OMAP_MCBSP_REG_RCERF    0x30
  91 #define OMAP_MCBSP_REG_XCERE    0x32
  92 #define OMAP_MCBSP_REG_XCERF    0x34
  93 #define OMAP_MCBSP_REG_RCERG    0x36
  94 #define OMAP_MCBSP_REG_RCERH    0x38
  95 #define OMAP_MCBSP_REG_XCERG    0x3A
  96 #define OMAP_MCBSP_REG_XCERH    0x3C
  97
  98 /* Dummy defines, these are not available on omap1 */
  99 #define OMAP_MCBSP_REG_XCCR     0x00
 100 #define OMAP_MCBSP_REG_RCCR     0x00
 101
 102 #define AUDIO_MCBSP_DATAWRITE   (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
 103 #define AUDIO_MCBSP_DATAREAD    (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)
 104
 105 #define AUDIO_MCBSP             OMAP_MCBSP1
 106 #define AUDIO_DMA_TX            OMAP_DMA_MCBSP1_TX
 107 #define AUDIO_DMA_RX            OMAP_DMA_MCBSP1_RX
 108
 109 #else
 110
 111 #define OMAP_MCBSP_REG_DRR2     0x00
 112 #define OMAP_MCBSP_REG_DRR1     0x04
 113 #define OMAP_MCBSP_REG_DXR2     0x08
 114 #define OMAP_MCBSP_REG_DXR1     0x0C
 115 #define OMAP_MCBSP_REG_DRR      0x00
 116 #define OMAP_MCBSP_REG_DXR      0x08
 117 #define OMAP_MCBSP_REG_SPCR2    0x10
 118 #define OMAP_MCBSP_REG_SPCR1    0x14
 119 #define OMAP_MCBSP_REG_RCR2     0x18
 120 #define OMAP_MCBSP_REG_RCR1     0x1C
 121 #define OMAP_MCBSP_REG_XCR2     0x20
 122 #define OMAP_MCBSP_REG_XCR1     0x24
 123 #define OMAP_MCBSP_REG_SRGR2    0x28
 124 #define OMAP_MCBSP_REG_SRGR1    0x2C
 125 #define OMAP_MCBSP_REG_MCR2     0x30
 126 #define OMAP_MCBSP_REG_MCR1     0x34
 127 #define OMAP_MCBSP_REG_RCERA    0x38
 128 #define OMAP_MCBSP_REG_RCERB    0x3C
 129 #define OMAP_MCBSP_REG_XCERA    0x40
 130 #define OMAP_MCBSP_REG_XCERB    0x44
 131 #define OMAP_MCBSP_REG_PCR0     0x48
 132 #define OMAP_MCBSP_REG_RCERC    0x4C
 133 #define OMAP_MCBSP_REG_RCERD    0x50
 134 #define OMAP_MCBSP_REG_XCERC    0x54
 135 #define OMAP_MCBSP_REG_XCERD    0x58
 136 #define OMAP_MCBSP_REG_RCERE    0x5C
 137 #define OMAP_MCBSP_REG_RCERF    0x60
 138 #define OMAP_MCBSP_REG_XCERE    0x64
 139 #define OMAP_MCBSP_REG_XCERF    0x68
 140 #define OMAP_MCBSP_REG_RCERG    0x6C
 141 #define OMAP_MCBSP_REG_RCERH    0x70
 142 #define OMAP_MCBSP_REG_XCERG    0x74
 143 #define OMAP_MCBSP_REG_XCERH    0x78
 144 #define OMAP_MCBSP_REG_SYSCON   0x8C
 145 #define OMAP_MCBSP_REG_THRSH2   0x90
 146 #define OMAP_MCBSP_REG_THRSH1   0x94
 147 #define OMAP_MCBSP_REG_IRQST    0xA0
 148 #define OMAP_MCBSP_REG_IRQEN    0xA4
 149 #define OMAP_MCBSP_REG_WAKEUPEN 0xA8
 150 #define OMAP_MCBSP_REG_XCCR     0xAC
 151 #define OMAP_MCBSP_REG_RCCR     0xB0
 152 #define OMAP_MCBSP_REG_SSELCR   0xBC
 153
 154 #define OMAP_ST_REG_REV         0x00
 155 #define OMAP_ST_REG_SYSCONFIG   0x10
 156 #define OMAP_ST_REG_IRQSTATUS   0x18
 157 #define OMAP_ST_REG_IRQENABLE   0x1C
 158 #define OMAP_ST_REG_SGAINCR     0x24
 159 #define OMAP_ST_REG_SFIRCR      0x28
 160 #define OMAP_ST_REG_SSELCR      0x2C
 161
 162 #define AUDIO_MCBSP_DATAWRITE   (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
 163 #define AUDIO_MCBSP_DATAREAD    (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)
 164
 165 #define AUDIO_MCBSP             OMAP_MCBSP2
 166 #define AUDIO_DMA_TX            OMAP24XX_DMA_MCBSP2_TX
 167 #define AUDIO_DMA_RX            OMAP24XX_DMA_MCBSP2_RX
 168
 169 #endif
 170
 171 /************************** McBSP SPCR1 bit definitions ***********************/
 172 #define RRST                    0x0001
 173 #define RRDY                    0x0002
 174 #define RFULL                   0x0004
 175 #define RSYNC_ERR               0x0008
 176 #define RINTM(value)            ((value)<<4)    /* bits 4:5 */
 177 #define ABIS                    0x0040
 178 #define DXENA                   0x0080
 179 #define CLKSTP(value)           ((value)<<11)   /* bits 11:12 */
 180 #define RJUST(value)            ((value)<<13)   /* bits 13:14 */
 181 #define ALB                     0x8000
 182 #define DLB                     0x8000
 183
 184 /************************** McBSP SPCR2 bit definitions ***********************/
 185 #define XRST            0x0001
 186 #define XRDY            0x0002
 187 #define XEMPTY          0x0004
 188 #define XSYNC_ERR       0x0008
 189 #define XINTM(value)    ((value)<<4)            /* bits 4:5 */
 190 #define GRST            0x0040
 191 #define FRST            0x0080
 192 #define SOFT            0x0100
 193 #define FREE            0x0200
 194
 195 /************************** McBSP PCR bit definitions *************************/
 196 #define CLKRP           0x0001
 197 #define CLKXP           0x0002
 198 #define FSRP            0x0004
 199 #define FSXP            0x0008
 200 #define DR_STAT         0x0010
 201 #define DX_STAT         0x0020
 202 #define CLKS_STAT       0x0040
 203 #define SCLKME          0x0080
 204 #define CLKRM           0x0100
 205 #define CLKXM           0x0200
 206 #define FSRM            0x0400
 207 #define FSXM            0x0800
 208 #define RIOEN           0x1000
 209 #define XIOEN           0x2000
 210 #define IDLE_EN         0x4000
 211
 212 /************************** McBSP RCR1 bit definitions ************************/
 213 #define RWDLEN1(value)          ((value)<<5)    /* Bits 5:7 */
 214 #define RFRLEN1(value)          ((value)<<8)    /* Bits 8:14 */
 215
 216 /************************** McBSP XCR1 bit definitions ************************/
 217 #define XWDLEN1(value)          ((value)<<5)    /* Bits 5:7 */
 218 #define XFRLEN1(value)          ((value)<<8)    /* Bits 8:14 */
 219
 220 /*************************** McBSP RCR2 bit definitions ***********************/
 221 #define RDATDLY(value)          (value)         /* Bits 0:1 */
 222 #define RFIG                    0x0004
 223 #define RCOMPAND(value)         ((value)<<3)    /* Bits 3:4 */
 224 #define RWDLEN2(value)          ((value)<<5)    /* Bits 5:7 */
 225 #define RFRLEN2(value)          ((value)<<8)    /* Bits 8:14 */
 226 #define RPHASE                  0x8000
 227
 228 /*************************** McBSP XCR2 bit definitions ***********************/
 229 #define XDATDLY(value)          (value)         /* Bits 0:1 */
 230 #define XFIG                    0x0004
 231 #define XCOMPAND(value)         ((value)<<3)    /* Bits 3:4 */
 232 #define XWDLEN2(value)          ((value)<<5)    /* Bits 5:7 */
 233 #define XFRLEN2(value)          ((value)<<8)    /* Bits 8:14 */
 234 #define XPHASE                  0x8000
 235
 236 /************************* McBSP SRGR1 bit definitions ************************/
 237 #define CLKGDV(value)           (value)         /* Bits 0:7 */
 238 #define FWID(value)             ((value)<<8)    /* Bits 8:15 */
 239
 240 /************************* McBSP SRGR2 bit definitions ************************/
 241 #define FPER(value)             (value)         /* Bits 0:11 */
 242 #define FSGM                    0x1000
 243 #define CLKSM                   0x2000
 244 #define CLKSP                   0x4000
 245 #define GSYNC                   0x8000
 246
 247 /************************* McBSP MCR1 bit definitions *************************/
 248 #define RMCM                    0x0001
 249 #define RCBLK(value)            ((value)<<2)    /* Bits 2:4 */
 250 #define RPABLK(value)           ((value)<<5)    /* Bits 5:6 */
 251 #define RPBBLK(value)           ((value)<<7)    /* Bits 7:8 */
 252
 253 /************************* McBSP MCR2 bit definitions *************************/
 254 #define XMCM(value)             (value)         /* Bits 0:1 */
 255 #define XCBLK(value)            ((value)<<2)    /* Bits 2:4 */
 256 #define XPABLK(value)           ((value)<<5)    /* Bits 5:6 */
 257 #define XPBBLK(value)           ((value)<<7)    /* Bits 7:8 */
 258
 259 /*********************** McBSP XCCR bit definitions *************************/
 260 #define EXTCLKGATE              0x8000
 261 #define PPCONNECT               0x4000
 262 #define DXENDLY(value)          ((value)<<12)   /* Bits 12:13 */
 263 #define XFULL_CYCLE             0x0800
 264 #define DILB                    0x0020
 265 #define XDMAEN                  0x0008
 266 #define XDISABLE                0x0001
 267
 268 /********************** McBSP RCCR bit definitions *************************/
 269 #define RFULL_CYCLE             0x0800
 270 #define RDMAEN                  0x0008
 271 #define RDISABLE                0x0001
 272
 273 /********************** McBSP SYSCONFIG bit definitions ********************/
 274 #define CLOCKACTIVITY(value)    ((value)<<8)
 275 #define SIDLEMODE(value)        ((value)<<3)
 276 #define ENAWAKEUP               0x0004
 277 #define SOFTRST                 0x0002
 278
 279 /********************** McBSP SSELCR bit definitions ***********************/
 280 #define SIDETONEEN              0x0400
 281
 282 /********************** McBSP Sidetone SYSCONFIG bit definitions ***********/
 283 #define ST_AUTOIDLE             0x0001
 284
 285 /********************** McBSP Sidetone SGAINCR bit definitions *************/
 286 #define ST_CH1GAIN(value)       ((value<<16))   /* Bits 16:31 */
 287 #define ST_CH0GAIN(value)       (value)         /* Bits 0:15 */
 288
 289 /********************** McBSP Sidetone SFIRCR bit definitions **************/
 290 #define ST_FIRCOEFF(value)      (value)         /* Bits 0:15 */
 291
 292 /********************** McBSP Sidetone SSELCR bit definitions **************/
 293 #define ST_COEFFWRDONE          0x0004
 294 #define ST_COEFFWREN            0x0002
 295 #define ST_SIDETONEEN           0x0001
 296
 297 /********************** McBSP DMA operating modes **************************/
 298 #define MCBSP_DMA_MODE_ELEMENT          0
 299 #define MCBSP_DMA_MODE_THRESHOLD        1
 300 #define MCBSP_DMA_MODE_FRAME            2
 301
 302 /********************** McBSP WAKEUPEN bit definitions *********************/
 303 #define XEMPTYEOFEN             0x4000
 304 #define XRDYEN                  0x0400
 305 #define XEOFEN                  0x0200
 306 #define XFSXEN                  0x0100
 307 #define XSYNCERREN              0x0080
 308 #define RRDYEN                  0x0008
 309 #define REOFEN                  0x0004
 310 #define RFSREN                  0x0002
 311 #define RSYNCERREN              0x0001
 312
 313 /* we don't do multichannel for now */
 314 struct omap_mcbsp_reg_cfg {
 315         u16 spcr2;
 316         u16 spcr1;
 317         u16 rcr2;
 318         u16 rcr1;
 319         u16 xcr2;
 320         u16 xcr1;
 321         u16 srgr2;
 322         u16 srgr1;
 323         u16 mcr2;
 324         u16 mcr1;
 325         u16 pcr0;
 326         u16 rcerc;
 327         u16 rcerd;
 328         u16 xcerc;
 329         u16 xcerd;
 330         u16 rcere;
 331         u16 rcerf;
 332         u16 xcere;
 333         u16 xcerf;
 334         u16 rcerg;
 335         u16 rcerh;
 336         u16 xcerg;
 337         u16 xcerh;
 338         u16 xccr;
 339         u16 rccr;
 340 };
 341
 342 typedef enum {
 343         OMAP_MCBSP1 = 0,
 344         OMAP_MCBSP2,
 345         OMAP_MCBSP3,
 346         OMAP_MCBSP4,
 347         OMAP_MCBSP5
 348 } omap_mcbsp_id;
 349
 350 typedef int __bitwise omap_mcbsp_io_type_t;
 351 #define OMAP_MCBSP_IRQ_IO ((__force omap_mcbsp_io_type_t) 1)
 352 #define OMAP_MCBSP_POLL_IO ((__force omap_mcbsp_io_type_t) 2)
 353
 354 typedef enum {
 355         OMAP_MCBSP_WORD_8 = 0,
 356         OMAP_MCBSP_WORD_12,
 357         OMAP_MCBSP_WORD_16,
 358         OMAP_MCBSP_WORD_20,
 359         OMAP_MCBSP_WORD_24,
 360         OMAP_MCBSP_WORD_32,
 361 } omap_mcbsp_word_length;
 362
 363 typedef enum {
 364         OMAP_MCBSP_CLK_RISING = 0,
 365         OMAP_MCBSP_CLK_FALLING,
 366 } omap_mcbsp_clk_polarity;
 367
 368 typedef enum {
 369         OMAP_MCBSP_FS_ACTIVE_HIGH = 0,
 370         OMAP_MCBSP_FS_ACTIVE_LOW,
 371 } omap_mcbsp_fs_polarity;
 372
 373 typedef enum {
 374         OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,
 375         OMAP_MCBSP_CLK_STP_MODE_DELAY,
 376 } omap_mcbsp_clk_stp_mode;
 377
 378
 379 /******* SPI specific mode **********/
 380 typedef enum {
 381         OMAP_MCBSP_SPI_MASTER = 0,
 382         OMAP_MCBSP_SPI_SLAVE,
 383 } omap_mcbsp_spi_mode;
 384
 385 struct omap_mcbsp_spi_cfg {
 386         omap_mcbsp_spi_mode             spi_mode;
 387         omap_mcbsp_clk_polarity         rx_clock_polarity;
 388         omap_mcbsp_clk_polarity         tx_clock_polarity;
 389         omap_mcbsp_fs_polarity          fsx_polarity;
 390         u8                              clk_div;
 391         omap_mcbsp_clk_stp_mode         clk_stp_mode;
 392         omap_mcbsp_word_length          word_length;
 393 };
 394
 395 /* Platform specific configuration */
 396 struct omap_mcbsp_ops {
 397         void (*request)(unsigned int);
 398         void (*free)(unsigned int);
 399 };
 400
 401 struct omap_mcbsp_platform_data {
 402         unsigned long phys_base;
 403         u8 dma_rx_sync, dma_tx_sync;
 404         u16 rx_irq, tx_irq;
 405         struct omap_mcbsp_ops *ops;
 406 #ifdef CONFIG_ARCH_OMAP3
 407         /* Sidetone block for McBSP 2 and 3 */
 408         unsigned long phys_base_st;
 409         u16 buffer_size;
 410 #endif
 411 };
 412
 413 struct omap_mcbsp_st_data {
 414         void __iomem *io_base_st;
 415         bool running;
 416         bool enabled;
 417         s16 taps[128];  /* Sidetone filter coefficients */
 418         int nr_taps;    /* Number of filter coefficients in use */
 419         s16 ch0gain;
 420         s16 ch1gain;
 421 };
 422
 423 struct omap_mcbsp {
 424         struct device *dev;
 425         unsigned long phys_base;
 426         void __iomem *io_base;
 427         u8 id;
 428         u8 free;
 429         omap_mcbsp_word_length rx_word_length;
 430         omap_mcbsp_word_length tx_word_length;
 431
 432         omap_mcbsp_io_type_t io_type; /* IRQ or poll */
 433         /* IRQ based TX/RX */
 434         int rx_irq;
 435         int tx_irq;
 436
 437         /* DMA stuff */
 438         u8 dma_rx_sync;
 439         short dma_rx_lch;
 440         u8 dma_tx_sync;
 441         short dma_tx_lch;
 442
 443         /* Completion queues */
 444         struct completion tx_irq_completion;
 445         struct completion rx_irq_completion;
 446         struct completion tx_dma_completion;
 447         struct completion rx_dma_completion;
 448
 449         /* Protect the field .free, while checking if the mcbsp is in use */
 450         spinlock_t lock;
 451         struct omap_mcbsp_platform_data *pdata;
 452         struct clk *iclk;
 453         struct clk *fclk;
 454 #ifdef CONFIG_ARCH_OMAP3
 455         struct omap_mcbsp_st_data *st_data;
 456         int dma_op_mode;
 457         u16 max_tx_thres;
 458         u16 max_rx_thres;
 459 #endif
 460         void *reg_cache;
 461 };
 462 extern struct omap_mcbsp **mcbsp_ptr;
 463 extern int omap_mcbsp_count, omap_mcbsp_cache_size;
 464
 465 int omap_mcbsp_init(void);
 466 void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
 467                                         int size);
 468 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
 469 #ifdef CONFIG_ARCH_OMAP3
 470 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
 471 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold);
 472 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id);
 473 u16 omap_mcbsp_get_max_rx_threshold(unsigned int id);
 474 int omap_mcbsp_get_dma_op_mode(unsigned int id);
 475 #else
 476 static inline void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
 477 { }
 478 static inline void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
 479 { }
 480 static inline u16 omap_mcbsp_get_max_tx_threshold(unsigned int id) { return 0; }
 481 static inline u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) { return 0; }
 482 static inline int omap_mcbsp_get_dma_op_mode(unsigned int id) { return 0; }
 483 #endif
 484 int omap_mcbsp_request(unsigned int id);
 485 void omap_mcbsp_free(unsigned int id);
 486 void omap_mcbsp_start(unsigned int id, int tx, int rx);
 487 void omap_mcbsp_stop(unsigned int id, int tx, int rx);
 488 void omap_mcbsp_xmit_word(unsigned int id, u32 word);
 489 u32 omap_mcbsp_recv_word(unsigned int id);
 490
 491 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
 492 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
 493 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word);
 494 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word);
 495
 496
 497 /* SPI specific API */
 498 void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);
 499
 500 /* Polled read/write functions */
 501 int omap_mcbsp_pollread(unsigned int id, u16 * buf);
 502 int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
 503 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
 504
 505 #ifdef CONFIG_ARCH_OMAP3
 506 /* Sidetone specific API */
 507 int omap_st_set_chgain(unsigned int id, int channel, s16 chgain);
 508 int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain);
 509 int omap_st_enable(unsigned int id);
 510 int omap_st_disable(unsigned int id);
 511 int omap_st_is_enabled(unsigned int id);
 512 #else
 513 static inline int omap_st_set_chgain(unsigned int id, int channel,
 514                                      s16 chgain) { return 0; }
 515 static inline int omap_st_get_chgain(unsigned int id, int channel,
 516                                      s16 *chgain) { return 0; }
 517 static inline int omap_st_enable(unsigned int id) { return 0; }
 518 static inline int omap_st_disable(unsigned int id) { return 0; }
 519 static inline int omap_st_is_enabled(unsigned int id) {  return 0; }
 520 #endif
 521
 522 #endif