2 * OMAP2/3 powerdomain control
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2009 Nokia Corporation
7 * Written by Paul Walmsley
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #ifndef ASM_ARM_ARCH_OMAP_POWERDOMAIN
15 #define ASM_ARM_ARCH_OMAP_POWERDOMAIN
17 #include <linux/types.h>
18 #include <linux/list.h>
20 #include <asm/atomic.h>
25 /* Powerdomain basic power states */
26 #define PWRDM_POWER_OFF 0x0
27 #define PWRDM_POWER_RET 0x1
28 #define PWRDM_POWER_INACTIVE 0x2
29 #define PWRDM_POWER_ON 0x3
31 #define PWRDM_MAX_PWRSTS 4
33 /* Powerdomain allowable state bitfields */
34 #define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \
35 (1 << PWRDM_POWER_ON))
37 #define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \
38 (1 << PWRDM_POWER_RET))
40 #define PWRSTS_RET_ON ((1 << PWRDM_POWER_RET) | \
41 (1 << PWRDM_POWER_ON))
43 #define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON))
46 /* Powerdomain flags */
47 #define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */
48 #define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits
49 * in MEM bank 1 position. This is
54 * Number of memory banks that are power-controllable. On OMAP4430, the
57 #define PWRDM_MAX_MEM_BANKS 5
60 * Maximum number of clockdomains that can be associated with a powerdomain.
61 * CORE powerdomain on OMAP4 is the worst case
63 #define PWRDM_MAX_CLKDMS 9
65 /* XXX A completely arbitrary number. What is reasonable here? */
66 #define PWRDM_TRANSITION_BAILOUT 100000
72 * struct powerdomain - OMAP powerdomain
73 * @name: Powerdomain name
74 * @omap_chip: represents the OMAP chip types containing this pwrdm
75 * @prcm_offs: the address offset from CM_BASE/PRM_BASE
76 * @pwrsts: Possible powerdomain power states
77 * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION
78 * @flags: Powerdomain flags
79 * @banks: Number of software-controllable memory banks in this powerdomain
80 * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION
81 * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON
82 * @pwrdm_clkdms: Clockdomains in this powerdomain
83 * @node: list_head linking all powerdomains
91 const struct omap_chip_id omap_chip
;
94 const u8 pwrsts_logic_ret
;
97 const u8 pwrsts_mem_ret
[PWRDM_MAX_MEM_BANKS
];
98 const u8 pwrsts_mem_on
[PWRDM_MAX_MEM_BANKS
];
99 struct clockdomain
*pwrdm_clkdms
[PWRDM_MAX_CLKDMS
];
100 struct list_head node
;
102 unsigned state_counter
[PWRDM_MAX_PWRSTS
];
103 unsigned ret_logic_off_counter
;
104 unsigned ret_mem_off_counter
[PWRDM_MAX_MEM_BANKS
];
106 #ifdef CONFIG_PM_DEBUG
108 s64 state_timer
[PWRDM_MAX_PWRSTS
];
113 void pwrdm_init(struct powerdomain
**pwrdm_list
);
115 struct powerdomain
*pwrdm_lookup(const char *name
);
117 int pwrdm_for_each(int (*fn
)(struct powerdomain
*pwrdm
, void *user
),
119 int pwrdm_for_each_nolock(int (*fn
)(struct powerdomain
*pwrdm
, void *user
),
122 int pwrdm_add_clkdm(struct powerdomain
*pwrdm
, struct clockdomain
*clkdm
);
123 int pwrdm_del_clkdm(struct powerdomain
*pwrdm
, struct clockdomain
*clkdm
);
124 int pwrdm_for_each_clkdm(struct powerdomain
*pwrdm
,
125 int (*fn
)(struct powerdomain
*pwrdm
,
126 struct clockdomain
*clkdm
));
128 int pwrdm_get_mem_bank_count(struct powerdomain
*pwrdm
);
130 int pwrdm_set_next_pwrst(struct powerdomain
*pwrdm
, u8 pwrst
);
131 int pwrdm_read_next_pwrst(struct powerdomain
*pwrdm
);
132 int pwrdm_read_pwrst(struct powerdomain
*pwrdm
);
133 int pwrdm_read_prev_pwrst(struct powerdomain
*pwrdm
);
134 int pwrdm_clear_all_prev_pwrst(struct powerdomain
*pwrdm
);
136 int pwrdm_set_logic_retst(struct powerdomain
*pwrdm
, u8 pwrst
);
137 int pwrdm_set_mem_onst(struct powerdomain
*pwrdm
, u8 bank
, u8 pwrst
);
138 int pwrdm_set_mem_retst(struct powerdomain
*pwrdm
, u8 bank
, u8 pwrst
);
140 int pwrdm_read_logic_pwrst(struct powerdomain
*pwrdm
);
141 int pwrdm_read_prev_logic_pwrst(struct powerdomain
*pwrdm
);
142 int pwrdm_read_logic_retst(struct powerdomain
*pwrdm
);
143 int pwrdm_read_mem_pwrst(struct powerdomain
*pwrdm
, u8 bank
);
144 int pwrdm_read_prev_mem_pwrst(struct powerdomain
*pwrdm
, u8 bank
);
145 int pwrdm_read_mem_retst(struct powerdomain
*pwrdm
, u8 bank
);
147 int pwrdm_enable_hdwr_sar(struct powerdomain
*pwrdm
);
148 int pwrdm_disable_hdwr_sar(struct powerdomain
*pwrdm
);
149 bool pwrdm_has_hdwr_sar(struct powerdomain
*pwrdm
);
151 int pwrdm_wait_transition(struct powerdomain
*pwrdm
);
153 int pwrdm_state_switch(struct powerdomain
*pwrdm
);
154 int pwrdm_clkdm_state_switch(struct clockdomain
*clkdm
);
155 int pwrdm_pre_transition(void);
156 int pwrdm_post_transition(void);