1 /* pci.c: UltraSparc PCI controller support.
3 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
7 * OF tree based PCI bus probing taken from the PowerPC port
8 * with minor modifications, see there for credits.
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/string.h>
14 #include <linux/sched.h>
15 #include <linux/capability.h>
16 #include <linux/errno.h>
17 #include <linux/pci.h>
18 #include <linux/msi.h>
19 #include <linux/irq.h>
20 #include <linux/init.h>
22 #include <linux/of_device.h>
24 #include <asm/uaccess.h>
25 #include <asm/pgtable.h>
32 /* List of all PCI controllers found in the system. */
33 struct pci_pbm_info
*pci_pbm_root
= NULL
;
35 /* Each PBM found gets a unique index. */
38 volatile int pci_poke_in_progress
;
39 volatile int pci_poke_cpu
= -1;
40 volatile int pci_poke_faulted
;
42 static DEFINE_SPINLOCK(pci_poke_lock
);
44 void pci_config_read8(u8
*addr
, u8
*ret
)
49 spin_lock_irqsave(&pci_poke_lock
, flags
);
50 pci_poke_cpu
= smp_processor_id();
51 pci_poke_in_progress
= 1;
53 __asm__
__volatile__("membar #Sync\n\t"
54 "lduba [%1] %2, %0\n\t"
57 : "r" (addr
), "i" (ASI_PHYS_BYPASS_EC_E_L
)
59 pci_poke_in_progress
= 0;
61 if (!pci_poke_faulted
)
63 spin_unlock_irqrestore(&pci_poke_lock
, flags
);
66 void pci_config_read16(u16
*addr
, u16
*ret
)
71 spin_lock_irqsave(&pci_poke_lock
, flags
);
72 pci_poke_cpu
= smp_processor_id();
73 pci_poke_in_progress
= 1;
75 __asm__
__volatile__("membar #Sync\n\t"
76 "lduha [%1] %2, %0\n\t"
79 : "r" (addr
), "i" (ASI_PHYS_BYPASS_EC_E_L
)
81 pci_poke_in_progress
= 0;
83 if (!pci_poke_faulted
)
85 spin_unlock_irqrestore(&pci_poke_lock
, flags
);
88 void pci_config_read32(u32
*addr
, u32
*ret
)
93 spin_lock_irqsave(&pci_poke_lock
, flags
);
94 pci_poke_cpu
= smp_processor_id();
95 pci_poke_in_progress
= 1;
97 __asm__
__volatile__("membar #Sync\n\t"
98 "lduwa [%1] %2, %0\n\t"
101 : "r" (addr
), "i" (ASI_PHYS_BYPASS_EC_E_L
)
103 pci_poke_in_progress
= 0;
105 if (!pci_poke_faulted
)
107 spin_unlock_irqrestore(&pci_poke_lock
, flags
);
110 void pci_config_write8(u8
*addr
, u8 val
)
114 spin_lock_irqsave(&pci_poke_lock
, flags
);
115 pci_poke_cpu
= smp_processor_id();
116 pci_poke_in_progress
= 1;
117 pci_poke_faulted
= 0;
118 __asm__
__volatile__("membar #Sync\n\t"
119 "stba %0, [%1] %2\n\t"
122 : "r" (val
), "r" (addr
), "i" (ASI_PHYS_BYPASS_EC_E_L
)
124 pci_poke_in_progress
= 0;
126 spin_unlock_irqrestore(&pci_poke_lock
, flags
);
129 void pci_config_write16(u16
*addr
, u16 val
)
133 spin_lock_irqsave(&pci_poke_lock
, flags
);
134 pci_poke_cpu
= smp_processor_id();
135 pci_poke_in_progress
= 1;
136 pci_poke_faulted
= 0;
137 __asm__
__volatile__("membar #Sync\n\t"
138 "stha %0, [%1] %2\n\t"
141 : "r" (val
), "r" (addr
), "i" (ASI_PHYS_BYPASS_EC_E_L
)
143 pci_poke_in_progress
= 0;
145 spin_unlock_irqrestore(&pci_poke_lock
, flags
);
148 void pci_config_write32(u32
*addr
, u32 val
)
152 spin_lock_irqsave(&pci_poke_lock
, flags
);
153 pci_poke_cpu
= smp_processor_id();
154 pci_poke_in_progress
= 1;
155 pci_poke_faulted
= 0;
156 __asm__
__volatile__("membar #Sync\n\t"
157 "stwa %0, [%1] %2\n\t"
160 : "r" (val
), "r" (addr
), "i" (ASI_PHYS_BYPASS_EC_E_L
)
162 pci_poke_in_progress
= 0;
164 spin_unlock_irqrestore(&pci_poke_lock
, flags
);
167 static int ofpci_verbose
;
169 static int __init
ofpci_debug(char *str
)
173 get_option(&str
, &val
);
179 __setup("ofpci_debug=", ofpci_debug
);
181 static unsigned long pci_parse_of_flags(u32 addr0
)
183 unsigned long flags
= 0;
185 if (addr0
& 0x02000000) {
186 flags
= IORESOURCE_MEM
| PCI_BASE_ADDRESS_SPACE_MEMORY
;
187 flags
|= (addr0
>> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64
;
188 flags
|= (addr0
>> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M
;
189 if (addr0
& 0x40000000)
190 flags
|= IORESOURCE_PREFETCH
191 | PCI_BASE_ADDRESS_MEM_PREFETCH
;
192 } else if (addr0
& 0x01000000)
193 flags
= IORESOURCE_IO
| PCI_BASE_ADDRESS_SPACE_IO
;
197 /* The of_device layer has translated all of the assigned-address properties
198 * into physical address resources, we only have to figure out the register
201 static void pci_parse_of_addrs(struct of_device
*op
,
202 struct device_node
*node
,
205 struct resource
*op_res
;
209 addrs
= of_get_property(node
, "assigned-addresses", &proplen
);
213 printk(" parse addresses (%d bytes) @ %p\n",
215 op_res
= &op
->resource
[0];
216 for (; proplen
>= 20; proplen
-= 20, addrs
+= 5, op_res
++) {
217 struct resource
*res
;
221 flags
= pci_parse_of_flags(addrs
[0]);
226 printk(" start: %llx, end: %llx, i: %x\n",
227 op_res
->start
, op_res
->end
, i
);
229 if (PCI_BASE_ADDRESS_0
<= i
&& i
<= PCI_BASE_ADDRESS_5
) {
230 res
= &dev
->resource
[(i
- PCI_BASE_ADDRESS_0
) >> 2];
231 } else if (i
== dev
->rom_base_reg
) {
232 res
= &dev
->resource
[PCI_ROM_RESOURCE
];
233 flags
|= IORESOURCE_READONLY
| IORESOURCE_CACHEABLE
;
235 printk(KERN_ERR
"PCI: bad cfg reg num 0x%x\n", i
);
238 res
->start
= op_res
->start
;
239 res
->end
= op_res
->end
;
241 res
->name
= pci_name(dev
);
245 static struct pci_dev
*of_create_pci_dev(struct pci_pbm_info
*pbm
,
246 struct device_node
*node
,
247 struct pci_bus
*bus
, int devfn
)
249 struct dev_archdata
*sd
;
250 struct pci_slot
*slot
;
251 struct of_device
*op
;
256 dev
= alloc_pci_dev();
260 sd
= &dev
->dev
.archdata
;
261 sd
->iommu
= pbm
->iommu
;
263 sd
->host_controller
= pbm
;
264 sd
->prom_node
= node
;
265 sd
->op
= op
= of_find_device_by_node(node
);
266 sd
->numa_node
= pbm
->numa_node
;
268 sd
= &op
->dev
.archdata
;
269 sd
->iommu
= pbm
->iommu
;
271 sd
->numa_node
= pbm
->numa_node
;
273 if (!strcmp(node
->name
, "ebus"))
274 of_propagate_archdata(op
);
276 type
= of_get_property(node
, "device_type", NULL
);
281 printk(" create device, devfn: %x, type: %s\n",
286 dev
->dev
.parent
= bus
->bridge
;
287 dev
->dev
.bus
= &pci_bus_type
;
289 dev
->multifunction
= 0; /* maybe a lie? */
290 set_pcie_port_type(dev
);
292 list_for_each_entry(slot
, &dev
->bus
->slots
, list
)
293 if (PCI_SLOT(dev
->devfn
) == slot
->number
)
296 dev
->vendor
= of_getintprop_default(node
, "vendor-id", 0xffff);
297 dev
->device
= of_getintprop_default(node
, "device-id", 0xffff);
298 dev
->subsystem_vendor
=
299 of_getintprop_default(node
, "subsystem-vendor-id", 0);
300 dev
->subsystem_device
=
301 of_getintprop_default(node
, "subsystem-id", 0);
303 dev
->cfg_size
= pci_cfg_space_size(dev
);
305 /* We can't actually use the firmware value, we have
306 * to read what is in the register right now. One
307 * reason is that in the case of IDE interfaces the
308 * firmware can sample the value before the the IDE
309 * interface is programmed into native mode.
311 pci_read_config_dword(dev
, PCI_CLASS_REVISION
, &class);
312 dev
->class = class >> 8;
313 dev
->revision
= class & 0xff;
315 dev_set_name(&dev
->dev
, "%04x:%02x:%02x.%d", pci_domain_nr(bus
),
316 dev
->bus
->number
, PCI_SLOT(devfn
), PCI_FUNC(devfn
));
319 printk(" class: 0x%x device name: %s\n",
320 dev
->class, pci_name(dev
));
322 /* I have seen IDE devices which will not respond to
323 * the bmdma simplex check reads if bus mastering is
326 if ((dev
->class >> 8) == PCI_CLASS_STORAGE_IDE
)
329 dev
->current_state
= 4; /* unknown power state */
330 dev
->error_state
= pci_channel_io_normal
;
331 dev
->dma_mask
= 0xffffffff;
333 if (!strcmp(node
->name
, "pci")) {
334 /* a PCI-PCI bridge */
335 dev
->hdr_type
= PCI_HEADER_TYPE_BRIDGE
;
336 dev
->rom_base_reg
= PCI_ROM_ADDRESS1
;
337 } else if (!strcmp(type
, "cardbus")) {
338 dev
->hdr_type
= PCI_HEADER_TYPE_CARDBUS
;
340 dev
->hdr_type
= PCI_HEADER_TYPE_NORMAL
;
341 dev
->rom_base_reg
= PCI_ROM_ADDRESS
;
343 dev
->irq
= sd
->op
->irqs
[0];
344 if (dev
->irq
== 0xffffffff)
345 dev
->irq
= PCI_IRQ_NONE
;
348 pci_parse_of_addrs(sd
->op
, node
, dev
);
351 printk(" adding to system ...\n");
353 pci_device_add(dev
, bus
);
358 static void __devinit
apb_calc_first_last(u8 map
, u32
*first_p
, u32
*last_p
)
360 u32 idx
, first
, last
;
364 for (idx
= 0; idx
< 8; idx
++) {
365 if ((map
& (1 << idx
)) != 0) {
377 static void pci_resource_adjust(struct resource
*res
,
378 struct resource
*root
)
380 res
->start
+= root
->start
;
381 res
->end
+= root
->start
;
384 /* For PCI bus devices which lack a 'ranges' property we interrogate
385 * the config space values to set the resources, just like the generic
386 * Linux PCI probing code does.
388 static void __devinit
pci_cfg_fake_ranges(struct pci_dev
*dev
,
390 struct pci_pbm_info
*pbm
)
392 struct resource
*res
;
393 u8 io_base_lo
, io_limit_lo
;
394 u16 mem_base_lo
, mem_limit_lo
;
395 unsigned long base
, limit
;
397 pci_read_config_byte(dev
, PCI_IO_BASE
, &io_base_lo
);
398 pci_read_config_byte(dev
, PCI_IO_LIMIT
, &io_limit_lo
);
399 base
= (io_base_lo
& PCI_IO_RANGE_MASK
) << 8;
400 limit
= (io_limit_lo
& PCI_IO_RANGE_MASK
) << 8;
402 if ((io_base_lo
& PCI_IO_RANGE_TYPE_MASK
) == PCI_IO_RANGE_TYPE_32
) {
403 u16 io_base_hi
, io_limit_hi
;
405 pci_read_config_word(dev
, PCI_IO_BASE_UPPER16
, &io_base_hi
);
406 pci_read_config_word(dev
, PCI_IO_LIMIT_UPPER16
, &io_limit_hi
);
407 base
|= (io_base_hi
<< 16);
408 limit
|= (io_limit_hi
<< 16);
411 res
= bus
->resource
[0];
413 res
->flags
= (io_base_lo
& PCI_IO_RANGE_TYPE_MASK
) | IORESOURCE_IO
;
417 res
->end
= limit
+ 0xfff;
418 pci_resource_adjust(res
, &pbm
->io_space
);
421 pci_read_config_word(dev
, PCI_MEMORY_BASE
, &mem_base_lo
);
422 pci_read_config_word(dev
, PCI_MEMORY_LIMIT
, &mem_limit_lo
);
423 base
= (mem_base_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
424 limit
= (mem_limit_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
426 res
= bus
->resource
[1];
428 res
->flags
= ((mem_base_lo
& PCI_MEMORY_RANGE_TYPE_MASK
) |
431 res
->end
= limit
+ 0xfffff;
432 pci_resource_adjust(res
, &pbm
->mem_space
);
435 pci_read_config_word(dev
, PCI_PREF_MEMORY_BASE
, &mem_base_lo
);
436 pci_read_config_word(dev
, PCI_PREF_MEMORY_LIMIT
, &mem_limit_lo
);
437 base
= (mem_base_lo
& PCI_PREF_RANGE_MASK
) << 16;
438 limit
= (mem_limit_lo
& PCI_PREF_RANGE_MASK
) << 16;
440 if ((mem_base_lo
& PCI_PREF_RANGE_TYPE_MASK
) == PCI_PREF_RANGE_TYPE_64
) {
441 u32 mem_base_hi
, mem_limit_hi
;
443 pci_read_config_dword(dev
, PCI_PREF_BASE_UPPER32
, &mem_base_hi
);
444 pci_read_config_dword(dev
, PCI_PREF_LIMIT_UPPER32
, &mem_limit_hi
);
447 * Some bridges set the base > limit by default, and some
448 * (broken) BIOSes do not initialize them. If we find
449 * this, just assume they are not being used.
451 if (mem_base_hi
<= mem_limit_hi
) {
452 base
|= ((long) mem_base_hi
) << 32;
453 limit
|= ((long) mem_limit_hi
) << 32;
457 res
= bus
->resource
[2];
459 res
->flags
= ((mem_base_lo
& PCI_MEMORY_RANGE_TYPE_MASK
) |
460 IORESOURCE_MEM
| IORESOURCE_PREFETCH
);
462 res
->end
= limit
+ 0xfffff;
463 pci_resource_adjust(res
, &pbm
->mem_space
);
467 /* Cook up fake bus resources for SUNW,simba PCI bridges which lack
468 * a proper 'ranges' property.
470 static void __devinit
apb_fake_ranges(struct pci_dev
*dev
,
472 struct pci_pbm_info
*pbm
)
474 struct resource
*res
;
478 pci_read_config_byte(dev
, APB_IO_ADDRESS_MAP
, &map
);
479 apb_calc_first_last(map
, &first
, &last
);
480 res
= bus
->resource
[0];
481 res
->start
= (first
<< 21);
482 res
->end
= (last
<< 21) + ((1 << 21) - 1);
483 res
->flags
= IORESOURCE_IO
;
484 pci_resource_adjust(res
, &pbm
->io_space
);
486 pci_read_config_byte(dev
, APB_MEM_ADDRESS_MAP
, &map
);
487 apb_calc_first_last(map
, &first
, &last
);
488 res
= bus
->resource
[1];
489 res
->start
= (first
<< 21);
490 res
->end
= (last
<< 21) + ((1 << 21) - 1);
491 res
->flags
= IORESOURCE_MEM
;
492 pci_resource_adjust(res
, &pbm
->mem_space
);
495 static void __devinit
pci_of_scan_bus(struct pci_pbm_info
*pbm
,
496 struct device_node
*node
,
497 struct pci_bus
*bus
);
499 #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
501 static void __devinit
of_scan_pci_bridge(struct pci_pbm_info
*pbm
,
502 struct device_node
*node
,
506 const u32
*busrange
, *ranges
;
508 struct resource
*res
;
513 printk("of_scan_pci_bridge(%s)\n", node
->full_name
);
515 /* parse bus-range property */
516 busrange
= of_get_property(node
, "bus-range", &len
);
517 if (busrange
== NULL
|| len
!= 8) {
518 printk(KERN_DEBUG
"Can't get bus-range for PCI-PCI bridge %s\n",
522 ranges
= of_get_property(node
, "ranges", &len
);
524 if (ranges
== NULL
) {
525 const char *model
= of_get_property(node
, "model", NULL
);
526 if (model
&& !strcmp(model
, "SUNW,simba"))
530 bus
= pci_add_new_bus(dev
->bus
, dev
, busrange
[0]);
532 printk(KERN_ERR
"Failed to create pci bus for %s\n",
537 bus
->primary
= dev
->bus
->number
;
538 bus
->subordinate
= busrange
[1];
541 /* parse ranges property, or cook one up by hand for Simba */
542 /* PCI #address-cells == 3 and #size-cells == 2 always */
543 res
= &dev
->resource
[PCI_BRIDGE_RESOURCES
];
544 for (i
= 0; i
< PCI_NUM_RESOURCES
- PCI_BRIDGE_RESOURCES
; ++i
) {
546 bus
->resource
[i
] = res
;
550 apb_fake_ranges(dev
, bus
, pbm
);
552 } else if (ranges
== NULL
) {
553 pci_cfg_fake_ranges(dev
, bus
, pbm
);
557 for (; len
>= 32; len
-= 32, ranges
+= 8) {
558 struct resource
*root
;
560 flags
= pci_parse_of_flags(ranges
[0]);
561 size
= GET_64BIT(ranges
, 6);
562 if (flags
== 0 || size
== 0)
564 if (flags
& IORESOURCE_IO
) {
565 res
= bus
->resource
[0];
567 printk(KERN_ERR
"PCI: ignoring extra I/O range"
568 " for bridge %s\n", node
->full_name
);
571 root
= &pbm
->io_space
;
573 if (i
>= PCI_NUM_RESOURCES
- PCI_BRIDGE_RESOURCES
) {
574 printk(KERN_ERR
"PCI: too many memory ranges"
575 " for bridge %s\n", node
->full_name
);
578 res
= bus
->resource
[i
];
580 root
= &pbm
->mem_space
;
583 res
->start
= GET_64BIT(ranges
, 1);
584 res
->end
= res
->start
+ size
- 1;
587 /* Another way to implement this would be to add an of_device
588 * layer routine that can calculate a resource for a given
589 * range property value in a PCI device.
591 pci_resource_adjust(res
, root
);
594 sprintf(bus
->name
, "PCI Bus %04x:%02x", pci_domain_nr(bus
),
597 printk(" bus name: %s\n", bus
->name
);
599 pci_of_scan_bus(pbm
, node
, bus
);
602 static void __devinit
pci_of_scan_bus(struct pci_pbm_info
*pbm
,
603 struct device_node
*node
,
606 struct device_node
*child
;
608 int reglen
, devfn
, prev_devfn
;
612 printk("PCI: scan_bus[%s] bus no %d\n",
613 node
->full_name
, bus
->number
);
617 while ((child
= of_get_next_child(node
, child
)) != NULL
) {
619 printk(" * %s\n", child
->full_name
);
620 reg
= of_get_property(child
, "reg", ®len
);
621 if (reg
== NULL
|| reglen
< 20)
624 devfn
= (reg
[0] >> 8) & 0xff;
626 /* This is a workaround for some device trees
627 * which list PCI devices twice. On the V100
628 * for example, device number 3 is listed twice.
629 * Once as "pm" and once again as "lomp".
631 if (devfn
== prev_devfn
)
635 /* create a new pci_dev for this device */
636 dev
= of_create_pci_dev(pbm
, child
, bus
, devfn
);
640 printk("PCI: dev header type: %x\n",
643 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
||
644 dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
)
645 of_scan_pci_bridge(pbm
, child
, dev
);
650 show_pciobppath_attr(struct device
* dev
, struct device_attribute
* attr
, char * buf
)
652 struct pci_dev
*pdev
;
653 struct device_node
*dp
;
655 pdev
= to_pci_dev(dev
);
656 dp
= pdev
->dev
.archdata
.prom_node
;
658 return snprintf (buf
, PAGE_SIZE
, "%s\n", dp
->full_name
);
661 static DEVICE_ATTR(obppath
, S_IRUSR
| S_IRGRP
| S_IROTH
, show_pciobppath_attr
, NULL
);
663 static void __devinit
pci_bus_register_of_sysfs(struct pci_bus
*bus
)
666 struct pci_bus
*child_bus
;
669 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
670 /* we don't really care if we can create this file or
671 * not, but we need to assign the result of the call
672 * or the world will fall under alien invasion and
673 * everybody will be frozen on a spaceship ready to be
674 * eaten on alpha centauri by some green and jelly
677 err
= sysfs_create_file(&dev
->dev
.kobj
, &dev_attr_obppath
.attr
);
679 list_for_each_entry(child_bus
, &bus
->children
, node
)
680 pci_bus_register_of_sysfs(child_bus
);
683 struct pci_bus
* __devinit
pci_scan_one_pbm(struct pci_pbm_info
*pbm
,
684 struct device
*parent
)
686 struct device_node
*node
= pbm
->op
->node
;
689 printk("PCI: Scanning PBM %s\n", node
->full_name
);
691 bus
= pci_create_bus(parent
, pbm
->pci_first_busno
, pbm
->pci_ops
, pbm
);
693 printk(KERN_ERR
"Failed to create bus for %s\n",
697 bus
->secondary
= pbm
->pci_first_busno
;
698 bus
->subordinate
= pbm
->pci_last_busno
;
700 bus
->resource
[0] = &pbm
->io_space
;
701 bus
->resource
[1] = &pbm
->mem_space
;
703 pci_of_scan_bus(pbm
, node
, bus
);
704 pci_bus_add_devices(bus
);
705 pci_bus_register_of_sysfs(bus
);
710 void __devinit
pcibios_fixup_bus(struct pci_bus
*pbus
)
712 struct pci_pbm_info
*pbm
= pbus
->sysdata
;
714 /* Generic PCI bus probing sets these to point at
715 * &io{port,mem}_resouce which is wrong for us.
717 pbus
->resource
[0] = &pbm
->io_space
;
718 pbus
->resource
[1] = &pbm
->mem_space
;
721 void pcibios_update_irq(struct pci_dev
*pdev
, int irq
)
725 resource_size_t
pcibios_align_resource(void *data
, const struct resource
*res
,
726 resource_size_t size
, resource_size_t align
)
731 int pcibios_enable_device(struct pci_dev
*dev
, int mask
)
736 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
739 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
740 struct resource
*res
= &dev
->resource
[i
];
742 /* Only set up the requested stuff */
743 if (!(mask
& (1<<i
)))
746 if (res
->flags
& IORESOURCE_IO
)
747 cmd
|= PCI_COMMAND_IO
;
748 if (res
->flags
& IORESOURCE_MEM
)
749 cmd
|= PCI_COMMAND_MEMORY
;
753 printk(KERN_DEBUG
"PCI: Enabling device: (%s), cmd %x\n",
755 /* Enable the appropriate bits in the PCI command register. */
756 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
761 void pcibios_resource_to_bus(struct pci_dev
*pdev
, struct pci_bus_region
*region
,
762 struct resource
*res
)
764 struct pci_pbm_info
*pbm
= pdev
->bus
->sysdata
;
765 struct resource zero_res
, *root
;
769 zero_res
.flags
= res
->flags
;
771 if (res
->flags
& IORESOURCE_IO
)
772 root
= &pbm
->io_space
;
774 root
= &pbm
->mem_space
;
776 pci_resource_adjust(&zero_res
, root
);
778 region
->start
= res
->start
- zero_res
.start
;
779 region
->end
= res
->end
- zero_res
.start
;
781 EXPORT_SYMBOL(pcibios_resource_to_bus
);
783 void pcibios_bus_to_resource(struct pci_dev
*pdev
, struct resource
*res
,
784 struct pci_bus_region
*region
)
786 struct pci_pbm_info
*pbm
= pdev
->bus
->sysdata
;
787 struct resource
*root
;
789 res
->start
= region
->start
;
790 res
->end
= region
->end
;
792 if (res
->flags
& IORESOURCE_IO
)
793 root
= &pbm
->io_space
;
795 root
= &pbm
->mem_space
;
797 pci_resource_adjust(res
, root
);
799 EXPORT_SYMBOL(pcibios_bus_to_resource
);
801 char * __devinit
pcibios_setup(char *str
)
806 /* Platform support for /proc/bus/pci/X/Y mmap()s. */
808 /* If the user uses a host-bridge as the PCI device, he may use
809 * this to perform a raw mmap() of the I/O or MEM space behind
812 * This can be useful for execution of x86 PCI bios initialization code
813 * on a PCI card, like the xfree86 int10 stuff does.
815 static int __pci_mmap_make_offset_bus(struct pci_dev
*pdev
, struct vm_area_struct
*vma
,
816 enum pci_mmap_state mmap_state
)
818 struct pci_pbm_info
*pbm
= pdev
->dev
.archdata
.host_controller
;
819 unsigned long space_size
, user_offset
, user_size
;
821 if (mmap_state
== pci_mmap_io
) {
822 space_size
= (pbm
->io_space
.end
-
823 pbm
->io_space
.start
) + 1;
825 space_size
= (pbm
->mem_space
.end
-
826 pbm
->mem_space
.start
) + 1;
829 /* Make sure the request is in range. */
830 user_offset
= vma
->vm_pgoff
<< PAGE_SHIFT
;
831 user_size
= vma
->vm_end
- vma
->vm_start
;
833 if (user_offset
>= space_size
||
834 (user_offset
+ user_size
) > space_size
)
837 if (mmap_state
== pci_mmap_io
) {
838 vma
->vm_pgoff
= (pbm
->io_space
.start
+
839 user_offset
) >> PAGE_SHIFT
;
841 vma
->vm_pgoff
= (pbm
->mem_space
.start
+
842 user_offset
) >> PAGE_SHIFT
;
848 /* Adjust vm_pgoff of VMA such that it is the physical page offset
849 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
851 * Basically, the user finds the base address for his device which he wishes
852 * to mmap. They read the 32-bit value from the config space base register,
853 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
854 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
856 * Returns negative error code on failure, zero on success.
858 static int __pci_mmap_make_offset(struct pci_dev
*pdev
,
859 struct vm_area_struct
*vma
,
860 enum pci_mmap_state mmap_state
)
862 unsigned long user_paddr
, user_size
;
865 /* First compute the physical address in vma->vm_pgoff,
866 * making sure the user offset is within range in the
867 * appropriate PCI space.
869 err
= __pci_mmap_make_offset_bus(pdev
, vma
, mmap_state
);
873 /* If this is a mapping on a host bridge, any address
876 if ((pdev
->class >> 8) == PCI_CLASS_BRIDGE_HOST
)
879 /* Otherwise make sure it's in the range for one of the
880 * device's resources.
882 user_paddr
= vma
->vm_pgoff
<< PAGE_SHIFT
;
883 user_size
= vma
->vm_end
- vma
->vm_start
;
885 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
886 struct resource
*rp
= &pdev
->resource
[i
];
887 resource_size_t aligned_end
;
894 if (i
== PCI_ROM_RESOURCE
) {
895 if (mmap_state
!= pci_mmap_mem
)
898 if ((mmap_state
== pci_mmap_io
&&
899 (rp
->flags
& IORESOURCE_IO
) == 0) ||
900 (mmap_state
== pci_mmap_mem
&&
901 (rp
->flags
& IORESOURCE_MEM
) == 0))
905 /* Align the resource end to the next page address.
906 * PAGE_SIZE intentionally added instead of (PAGE_SIZE - 1),
907 * because actually we need the address of the next byte
910 aligned_end
= (rp
->end
+ PAGE_SIZE
) & PAGE_MASK
;
912 if ((rp
->start
<= user_paddr
) &&
913 (user_paddr
+ user_size
) <= aligned_end
)
917 if (i
> PCI_ROM_RESOURCE
)
923 /* Set vm_flags of VMA, as appropriate for this architecture, for a pci device
926 static void __pci_mmap_set_flags(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
927 enum pci_mmap_state mmap_state
)
929 vma
->vm_flags
|= (VM_IO
| VM_RESERVED
);
932 /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
935 static void __pci_mmap_set_pgprot(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
936 enum pci_mmap_state mmap_state
)
938 /* Our io_remap_pfn_range takes care of this, do nothing. */
941 /* Perform the actual remap of the pages for a PCI device mapping, as appropriate
942 * for this architecture. The region in the process to map is described by vm_start
943 * and vm_end members of VMA, the base physical address is found in vm_pgoff.
944 * The pci device structure is provided so that architectures may make mapping
945 * decisions on a per-device or per-bus basis.
947 * Returns a negative error code on failure, zero on success.
949 int pci_mmap_page_range(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
950 enum pci_mmap_state mmap_state
,
955 ret
= __pci_mmap_make_offset(dev
, vma
, mmap_state
);
959 __pci_mmap_set_flags(dev
, vma
, mmap_state
);
960 __pci_mmap_set_pgprot(dev
, vma
, mmap_state
);
962 vma
->vm_page_prot
= pgprot_noncached(vma
->vm_page_prot
);
963 ret
= io_remap_pfn_range(vma
, vma
->vm_start
,
965 vma
->vm_end
- vma
->vm_start
,
974 int pcibus_to_node(struct pci_bus
*pbus
)
976 struct pci_pbm_info
*pbm
= pbus
->sysdata
;
978 return pbm
->numa_node
;
980 EXPORT_SYMBOL(pcibus_to_node
);
983 /* Return the domain number for this pci bus */
985 int pci_domain_nr(struct pci_bus
*pbus
)
987 struct pci_pbm_info
*pbm
= pbus
->sysdata
;
998 EXPORT_SYMBOL(pci_domain_nr
);
1000 #ifdef CONFIG_PCI_MSI
1001 int arch_setup_msi_irq(struct pci_dev
*pdev
, struct msi_desc
*desc
)
1003 struct pci_pbm_info
*pbm
= pdev
->dev
.archdata
.host_controller
;
1004 unsigned int virt_irq
;
1006 if (!pbm
->setup_msi_irq
)
1009 return pbm
->setup_msi_irq(&virt_irq
, pdev
, desc
);
1012 void arch_teardown_msi_irq(unsigned int virt_irq
)
1014 struct msi_desc
*entry
= get_irq_msi(virt_irq
);
1015 struct pci_dev
*pdev
= entry
->dev
;
1016 struct pci_pbm_info
*pbm
= pdev
->dev
.archdata
.host_controller
;
1018 if (pbm
->teardown_msi_irq
)
1019 pbm
->teardown_msi_irq(virt_irq
, pdev
);
1021 #endif /* !(CONFIG_PCI_MSI) */
1023 struct device_node
*pci_device_to_OF_node(struct pci_dev
*pdev
)
1025 return pdev
->dev
.archdata
.prom_node
;
1027 EXPORT_SYMBOL(pci_device_to_OF_node
);
1029 static void ali_sound_dma_hack(struct pci_dev
*pdev
, int set_bit
)
1031 struct pci_dev
*ali_isa_bridge
;
1034 /* ALI sound chips generate 31-bits of DMA, a special register
1035 * determines what bit 31 is emitted as.
1037 ali_isa_bridge
= pci_get_device(PCI_VENDOR_ID_AL
,
1038 PCI_DEVICE_ID_AL_M1533
,
1041 pci_read_config_byte(ali_isa_bridge
, 0x7e, &val
);
1046 pci_write_config_byte(ali_isa_bridge
, 0x7e, val
);
1047 pci_dev_put(ali_isa_bridge
);
1050 int pci64_dma_supported(struct pci_dev
*pdev
, u64 device_mask
)
1055 dma_addr_mask
= 0xffffffff;
1057 struct iommu
*iommu
= pdev
->dev
.archdata
.iommu
;
1059 dma_addr_mask
= iommu
->dma_addr_mask
;
1061 if (pdev
->vendor
== PCI_VENDOR_ID_AL
&&
1062 pdev
->device
== PCI_DEVICE_ID_AL_M5451
&&
1063 device_mask
== 0x7fffffff) {
1064 ali_sound_dma_hack(pdev
,
1065 (dma_addr_mask
& 0x80000000) != 0);
1070 if (device_mask
>= (1UL << 32UL))
1073 return (device_mask
& dma_addr_mask
) == dma_addr_mask
;
1076 void pci_resource_to_user(const struct pci_dev
*pdev
, int bar
,
1077 const struct resource
*rp
, resource_size_t
*start
,
1078 resource_size_t
*end
)
1080 struct pci_pbm_info
*pbm
= pdev
->dev
.archdata
.host_controller
;
1081 unsigned long offset
;
1083 if (rp
->flags
& IORESOURCE_IO
)
1084 offset
= pbm
->io_space
.start
;
1086 offset
= pbm
->mem_space
.start
;
1088 *start
= rp
->start
- offset
;
1089 *end
= rp
->end
- offset
;
1092 static int __init
pcibios_init(void)
1094 pci_dfl_cache_line_size
= 64 >> 2;
1097 subsys_initcall(pcibios_init
);
1100 static void __devinit
pci_bus_slot_names(struct device_node
*node
,
1101 struct pci_bus
*bus
)
1103 const struct pci_slot_names
{
1111 prop
= of_get_property(node
, "slot-names", &len
);
1115 mask
= prop
->slot_mask
;
1119 printk("PCI: Making slots for [%s] mask[0x%02x]\n",
1120 node
->full_name
, mask
);
1124 struct pci_slot
*pci_slot
;
1125 u32 this_bit
= 1 << i
;
1127 if (!(mask
& this_bit
)) {
1133 printk("PCI: Making slot [%s]\n", sp
);
1135 pci_slot
= pci_create_slot(bus
, i
, sp
, NULL
);
1136 if (IS_ERR(pci_slot
))
1137 printk(KERN_ERR
"PCI: pci_create_slot returned %ld\n",
1140 sp
+= strlen(sp
) + 1;
1146 static int __init
of_pci_slot_init(void)
1148 struct pci_bus
*pbus
= NULL
;
1150 while ((pbus
= pci_find_next_bus(pbus
)) != NULL
) {
1151 struct device_node
*node
;
1154 struct dev_archdata
*sd
= pbus
->self
->sysdata
;
1156 /* PCI->PCI bridge */
1157 node
= sd
->prom_node
;
1159 struct pci_pbm_info
*pbm
= pbus
->sysdata
;
1161 /* Host PCI controller */
1162 node
= pbm
->op
->node
;
1165 pci_bus_slot_names(node
, pbus
);
1171 module_init(of_pci_slot_init
);