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MIPS: SB1250: Include correct header and fix a warning
[linux-2.6/linux-mips.git] / arch / x86 / kernel / amd_iommu.c
blobf854d89b7edf6cdc933043732497020e4cdb48a2
1 /*
2 * Copyright (C) 2007-2009 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/pci.h>
21 #include <linux/bitmap.h>
22 #include <linux/slab.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/iommu-helper.h>
27 #include <linux/iommu.h>
28 #include <asm/proto.h>
29 #include <asm/iommu.h>
30 #include <asm/gart.h>
31 #include <asm/amd_iommu_proto.h>
32 #include <asm/amd_iommu_types.h>
33 #include <asm/amd_iommu.h>
34
35 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
36
37 #define EXIT_LOOP_COUNT 10000000
38
39 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
40
41 /* A list of preallocated protection domains */
42 static LIST_HEAD(iommu_pd_list);
43 static DEFINE_SPINLOCK(iommu_pd_list_lock);
44
45 /*
46 * Domain for untranslated devices - only allocated
47 * if iommu=pt passed on kernel cmd line.
48 */
49 static struct protection_domain *pt_domain;
50
51 static struct iommu_ops amd_iommu_ops;
52
53 /*
54 * general struct to manage commands send to an IOMMU
55 */
56 struct iommu_cmd {
57 u32 data[4];
58 };
59
60 static void reset_iommu_command_buffer(struct amd_iommu *iommu);
61 static void update_domain(struct protection_domain *domain);
62
63 /****************************************************************************
64 *
65 * Helper functions
66 *
67 ****************************************************************************/
68
69 static inline u16 get_device_id(struct device *dev)
70 {
71 struct pci_dev *pdev = to_pci_dev(dev);
72
73 return calc_devid(pdev->bus->number, pdev->devfn);
74 }
75
76 static struct iommu_dev_data *get_dev_data(struct device *dev)
77 {
78 return dev->archdata.iommu;
79 }
80
81 /*
82 * In this function the list of preallocated protection domains is traversed to
83 * find the domain for a specific device
84 */
85 static struct dma_ops_domain *find_protection_domain(u16 devid)
86 {
87 struct dma_ops_domain *entry, *ret = NULL;
88 unsigned long flags;
89 u16 alias = amd_iommu_alias_table[devid];
90
91 if (list_empty(&iommu_pd_list))
92 return NULL;
93
94 spin_lock_irqsave(&iommu_pd_list_lock, flags);
95
96 list_for_each_entry(entry, &iommu_pd_list, list) {
97 if (entry->target_dev == devid ||
98 entry->target_dev == alias) {
99 ret = entry;
100 break;
101 }
102 }
103
104 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
105
106 return ret;
107 }
108
109 /*
110 * This function checks if the driver got a valid device from the caller to
111 * avoid dereferencing invalid pointers.
112 */
113 static bool check_device(struct device *dev)
114 {
115 u16 devid;
116
117 if (!dev || !dev->dma_mask)
118 return false;
119
120 /* No device or no PCI device */
121 if (dev->bus != &pci_bus_type)
122 return false;
123
124 devid = get_device_id(dev);
125
126 /* Out of our scope? */
127 if (devid > amd_iommu_last_bdf)
128 return false;
129
130 if (amd_iommu_rlookup_table[devid] == NULL)
131 return false;
132
133 return true;
134 }
135
136 static int iommu_init_device(struct device *dev)
137 {
138 struct iommu_dev_data *dev_data;
139 struct pci_dev *pdev;
140 u16 devid, alias;
141
142 if (dev->archdata.iommu)
143 return 0;
144
145 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
146 if (!dev_data)
147 return -ENOMEM;
148
149 dev_data->dev = dev;
150
151 devid = get_device_id(dev);
152 alias = amd_iommu_alias_table[devid];
153 pdev = pci_get_bus_and_slot(PCI_BUS(alias), alias & 0xff);
154 if (pdev)
155 dev_data->alias = &pdev->dev;
156
157 atomic_set(&dev_data->bind, 0);
158
159 dev->archdata.iommu = dev_data;
160
161
162 return 0;
163 }
164
165 static void iommu_uninit_device(struct device *dev)
166 {
167 kfree(dev->archdata.iommu);
168 }
169
170 void __init amd_iommu_uninit_devices(void)
171 {
172 struct pci_dev *pdev = NULL;
173
174 for_each_pci_dev(pdev) {
175
176 if (!check_device(&pdev->dev))
177 continue;
178
179 iommu_uninit_device(&pdev->dev);
180 }
181 }
182
183 int __init amd_iommu_init_devices(void)
184 {
185 struct pci_dev *pdev = NULL;
186 int ret = 0;
187
188 for_each_pci_dev(pdev) {
189
190 if (!check_device(&pdev->dev))
191 continue;
192
193 ret = iommu_init_device(&pdev->dev);
194 if (ret)
195 goto out_free;
196 }
197
198 return 0;
199
200 out_free:
201
202 amd_iommu_uninit_devices();
203
204 return ret;
205 }
206 #ifdef CONFIG_AMD_IOMMU_STATS
207
208 /*
209 * Initialization code for statistics collection
210 */
211
212 DECLARE_STATS_COUNTER(compl_wait);
213 DECLARE_STATS_COUNTER(cnt_map_single);
214 DECLARE_STATS_COUNTER(cnt_unmap_single);
215 DECLARE_STATS_COUNTER(cnt_map_sg);
216 DECLARE_STATS_COUNTER(cnt_unmap_sg);
217 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
218 DECLARE_STATS_COUNTER(cnt_free_coherent);
219 DECLARE_STATS_COUNTER(cross_page);
220 DECLARE_STATS_COUNTER(domain_flush_single);
221 DECLARE_STATS_COUNTER(domain_flush_all);
222 DECLARE_STATS_COUNTER(alloced_io_mem);
223 DECLARE_STATS_COUNTER(total_map_requests);
224
225 static struct dentry *stats_dir;
226 static struct dentry *de_fflush;
227
228 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
229 {
230 if (stats_dir == NULL)
231 return;
232
233 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
234 &cnt->value);
235 }
236
237 static void amd_iommu_stats_init(void)
238 {
239 stats_dir = debugfs_create_dir("amd-iommu", NULL);
240 if (stats_dir == NULL)
241 return;
242
243 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
244 (u32 *)&amd_iommu_unmap_flush);
245
246 amd_iommu_stats_add(&compl_wait);
247 amd_iommu_stats_add(&cnt_map_single);
248 amd_iommu_stats_add(&cnt_unmap_single);
249 amd_iommu_stats_add(&cnt_map_sg);
250 amd_iommu_stats_add(&cnt_unmap_sg);
251 amd_iommu_stats_add(&cnt_alloc_coherent);
252 amd_iommu_stats_add(&cnt_free_coherent);
253 amd_iommu_stats_add(&cross_page);
254 amd_iommu_stats_add(&domain_flush_single);
255 amd_iommu_stats_add(&domain_flush_all);
256 amd_iommu_stats_add(&alloced_io_mem);
257 amd_iommu_stats_add(&total_map_requests);
258 }
259
260 #endif
261
262 /****************************************************************************
263 *
264 * Interrupt handling functions
265 *
266 ****************************************************************************/
267
268 static void dump_dte_entry(u16 devid)
269 {
270 int i;
271
272 for (i = 0; i < 8; ++i)
273 pr_err("AMD-Vi: DTE[%d]: %08x\n", i,
274 amd_iommu_dev_table[devid].data[i]);
275 }
276
277 static void dump_command(unsigned long phys_addr)
278 {
279 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
280 int i;
281
282 for (i = 0; i < 4; ++i)
283 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
284 }
285
286 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
287 {
288 u32 *event = __evt;
289 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
290 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
291 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
292 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
293 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
294
295 printk(KERN_ERR "AMD-Vi: Event logged [");
296
297 switch (type) {
298 case EVENT_TYPE_ILL_DEV:
299 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
300 "address=0x%016llx flags=0x%04x]\n",
301 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
302 address, flags);
303 dump_dte_entry(devid);
304 break;
305 case EVENT_TYPE_IO_FAULT:
306 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
307 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
308 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
309 domid, address, flags);
310 break;
311 case EVENT_TYPE_DEV_TAB_ERR:
312 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
313 "address=0x%016llx flags=0x%04x]\n",
314 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
315 address, flags);
316 break;
317 case EVENT_TYPE_PAGE_TAB_ERR:
318 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
319 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
320 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
321 domid, address, flags);
322 break;
323 case EVENT_TYPE_ILL_CMD:
324 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
325 iommu->reset_in_progress = true;
326 reset_iommu_command_buffer(iommu);
327 dump_command(address);
328 break;
329 case EVENT_TYPE_CMD_HARD_ERR:
330 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
331 "flags=0x%04x]\n", address, flags);
332 break;
333 case EVENT_TYPE_IOTLB_INV_TO:
334 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
335 "address=0x%016llx]\n",
336 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
337 address);
338 break;
339 case EVENT_TYPE_INV_DEV_REQ:
340 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
341 "address=0x%016llx flags=0x%04x]\n",
342 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
343 address, flags);
344 break;
345 default:
346 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
347 }
348 }
349
350 static void iommu_poll_events(struct amd_iommu *iommu)
351 {
352 u32 head, tail;
353 unsigned long flags;
354
355 spin_lock_irqsave(&iommu->lock, flags);
356
357 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
358 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
359
360 while (head != tail) {
361 iommu_print_event(iommu, iommu->evt_buf + head);
362 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
363 }
364
365 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
366
367 spin_unlock_irqrestore(&iommu->lock, flags);
368 }
369
370 irqreturn_t amd_iommu_int_handler(int irq, void *data)
371 {
372 struct amd_iommu *iommu;
373
374 for_each_iommu(iommu)
375 iommu_poll_events(iommu);
376
377 return IRQ_HANDLED;
378 }
379
380 /****************************************************************************
381 *
382 * IOMMU command queuing functions
383 *
384 ****************************************************************************/
385
386 /*
387 * Writes the command to the IOMMUs command buffer and informs the
388 * hardware about the new command. Must be called with iommu->lock held.
389 */
390 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
391 {
392 u32 tail, head;
393 u8 *target;
394
395 WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED);
396 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
397 target = iommu->cmd_buf + tail;
398 memcpy_toio(target, cmd, sizeof(*cmd));
399 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
400 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
401 if (tail == head)
402 return -ENOMEM;
403 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
404
405 return 0;
406 }
407
408 /*
409 * General queuing function for commands. Takes iommu->lock and calls
410 * __iommu_queue_command().
411 */
412 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
413 {
414 unsigned long flags;
415 int ret;
416
417 spin_lock_irqsave(&iommu->lock, flags);
418 ret = __iommu_queue_command(iommu, cmd);
419 if (!ret)
420 iommu->need_sync = true;
421 spin_unlock_irqrestore(&iommu->lock, flags);
422
423 return ret;
424 }
425
426 /*
427 * This function waits until an IOMMU has completed a completion
428 * wait command
429 */
430 static void __iommu_wait_for_completion(struct amd_iommu *iommu)
431 {
432 int ready = 0;
433 unsigned status = 0;
434 unsigned long i = 0;
435
436 INC_STATS_COUNTER(compl_wait);
437
438 while (!ready && (i < EXIT_LOOP_COUNT)) {
439 ++i;
440 /* wait for the bit to become one */
441 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
442 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
443 }
444
445 /* set bit back to zero */
446 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
447 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
448
449 if (unlikely(i == EXIT_LOOP_COUNT))
450 iommu->reset_in_progress = true;
451 }
452
453 /*
454 * This function queues a completion wait command into the command
455 * buffer of an IOMMU
456 */
457 static int __iommu_completion_wait(struct amd_iommu *iommu)
458 {
459 struct iommu_cmd cmd;
460
461 memset(&cmd, 0, sizeof(cmd));
462 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
463 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
464
465 return __iommu_queue_command(iommu, &cmd);
466 }
467
468 /*
469 * This function is called whenever we need to ensure that the IOMMU has
470 * completed execution of all commands we sent. It sends a
471 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
472 * us about that by writing a value to a physical address we pass with
473 * the command.
474 */
475 static int iommu_completion_wait(struct amd_iommu *iommu)
476 {
477 int ret = 0;
478 unsigned long flags;
479
480 spin_lock_irqsave(&iommu->lock, flags);
481
482 if (!iommu->need_sync)
483 goto out;
484
485 ret = __iommu_completion_wait(iommu);
486
487 iommu->need_sync = false;
488
489 if (ret)
490 goto out;
491
492 __iommu_wait_for_completion(iommu);
493
494 out:
495 spin_unlock_irqrestore(&iommu->lock, flags);
496
497 if (iommu->reset_in_progress)
498 reset_iommu_command_buffer(iommu);
499
500 return 0;
501 }
502
503 static void iommu_flush_complete(struct protection_domain *domain)
504 {
505 int i;
506
507 for (i = 0; i < amd_iommus_present; ++i) {
508 if (!domain->dev_iommu[i])
509 continue;
510
511 /*
512 * Devices of this domain are behind this IOMMU
513 * We need to wait for completion of all commands.
514 */
515 iommu_completion_wait(amd_iommus[i]);
516 }
517 }
518
519 /*
520 * Command send function for invalidating a device table entry
521 */
522 static int iommu_flush_device(struct device *dev)
523 {
524 struct amd_iommu *iommu;
525 struct iommu_cmd cmd;
526 u16 devid;
527
528 devid = get_device_id(dev);
529 iommu = amd_iommu_rlookup_table[devid];
530
531 /* Build command */
532 memset(&cmd, 0, sizeof(cmd));
533 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
534 cmd.data[0] = devid;
535
536 return iommu_queue_command(iommu, &cmd);
537 }
538
539 static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
540 u16 domid, int pde, int s)
541 {
542 memset(cmd, 0, sizeof(*cmd));
543 address &= PAGE_MASK;
544 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
545 cmd->data[1] |= domid;
546 cmd->data[2] = lower_32_bits(address);
547 cmd->data[3] = upper_32_bits(address);
548 if (s) /* size bit - we flush more than one 4kb page */
549 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
550 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
551 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
552 }
553
554 /*
555 * Generic command send function for invalidaing TLB entries
556 */
557 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
558 u64 address, u16 domid, int pde, int s)
559 {
560 struct iommu_cmd cmd;
561 int ret;
562
563 __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s);
564
565 ret = iommu_queue_command(iommu, &cmd);
566
567 return ret;
568 }
569
570 /*
571 * TLB invalidation function which is called from the mapping functions.
572 * It invalidates a single PTE if the range to flush is within a single
573 * page. Otherwise it flushes the whole TLB of the IOMMU.
574 */
575 static void __iommu_flush_pages(struct protection_domain *domain,
576 u64 address, size_t size, int pde)
577 {
578 int s = 0, i;
579 unsigned long pages = iommu_num_pages(address, size, PAGE_SIZE);
580
581 address &= PAGE_MASK;
582
583 if (pages > 1) {
584 /*
585 * If we have to flush more than one page, flush all
586 * TLB entries for this domain
587 */
588 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
589 s = 1;
590 }
591
592
593 for (i = 0; i < amd_iommus_present; ++i) {
594 if (!domain->dev_iommu[i])
595 continue;
596
597 /*
598 * Devices of this domain are behind this IOMMU
599 * We need a TLB flush
600 */
601 iommu_queue_inv_iommu_pages(amd_iommus[i], address,
602 domain->id, pde, s);
603 }
604
605 return;
606 }
607
608 static void iommu_flush_pages(struct protection_domain *domain,
609 u64 address, size_t size)
610 {
611 __iommu_flush_pages(domain, address, size, 0);
612 }
613
614 /* Flush the whole IO/TLB for a given protection domain */
615 static void iommu_flush_tlb(struct protection_domain *domain)
616 {
617 __iommu_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
618 }
619
620 /* Flush the whole IO/TLB for a given protection domain - including PDE */
621 static void iommu_flush_tlb_pde(struct protection_domain *domain)
622 {
623 __iommu_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
624 }
625
626
627 /*
628 * This function flushes the DTEs for all devices in domain
629 */
630 static void iommu_flush_domain_devices(struct protection_domain *domain)
631 {
632 struct iommu_dev_data *dev_data;
633 unsigned long flags;
634
635 spin_lock_irqsave(&domain->lock, flags);
636
637 list_for_each_entry(dev_data, &domain->dev_list, list)
638 iommu_flush_device(dev_data->dev);
639
640 spin_unlock_irqrestore(&domain->lock, flags);
641 }
642
643 static void iommu_flush_all_domain_devices(void)
644 {
645 struct protection_domain *domain;
646 unsigned long flags;
647
648 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
649
650 list_for_each_entry(domain, &amd_iommu_pd_list, list) {
651 iommu_flush_domain_devices(domain);
652 iommu_flush_complete(domain);
653 }
654
655 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
656 }
657
658 void amd_iommu_flush_all_devices(void)
659 {
660 iommu_flush_all_domain_devices();
661 }
662
663 /*
664 * This function uses heavy locking and may disable irqs for some time. But
665 * this is no issue because it is only called during resume.
666 */
667 void amd_iommu_flush_all_domains(void)
668 {
669 struct protection_domain *domain;
670 unsigned long flags;
671
672 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
673
674 list_for_each_entry(domain, &amd_iommu_pd_list, list) {
675 spin_lock(&domain->lock);
676 iommu_flush_tlb_pde(domain);
677 iommu_flush_complete(domain);
678 spin_unlock(&domain->lock);
679 }
680
681 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
682 }
683
684 static void reset_iommu_command_buffer(struct amd_iommu *iommu)
685 {
686 pr_err("AMD-Vi: Resetting IOMMU command buffer\n");
687
688 if (iommu->reset_in_progress)
689 panic("AMD-Vi: ILLEGAL_COMMAND_ERROR while resetting command buffer\n");
690
691 amd_iommu_reset_cmd_buffer(iommu);
692 amd_iommu_flush_all_devices();
693 amd_iommu_flush_all_domains();
694
695 iommu->reset_in_progress = false;
696 }
697
698 /****************************************************************************
699 *
700 * The functions below are used the create the page table mappings for
701 * unity mapped regions.
702 *
703 ****************************************************************************/
704
705 /*
706 * This function is used to add another level to an IO page table. Adding
707 * another level increases the size of the address space by 9 bits to a size up
708 * to 64 bits.
709 */
710 static bool increase_address_space(struct protection_domain *domain,
711 gfp_t gfp)
712 {
713 u64 *pte;
714
715 if (domain->mode == PAGE_MODE_6_LEVEL)
716 /* address space already 64 bit large */
717 return false;
718
719 pte = (void *)get_zeroed_page(gfp);
720 if (!pte)
721 return false;
722
723 *pte = PM_LEVEL_PDE(domain->mode,
724 virt_to_phys(domain->pt_root));
725 domain->pt_root = pte;
726 domain->mode += 1;
727 domain->updated = true;
728
729 return true;
730 }
731
732 static u64 *alloc_pte(struct protection_domain *domain,
733 unsigned long address,
734 int end_lvl,
735 u64 **pte_page,
736 gfp_t gfp)
737 {
738 u64 *pte, *page;
739 int level;
740
741 while (address > PM_LEVEL_SIZE(domain->mode))
742 increase_address_space(domain, gfp);
743
744 level = domain->mode - 1;
745 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
746
747 while (level > end_lvl) {
748 if (!IOMMU_PTE_PRESENT(*pte)) {
749 page = (u64 *)get_zeroed_page(gfp);
750 if (!page)
751 return NULL;
752 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
753 }
754
755 level -= 1;
756
757 pte = IOMMU_PTE_PAGE(*pte);
758
759 if (pte_page && level == end_lvl)
760 *pte_page = pte;
761
762 pte = &pte[PM_LEVEL_INDEX(level, address)];
763 }
764
765 return pte;
766 }
767
768 /*
769 * This function checks if there is a PTE for a given dma address. If
770 * there is one, it returns the pointer to it.
771 */
772 static u64 *fetch_pte(struct protection_domain *domain,
773 unsigned long address, int map_size)
774 {
775 int level;
776 u64 *pte;
777
778 level = domain->mode - 1;
779 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
780
781 while (level > map_size) {
782 if (!IOMMU_PTE_PRESENT(*pte))
783 return NULL;
784
785 level -= 1;
786
787 pte = IOMMU_PTE_PAGE(*pte);
788 pte = &pte[PM_LEVEL_INDEX(level, address)];
789
790 if ((PM_PTE_LEVEL(*pte) == 0) && level != map_size) {
791 pte = NULL;
792 break;
793 }
794 }
795
796 return pte;
797 }
798
799 /*
800 * Generic mapping functions. It maps a physical address into a DMA
801 * address space. It allocates the page table pages if necessary.
802 * In the future it can be extended to a generic mapping function
803 * supporting all features of AMD IOMMU page tables like level skipping
804 * and full 64 bit address spaces.
805 */
806 static int iommu_map_page(struct protection_domain *dom,
807 unsigned long bus_addr,
808 unsigned long phys_addr,
809 int prot,
810 int map_size)
811 {
812 u64 __pte, *pte;
813
814 bus_addr = PAGE_ALIGN(bus_addr);
815 phys_addr = PAGE_ALIGN(phys_addr);
816
817 BUG_ON(!PM_ALIGNED(map_size, bus_addr));
818 BUG_ON(!PM_ALIGNED(map_size, phys_addr));
819
820 if (!(prot & IOMMU_PROT_MASK))
821 return -EINVAL;
822
823 pte = alloc_pte(dom, bus_addr, map_size, NULL, GFP_KERNEL);
824
825 if (IOMMU_PTE_PRESENT(*pte))
826 return -EBUSY;
827
828 __pte = phys_addr | IOMMU_PTE_P;
829 if (prot & IOMMU_PROT_IR)
830 __pte |= IOMMU_PTE_IR;
831 if (prot & IOMMU_PROT_IW)
832 __pte |= IOMMU_PTE_IW;
833
834 *pte = __pte;
835
836 update_domain(dom);
837
838 return 0;
839 }
840
841 static void iommu_unmap_page(struct protection_domain *dom,
842 unsigned long bus_addr, int map_size)
843 {
844 u64 *pte = fetch_pte(dom, bus_addr, map_size);
845
846 if (pte)
847 *pte = 0;
848 }
849
850 /*
851 * This function checks if a specific unity mapping entry is needed for
852 * this specific IOMMU.
853 */
854 static int iommu_for_unity_map(struct amd_iommu *iommu,
855 struct unity_map_entry *entry)
856 {
857 u16 bdf, i;
858
859 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
860 bdf = amd_iommu_alias_table[i];
861 if (amd_iommu_rlookup_table[bdf] == iommu)
862 return 1;
863 }
864
865 return 0;
866 }
867
868 /*
869 * This function actually applies the mapping to the page table of the
870 * dma_ops domain.
871 */
872 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
873 struct unity_map_entry *e)
874 {
875 u64 addr;
876 int ret;
877
878 for (addr = e->address_start; addr < e->address_end;
879 addr += PAGE_SIZE) {
880 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
881 PM_MAP_4k);
882 if (ret)
883 return ret;
884 /*
885 * if unity mapping is in aperture range mark the page
886 * as allocated in the aperture
887 */
888 if (addr < dma_dom->aperture_size)
889 __set_bit(addr >> PAGE_SHIFT,
890 dma_dom->aperture[0]->bitmap);
891 }
892
893 return 0;
894 }
895
896 /*
897 * Init the unity mappings for a specific IOMMU in the system
898 *
899 * Basically iterates over all unity mapping entries and applies them to
900 * the default domain DMA of that IOMMU if necessary.
901 */
902 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
903 {
904 struct unity_map_entry *entry;
905 int ret;
906
907 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
908 if (!iommu_for_unity_map(iommu, entry))
909 continue;
910 ret = dma_ops_unity_map(iommu->default_dom, entry);
911 if (ret)
912 return ret;
913 }
914
915 return 0;
916 }
917
918 /*
919 * Inits the unity mappings required for a specific device
920 */
921 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
922 u16 devid)
923 {
924 struct unity_map_entry *e;
925 int ret;
926
927 list_for_each_entry(e, &amd_iommu_unity_map, list) {
928 if (!(devid >= e->devid_start && devid <= e->devid_end))
929 continue;
930 ret = dma_ops_unity_map(dma_dom, e);
931 if (ret)
932 return ret;
933 }
934
935 return 0;
936 }
937
938 /****************************************************************************
939 *
940 * The next functions belong to the address allocator for the dma_ops
941 * interface functions. They work like the allocators in the other IOMMU
942 * drivers. Its basically a bitmap which marks the allocated pages in
943 * the aperture. Maybe it could be enhanced in the future to a more
944 * efficient allocator.
945 *
946 ****************************************************************************/
947
948 /*
949 * The address allocator core functions.
950 *
951 * called with domain->lock held
952 */
953
954 /*
955 * Used to reserve address ranges in the aperture (e.g. for exclusion
956 * ranges.
957 */
958 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
959 unsigned long start_page,
960 unsigned int pages)
961 {
962 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
963
964 if (start_page + pages > last_page)
965 pages = last_page - start_page;
966
967 for (i = start_page; i < start_page + pages; ++i) {
968 int index = i / APERTURE_RANGE_PAGES;
969 int page = i % APERTURE_RANGE_PAGES;
970 __set_bit(page, dom->aperture[index]->bitmap);
971 }
972 }
973
974 /*
975 * This function is used to add a new aperture range to an existing
976 * aperture in case of dma_ops domain allocation or address allocation
977 * failure.
978 */
979 static int alloc_new_range(struct dma_ops_domain *dma_dom,
980 bool populate, gfp_t gfp)
981 {
982 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
983 struct amd_iommu *iommu;
984 unsigned long i;
985
986 #ifdef CONFIG_IOMMU_STRESS
987 populate = false;
988 #endif
989
990 if (index >= APERTURE_MAX_RANGES)
991 return -ENOMEM;
992
993 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
994 if (!dma_dom->aperture[index])
995 return -ENOMEM;
996
997 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
998 if (!dma_dom->aperture[index]->bitmap)
999 goto out_free;
1000
1001 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
1002
1003 if (populate) {
1004 unsigned long address = dma_dom->aperture_size;
1005 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
1006 u64 *pte, *pte_page;
1007
1008 for (i = 0; i < num_ptes; ++i) {
1009 pte = alloc_pte(&dma_dom->domain, address, PM_MAP_4k,
1010 &pte_page, gfp);
1011 if (!pte)
1012 goto out_free;
1013
1014 dma_dom->aperture[index]->pte_pages[i] = pte_page;
1015
1016 address += APERTURE_RANGE_SIZE / 64;
1017 }
1018 }
1019
1020 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
1021
1022 /* Intialize the exclusion range if necessary */
1023 for_each_iommu(iommu) {
1024 if (iommu->exclusion_start &&
1025 iommu->exclusion_start >= dma_dom->aperture[index]->offset
1026 && iommu->exclusion_start < dma_dom->aperture_size) {
1027 unsigned long startpage;
1028 int pages = iommu_num_pages(iommu->exclusion_start,
1029 iommu->exclusion_length,
1030 PAGE_SIZE);
1031 startpage = iommu->exclusion_start >> PAGE_SHIFT;
1032 dma_ops_reserve_addresses(dma_dom, startpage, pages);
1033 }
1034 }
1035
1036 /*
1037 * Check for areas already mapped as present in the new aperture
1038 * range and mark those pages as reserved in the allocator. Such
1039 * mappings may already exist as a result of requested unity
1040 * mappings for devices.
1041 */
1042 for (i = dma_dom->aperture[index]->offset;
1043 i < dma_dom->aperture_size;
1044 i += PAGE_SIZE) {
1045 u64 *pte = fetch_pte(&dma_dom->domain, i, PM_MAP_4k);
1046 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1047 continue;
1048
1049 dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1);
1050 }
1051
1052 update_domain(&dma_dom->domain);
1053
1054 return 0;
1055
1056 out_free:
1057 update_domain(&dma_dom->domain);
1058
1059 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
1060
1061 kfree(dma_dom->aperture[index]);
1062 dma_dom->aperture[index] = NULL;
1063
1064 return -ENOMEM;
1065 }
1066
1067 static unsigned long dma_ops_area_alloc(struct device *dev,
1068 struct dma_ops_domain *dom,
1069 unsigned int pages,
1070 unsigned long align_mask,
1071 u64 dma_mask,
1072 unsigned long start)
1073 {
1074 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
1075 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
1076 int i = start >> APERTURE_RANGE_SHIFT;
1077 unsigned long boundary_size;
1078 unsigned long address = -1;
1079 unsigned long limit;
1080
1081 next_bit >>= PAGE_SHIFT;
1082
1083 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
1084 PAGE_SIZE) >> PAGE_SHIFT;
1085
1086 for (;i < max_index; ++i) {
1087 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
1088
1089 if (dom->aperture[i]->offset >= dma_mask)
1090 break;
1091
1092 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1093 dma_mask >> PAGE_SHIFT);
1094
1095 address = iommu_area_alloc(dom->aperture[i]->bitmap,
1096 limit, next_bit, pages, 0,
1097 boundary_size, align_mask);
1098 if (address != -1) {
1099 address = dom->aperture[i]->offset +
1100 (address << PAGE_SHIFT);
1101 dom->next_address = address + (pages << PAGE_SHIFT);
1102 break;
1103 }
1104
1105 next_bit = 0;
1106 }
1107
1108 return address;
1109 }
1110
1111 static unsigned long dma_ops_alloc_addresses(struct device *dev,
1112 struct dma_ops_domain *dom,
1113 unsigned int pages,
1114 unsigned long align_mask,
1115 u64 dma_mask)
1116 {
1117 unsigned long address;
1118
1119 #ifdef CONFIG_IOMMU_STRESS
1120 dom->next_address = 0;
1121 dom->need_flush = true;
1122 #endif
1123
1124 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1125 dma_mask, dom->next_address);
1126
1127 if (address == -1) {
1128 dom->next_address = 0;
1129 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1130 dma_mask, 0);
1131 dom->need_flush = true;
1132 }
1133
1134 if (unlikely(address == -1))
1135 address = DMA_ERROR_CODE;
1136
1137 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1138
1139 return address;
1140 }
1141
1142 /*
1143 * The address free function.
1144 *
1145 * called with domain->lock held
1146 */
1147 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1148 unsigned long address,
1149 unsigned int pages)
1150 {
1151 unsigned i = address >> APERTURE_RANGE_SHIFT;
1152 struct aperture_range *range = dom->aperture[i];
1153
1154 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1155
1156 #ifdef CONFIG_IOMMU_STRESS
1157 if (i < 4)
1158 return;
1159 #endif
1160
1161 if (address >= dom->next_address)
1162 dom->need_flush = true;
1163
1164 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
1165
1166 bitmap_clear(range->bitmap, address, pages);
1167
1168 }
1169
1170 /****************************************************************************
1171 *
1172 * The next functions belong to the domain allocation. A domain is
1173 * allocated for every IOMMU as the default domain. If device isolation
1174 * is enabled, every device get its own domain. The most important thing
1175 * about domains is the page table mapping the DMA address space they
1176 * contain.
1177 *
1178 ****************************************************************************/
1179
1180 /*
1181 * This function adds a protection domain to the global protection domain list
1182 */
1183 static void add_domain_to_list(struct protection_domain *domain)
1184 {
1185 unsigned long flags;
1186
1187 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1188 list_add(&domain->list, &amd_iommu_pd_list);
1189 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1190 }
1191
1192 /*
1193 * This function removes a protection domain to the global
1194 * protection domain list
1195 */
1196 static void del_domain_from_list(struct protection_domain *domain)
1197 {
1198 unsigned long flags;
1199
1200 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1201 list_del(&domain->list);
1202 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1203 }
1204
1205 static u16 domain_id_alloc(void)
1206 {
1207 unsigned long flags;
1208 int id;
1209
1210 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1211 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1212 BUG_ON(id == 0);
1213 if (id > 0 && id < MAX_DOMAIN_ID)
1214 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1215 else
1216 id = 0;
1217 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1218
1219 return id;
1220 }
1221
1222 static void domain_id_free(int id)
1223 {
1224 unsigned long flags;
1225
1226 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1227 if (id > 0 && id < MAX_DOMAIN_ID)
1228 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1229 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1230 }
1231
1232 static void free_pagetable(struct protection_domain *domain)
1233 {
1234 int i, j;
1235 u64 *p1, *p2, *p3;
1236
1237 p1 = domain->pt_root;
1238
1239 if (!p1)
1240 return;
1241
1242 for (i = 0; i < 512; ++i) {
1243 if (!IOMMU_PTE_PRESENT(p1[i]))
1244 continue;
1245
1246 p2 = IOMMU_PTE_PAGE(p1[i]);
1247 for (j = 0; j < 512; ++j) {
1248 if (!IOMMU_PTE_PRESENT(p2[j]))
1249 continue;
1250 p3 = IOMMU_PTE_PAGE(p2[j]);
1251 free_page((unsigned long)p3);
1252 }
1253
1254 free_page((unsigned long)p2);
1255 }
1256
1257 free_page((unsigned long)p1);
1258
1259 domain->pt_root = NULL;
1260 }
1261
1262 /*
1263 * Free a domain, only used if something went wrong in the
1264 * allocation path and we need to free an already allocated page table
1265 */
1266 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1267 {
1268 int i;
1269
1270 if (!dom)
1271 return;
1272
1273 del_domain_from_list(&dom->domain);
1274
1275 free_pagetable(&dom->domain);
1276
1277 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1278 if (!dom->aperture[i])
1279 continue;
1280 free_page((unsigned long)dom->aperture[i]->bitmap);
1281 kfree(dom->aperture[i]);
1282 }
1283
1284 kfree(dom);
1285 }
1286
1287 /*
1288 * Allocates a new protection domain usable for the dma_ops functions.
1289 * It also intializes the page table and the address allocator data
1290 * structures required for the dma_ops interface
1291 */
1292 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1293 {
1294 struct dma_ops_domain *dma_dom;
1295
1296 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1297 if (!dma_dom)
1298 return NULL;
1299
1300 spin_lock_init(&dma_dom->domain.lock);
1301
1302 dma_dom->domain.id = domain_id_alloc();
1303 if (dma_dom->domain.id == 0)
1304 goto free_dma_dom;
1305 INIT_LIST_HEAD(&dma_dom->domain.dev_list);
1306 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
1307 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1308 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1309 dma_dom->domain.priv = dma_dom;
1310 if (!dma_dom->domain.pt_root)
1311 goto free_dma_dom;
1312
1313 dma_dom->need_flush = false;
1314 dma_dom->target_dev = 0xffff;
1315
1316 add_domain_to_list(&dma_dom->domain);
1317
1318 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
1319 goto free_dma_dom;
1320
1321 /*
1322 * mark the first page as allocated so we never return 0 as
1323 * a valid dma-address. So we can use 0 as error value
1324 */
1325 dma_dom->aperture[0]->bitmap[0] = 1;
1326 dma_dom->next_address = 0;
1327
1328
1329 return dma_dom;
1330
1331 free_dma_dom:
1332 dma_ops_domain_free(dma_dom);
1333
1334 return NULL;
1335 }
1336
1337 /*
1338 * little helper function to check whether a given protection domain is a
1339 * dma_ops domain
1340 */
1341 static bool dma_ops_domain(struct protection_domain *domain)
1342 {
1343 return domain->flags & PD_DMA_OPS_MASK;
1344 }
1345
1346 static void set_dte_entry(u16 devid, struct protection_domain *domain)
1347 {
1348 u64 pte_root = virt_to_phys(domain->pt_root);
1349
1350 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1351 << DEV_ENTRY_MODE_SHIFT;
1352 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1353
1354 amd_iommu_dev_table[devid].data[2] = domain->id;
1355 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
1356 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
1357 }
1358
1359 static void clear_dte_entry(u16 devid)
1360 {
1361 /* remove entry from the device table seen by the hardware */
1362 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1363 amd_iommu_dev_table[devid].data[1] = 0;
1364 amd_iommu_dev_table[devid].data[2] = 0;
1365
1366 amd_iommu_apply_erratum_63(devid);
1367 }
1368
1369 static void do_attach(struct device *dev, struct protection_domain *domain)
1370 {
1371 struct iommu_dev_data *dev_data;
1372 struct amd_iommu *iommu;
1373 u16 devid;
1374
1375 devid = get_device_id(dev);
1376 iommu = amd_iommu_rlookup_table[devid];
1377 dev_data = get_dev_data(dev);
1378
1379 /* Update data structures */
1380 dev_data->domain = domain;
1381 list_add(&dev_data->list, &domain->dev_list);
1382 set_dte_entry(devid, domain);
1383
1384 /* Do reference counting */
1385 domain->dev_iommu[iommu->index] += 1;
1386 domain->dev_cnt += 1;
1387
1388 /* Flush the DTE entry */
1389 iommu_flush_device(dev);
1390 }
1391
1392 static void do_detach(struct device *dev)
1393 {
1394 struct iommu_dev_data *dev_data;
1395 struct amd_iommu *iommu;
1396 u16 devid;
1397
1398 devid = get_device_id(dev);
1399 iommu = amd_iommu_rlookup_table[devid];
1400 dev_data = get_dev_data(dev);
1401
1402 /* decrease reference counters */
1403 dev_data->domain->dev_iommu[iommu->index] -= 1;
1404 dev_data->domain->dev_cnt -= 1;
1405
1406 /* Update data structures */
1407 dev_data->domain = NULL;
1408 list_del(&dev_data->list);
1409 clear_dte_entry(devid);
1410
1411 /* Flush the DTE entry */
1412 iommu_flush_device(dev);
1413 }
1414
1415 /*
1416 * If a device is not yet associated with a domain, this function does
1417 * assigns it visible for the hardware
1418 */
1419 static int __attach_device(struct device *dev,
1420 struct protection_domain *domain)
1421 {
1422 struct iommu_dev_data *dev_data, *alias_data;
1423
1424 dev_data = get_dev_data(dev);
1425 alias_data = get_dev_data(dev_data->alias);
1426
1427 if (!alias_data)
1428 return -EINVAL;
1429
1430 /* lock domain */
1431 spin_lock(&domain->lock);
1432
1433 /* Some sanity checks */
1434 if (alias_data->domain != NULL &&
1435 alias_data->domain != domain)
1436 return -EBUSY;
1437
1438 if (dev_data->domain != NULL &&
1439 dev_data->domain != domain)
1440 return -EBUSY;
1441
1442 /* Do real assignment */
1443 if (dev_data->alias != dev) {
1444 alias_data = get_dev_data(dev_data->alias);
1445 if (alias_data->domain == NULL)
1446 do_attach(dev_data->alias, domain);
1447
1448 atomic_inc(&alias_data->bind);
1449 }
1450
1451 if (dev_data->domain == NULL)
1452 do_attach(dev, domain);
1453
1454 atomic_inc(&dev_data->bind);
1455
1456 /* ready */
1457 spin_unlock(&domain->lock);
1458
1459 return 0;
1460 }
1461
1462 /*
1463 * If a device is not yet associated with a domain, this function does
1464 * assigns it visible for the hardware
1465 */
1466 static int attach_device(struct device *dev,
1467 struct protection_domain *domain)
1468 {
1469 unsigned long flags;
1470 int ret;
1471
1472 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1473 ret = __attach_device(dev, domain);
1474 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1475
1476 /*
1477 * We might boot into a crash-kernel here. The crashed kernel
1478 * left the caches in the IOMMU dirty. So we have to flush
1479 * here to evict all dirty stuff.
1480 */
1481 iommu_flush_tlb_pde(domain);
1482
1483 return ret;
1484 }
1485
1486 /*
1487 * Removes a device from a protection domain (unlocked)
1488 */
1489 static void __detach_device(struct device *dev)
1490 {
1491 struct iommu_dev_data *dev_data = get_dev_data(dev);
1492 struct iommu_dev_data *alias_data;
1493 struct protection_domain *domain;
1494 unsigned long flags;
1495
1496 BUG_ON(!dev_data->domain);
1497
1498 domain = dev_data->domain;
1499
1500 spin_lock_irqsave(&domain->lock, flags);
1501
1502 if (dev_data->alias != dev) {
1503 alias_data = get_dev_data(dev_data->alias);
1504 if (atomic_dec_and_test(&alias_data->bind))
1505 do_detach(dev_data->alias);
1506 }
1507
1508 if (atomic_dec_and_test(&dev_data->bind))
1509 do_detach(dev);
1510
1511 spin_unlock_irqrestore(&domain->lock, flags);
1512
1513 /*
1514 * If we run in passthrough mode the device must be assigned to the
1515 * passthrough domain if it is detached from any other domain.
1516 * Make sure we can deassign from the pt_domain itself.
1517 */
1518 if (iommu_pass_through &&
1519 (dev_data->domain == NULL && domain != pt_domain))
1520 __attach_device(dev, pt_domain);
1521 }
1522
1523 /*
1524 * Removes a device from a protection domain (with devtable_lock held)
1525 */
1526 static void detach_device(struct device *dev)
1527 {
1528 unsigned long flags;
1529
1530 /* lock device table */
1531 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1532 __detach_device(dev);
1533 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1534 }
1535
1536 /*
1537 * Find out the protection domain structure for a given PCI device. This
1538 * will give us the pointer to the page table root for example.
1539 */
1540 static struct protection_domain *domain_for_device(struct device *dev)
1541 {
1542 struct protection_domain *dom;
1543 struct iommu_dev_data *dev_data, *alias_data;
1544 unsigned long flags;
1545 u16 devid, alias;
1546
1547 devid = get_device_id(dev);
1548 alias = amd_iommu_alias_table[devid];
1549 dev_data = get_dev_data(dev);
1550 alias_data = get_dev_data(dev_data->alias);
1551 if (!alias_data)
1552 return NULL;
1553
1554 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
1555 dom = dev_data->domain;
1556 if (dom == NULL &&
1557 alias_data->domain != NULL) {
1558 __attach_device(dev, alias_data->domain);
1559 dom = alias_data->domain;
1560 }
1561
1562 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1563
1564 return dom;
1565 }
1566
1567 static int device_change_notifier(struct notifier_block *nb,
1568 unsigned long action, void *data)
1569 {
1570 struct device *dev = data;
1571 u16 devid;
1572 struct protection_domain *domain;
1573 struct dma_ops_domain *dma_domain;
1574 struct amd_iommu *iommu;
1575 unsigned long flags;
1576
1577 if (!check_device(dev))
1578 return 0;
1579
1580 devid = get_device_id(dev);
1581 iommu = amd_iommu_rlookup_table[devid];
1582
1583 switch (action) {
1584 case BUS_NOTIFY_UNBOUND_DRIVER:
1585
1586 domain = domain_for_device(dev);
1587
1588 if (!domain)
1589 goto out;
1590 if (iommu_pass_through)
1591 break;
1592 detach_device(dev);
1593 break;
1594 case BUS_NOTIFY_ADD_DEVICE:
1595
1596 iommu_init_device(dev);
1597
1598 domain = domain_for_device(dev);
1599
1600 /* allocate a protection domain if a device is added */
1601 dma_domain = find_protection_domain(devid);
1602 if (dma_domain)
1603 goto out;
1604 dma_domain = dma_ops_domain_alloc();
1605 if (!dma_domain)
1606 goto out;
1607 dma_domain->target_dev = devid;
1608
1609 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1610 list_add_tail(&dma_domain->list, &iommu_pd_list);
1611 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1612
1613 break;
1614 case BUS_NOTIFY_DEL_DEVICE:
1615
1616 iommu_uninit_device(dev);
1617
1618 default:
1619 goto out;
1620 }
1621
1622 iommu_flush_device(dev);
1623 iommu_completion_wait(iommu);
1624
1625 out:
1626 return 0;
1627 }
1628
1629 static struct notifier_block device_nb = {
1630 .notifier_call = device_change_notifier,
1631 };
1632
1633 void amd_iommu_init_notifier(void)
1634 {
1635 bus_register_notifier(&pci_bus_type, &device_nb);
1636 }
1637
1638 /*****************************************************************************
1639 *
1640 * The next functions belong to the dma_ops mapping/unmapping code.
1641 *
1642 *****************************************************************************/
1643
1644 /*
1645 * In the dma_ops path we only have the struct device. This function
1646 * finds the corresponding IOMMU, the protection domain and the
1647 * requestor id for a given device.
1648 * If the device is not yet associated with a domain this is also done
1649 * in this function.
1650 */
1651 static struct protection_domain *get_domain(struct device *dev)
1652 {
1653 struct protection_domain *domain;
1654 struct dma_ops_domain *dma_dom;
1655 u16 devid = get_device_id(dev);
1656
1657 if (!check_device(dev))
1658 return ERR_PTR(-EINVAL);
1659
1660 domain = domain_for_device(dev);
1661 if (domain != NULL && !dma_ops_domain(domain))
1662 return ERR_PTR(-EBUSY);
1663
1664 if (domain != NULL)
1665 return domain;
1666
1667 /* Device not bount yet - bind it */
1668 dma_dom = find_protection_domain(devid);
1669 if (!dma_dom)
1670 dma_dom = amd_iommu_rlookup_table[devid]->default_dom;
1671 attach_device(dev, &dma_dom->domain);
1672 DUMP_printk("Using protection domain %d for device %s\n",
1673 dma_dom->domain.id, dev_name(dev));
1674
1675 return &dma_dom->domain;
1676 }
1677
1678 static void update_device_table(struct protection_domain *domain)
1679 {
1680 struct iommu_dev_data *dev_data;
1681
1682 list_for_each_entry(dev_data, &domain->dev_list, list) {
1683 u16 devid = get_device_id(dev_data->dev);
1684 set_dte_entry(devid, domain);
1685 }
1686 }
1687
1688 static void update_domain(struct protection_domain *domain)
1689 {
1690 if (!domain->updated)
1691 return;
1692
1693 update_device_table(domain);
1694 iommu_flush_domain_devices(domain);
1695 iommu_flush_tlb_pde(domain);
1696
1697 domain->updated = false;
1698 }
1699
1700 /*
1701 * This function fetches the PTE for a given address in the aperture
1702 */
1703 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
1704 unsigned long address)
1705 {
1706 struct aperture_range *aperture;
1707 u64 *pte, *pte_page;
1708
1709 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1710 if (!aperture)
1711 return NULL;
1712
1713 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1714 if (!pte) {
1715 pte = alloc_pte(&dom->domain, address, PM_MAP_4k, &pte_page,
1716 GFP_ATOMIC);
1717 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
1718 } else
1719 pte += PM_LEVEL_INDEX(0, address);
1720
1721 update_domain(&dom->domain);
1722
1723 return pte;
1724 }
1725
1726 /*
1727 * This is the generic map function. It maps one 4kb page at paddr to
1728 * the given address in the DMA address space for the domain.
1729 */
1730 static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
1731 unsigned long address,
1732 phys_addr_t paddr,
1733 int direction)
1734 {
1735 u64 *pte, __pte;
1736
1737 WARN_ON(address > dom->aperture_size);
1738
1739 paddr &= PAGE_MASK;
1740
1741 pte = dma_ops_get_pte(dom, address);
1742 if (!pte)
1743 return DMA_ERROR_CODE;
1744
1745 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1746
1747 if (direction == DMA_TO_DEVICE)
1748 __pte |= IOMMU_PTE_IR;
1749 else if (direction == DMA_FROM_DEVICE)
1750 __pte |= IOMMU_PTE_IW;
1751 else if (direction == DMA_BIDIRECTIONAL)
1752 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1753
1754 WARN_ON(*pte);
1755
1756 *pte = __pte;
1757
1758 return (dma_addr_t)address;
1759 }
1760
1761 /*
1762 * The generic unmapping function for on page in the DMA address space.
1763 */
1764 static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
1765 unsigned long address)
1766 {
1767 struct aperture_range *aperture;
1768 u64 *pte;
1769
1770 if (address >= dom->aperture_size)
1771 return;
1772
1773 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1774 if (!aperture)
1775 return;
1776
1777 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1778 if (!pte)
1779 return;
1780
1781 pte += PM_LEVEL_INDEX(0, address);
1782
1783 WARN_ON(!*pte);
1784
1785 *pte = 0ULL;
1786 }
1787
1788 /*
1789 * This function contains common code for mapping of a physically
1790 * contiguous memory region into DMA address space. It is used by all
1791 * mapping functions provided with this IOMMU driver.
1792 * Must be called with the domain lock held.
1793 */
1794 static dma_addr_t __map_single(struct device *dev,
1795 struct dma_ops_domain *dma_dom,
1796 phys_addr_t paddr,
1797 size_t size,
1798 int dir,
1799 bool align,
1800 u64 dma_mask)
1801 {
1802 dma_addr_t offset = paddr & ~PAGE_MASK;
1803 dma_addr_t address, start, ret;
1804 unsigned int pages;
1805 unsigned long align_mask = 0;
1806 int i;
1807
1808 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1809 paddr &= PAGE_MASK;
1810
1811 INC_STATS_COUNTER(total_map_requests);
1812
1813 if (pages > 1)
1814 INC_STATS_COUNTER(cross_page);
1815
1816 if (align)
1817 align_mask = (1UL << get_order(size)) - 1;
1818
1819 retry:
1820 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1821 dma_mask);
1822 if (unlikely(address == DMA_ERROR_CODE)) {
1823 /*
1824 * setting next_address here will let the address
1825 * allocator only scan the new allocated range in the
1826 * first run. This is a small optimization.
1827 */
1828 dma_dom->next_address = dma_dom->aperture_size;
1829
1830 if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
1831 goto out;
1832
1833 /*
1834 * aperture was successfully enlarged by 128 MB, try
1835 * allocation again
1836 */
1837 goto retry;
1838 }
1839
1840 start = address;
1841 for (i = 0; i < pages; ++i) {
1842 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
1843 if (ret == DMA_ERROR_CODE)
1844 goto out_unmap;
1845
1846 paddr += PAGE_SIZE;
1847 start += PAGE_SIZE;
1848 }
1849 address += offset;
1850
1851 ADD_STATS_COUNTER(alloced_io_mem, size);
1852
1853 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
1854 iommu_flush_tlb(&dma_dom->domain);
1855 dma_dom->need_flush = false;
1856 } else if (unlikely(amd_iommu_np_cache))
1857 iommu_flush_pages(&dma_dom->domain, address, size);
1858
1859 out:
1860 return address;
1861
1862 out_unmap:
1863
1864 for (--i; i >= 0; --i) {
1865 start -= PAGE_SIZE;
1866 dma_ops_domain_unmap(dma_dom, start);
1867 }
1868
1869 dma_ops_free_addresses(dma_dom, address, pages);
1870
1871 return DMA_ERROR_CODE;
1872 }
1873
1874 /*
1875 * Does the reverse of the __map_single function. Must be called with
1876 * the domain lock held too
1877 */
1878 static void __unmap_single(struct dma_ops_domain *dma_dom,
1879 dma_addr_t dma_addr,
1880 size_t size,
1881 int dir)
1882 {
1883 dma_addr_t i, start;
1884 unsigned int pages;
1885
1886 if ((dma_addr == DMA_ERROR_CODE) ||
1887 (dma_addr + size > dma_dom->aperture_size))
1888 return;
1889
1890 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
1891 dma_addr &= PAGE_MASK;
1892 start = dma_addr;
1893
1894 for (i = 0; i < pages; ++i) {
1895 dma_ops_domain_unmap(dma_dom, start);
1896 start += PAGE_SIZE;
1897 }
1898
1899 SUB_STATS_COUNTER(alloced_io_mem, size);
1900
1901 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1902
1903 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1904 iommu_flush_pages(&dma_dom->domain, dma_addr, size);
1905 dma_dom->need_flush = false;
1906 }
1907 }
1908
1909 /*
1910 * The exported map_single function for dma_ops.
1911 */
1912 static dma_addr_t map_page(struct device *dev, struct page *page,
1913 unsigned long offset, size_t size,
1914 enum dma_data_direction dir,
1915 struct dma_attrs *attrs)
1916 {
1917 unsigned long flags;
1918 struct protection_domain *domain;
1919 dma_addr_t addr;
1920 u64 dma_mask;
1921 phys_addr_t paddr = page_to_phys(page) + offset;
1922
1923 INC_STATS_COUNTER(cnt_map_single);
1924
1925 domain = get_domain(dev);
1926 if (PTR_ERR(domain) == -EINVAL)
1927 return (dma_addr_t)paddr;
1928 else if (IS_ERR(domain))
1929 return DMA_ERROR_CODE;
1930
1931 dma_mask = *dev->dma_mask;
1932
1933 spin_lock_irqsave(&domain->lock, flags);
1934
1935 addr = __map_single(dev, domain->priv, paddr, size, dir, false,
1936 dma_mask);
1937 if (addr == DMA_ERROR_CODE)
1938 goto out;
1939
1940 iommu_flush_complete(domain);
1941
1942 out:
1943 spin_unlock_irqrestore(&domain->lock, flags);
1944
1945 return addr;
1946 }
1947
1948 /*
1949 * The exported unmap_single function for dma_ops.
1950 */
1951 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
1952 enum dma_data_direction dir, struct dma_attrs *attrs)
1953 {
1954 unsigned long flags;
1955 struct protection_domain *domain;
1956
1957 INC_STATS_COUNTER(cnt_unmap_single);
1958
1959 domain = get_domain(dev);
1960 if (IS_ERR(domain))
1961 return;
1962
1963 spin_lock_irqsave(&domain->lock, flags);
1964
1965 __unmap_single(domain->priv, dma_addr, size, dir);
1966
1967 iommu_flush_complete(domain);
1968
1969 spin_unlock_irqrestore(&domain->lock, flags);
1970 }
1971
1972 /*
1973 * This is a special map_sg function which is used if we should map a
1974 * device which is not handled by an AMD IOMMU in the system.
1975 */
1976 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1977 int nelems, int dir)
1978 {
1979 struct scatterlist *s;
1980 int i;
1981
1982 for_each_sg(sglist, s, nelems, i) {
1983 s->dma_address = (dma_addr_t)sg_phys(s);
1984 s->dma_length = s->length;
1985 }
1986
1987 return nelems;
1988 }
1989
1990 /*
1991 * The exported map_sg function for dma_ops (handles scatter-gather
1992 * lists).
1993 */
1994 static int map_sg(struct device *dev, struct scatterlist *sglist,
1995 int nelems, enum dma_data_direction dir,
1996 struct dma_attrs *attrs)
1997 {
1998 unsigned long flags;
1999 struct protection_domain *domain;
2000 int i;
2001 struct scatterlist *s;
2002 phys_addr_t paddr;
2003 int mapped_elems = 0;
2004 u64 dma_mask;
2005
2006 INC_STATS_COUNTER(cnt_map_sg);
2007
2008 domain = get_domain(dev);
2009 if (PTR_ERR(domain) == -EINVAL)
2010 return map_sg_no_iommu(dev, sglist, nelems, dir);
2011 else if (IS_ERR(domain))
2012 return 0;
2013
2014 dma_mask = *dev->dma_mask;
2015
2016 spin_lock_irqsave(&domain->lock, flags);
2017
2018 for_each_sg(sglist, s, nelems, i) {
2019 paddr = sg_phys(s);
2020
2021 s->dma_address = __map_single(dev, domain->priv,
2022 paddr, s->length, dir, false,
2023 dma_mask);
2024
2025 if (s->dma_address) {
2026 s->dma_length = s->length;
2027 mapped_elems++;
2028 } else
2029 goto unmap;
2030 }
2031
2032 iommu_flush_complete(domain);
2033
2034 out:
2035 spin_unlock_irqrestore(&domain->lock, flags);
2036
2037 return mapped_elems;
2038 unmap:
2039 for_each_sg(sglist, s, mapped_elems, i) {
2040 if (s->dma_address)
2041 __unmap_single(domain->priv, s->dma_address,
2042 s->dma_length, dir);
2043 s->dma_address = s->dma_length = 0;
2044 }
2045
2046 mapped_elems = 0;
2047
2048 goto out;
2049 }
2050
2051 /*
2052 * The exported map_sg function for dma_ops (handles scatter-gather
2053 * lists).
2054 */
2055 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2056 int nelems, enum dma_data_direction dir,
2057 struct dma_attrs *attrs)
2058 {
2059 unsigned long flags;
2060 struct protection_domain *domain;
2061 struct scatterlist *s;
2062 int i;
2063
2064 INC_STATS_COUNTER(cnt_unmap_sg);
2065
2066 domain = get_domain(dev);
2067 if (IS_ERR(domain))
2068 return;
2069
2070 spin_lock_irqsave(&domain->lock, flags);
2071
2072 for_each_sg(sglist, s, nelems, i) {
2073 __unmap_single(domain->priv, s->dma_address,
2074 s->dma_length, dir);
2075 s->dma_address = s->dma_length = 0;
2076 }
2077
2078 iommu_flush_complete(domain);
2079
2080 spin_unlock_irqrestore(&domain->lock, flags);
2081 }
2082
2083 /*
2084 * The exported alloc_coherent function for dma_ops.
2085 */
2086 static void *alloc_coherent(struct device *dev, size_t size,
2087 dma_addr_t *dma_addr, gfp_t flag)
2088 {
2089 unsigned long flags;
2090 void *virt_addr;
2091 struct protection_domain *domain;
2092 phys_addr_t paddr;
2093 u64 dma_mask = dev->coherent_dma_mask;
2094
2095 INC_STATS_COUNTER(cnt_alloc_coherent);
2096
2097 domain = get_domain(dev);
2098 if (PTR_ERR(domain) == -EINVAL) {
2099 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2100 *dma_addr = __pa(virt_addr);
2101 return virt_addr;
2102 } else if (IS_ERR(domain))
2103 return NULL;
2104
2105 dma_mask = dev->coherent_dma_mask;
2106 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2107 flag |= __GFP_ZERO;
2108
2109 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2110 if (!virt_addr)
2111 return NULL;
2112
2113 paddr = virt_to_phys(virt_addr);
2114
2115 if (!dma_mask)
2116 dma_mask = *dev->dma_mask;
2117
2118 spin_lock_irqsave(&domain->lock, flags);
2119
2120 *dma_addr = __map_single(dev, domain->priv, paddr,
2121 size, DMA_BIDIRECTIONAL, true, dma_mask);
2122
2123 if (*dma_addr == DMA_ERROR_CODE) {
2124 spin_unlock_irqrestore(&domain->lock, flags);
2125 goto out_free;
2126 }
2127
2128 iommu_flush_complete(domain);
2129
2130 spin_unlock_irqrestore(&domain->lock, flags);
2131
2132 return virt_addr;
2133
2134 out_free:
2135
2136 free_pages((unsigned long)virt_addr, get_order(size));
2137
2138 return NULL;
2139 }
2140
2141 /*
2142 * The exported free_coherent function for dma_ops.
2143 */
2144 static void free_coherent(struct device *dev, size_t size,
2145 void *virt_addr, dma_addr_t dma_addr)
2146 {
2147 unsigned long flags;
2148 struct protection_domain *domain;
2149
2150 INC_STATS_COUNTER(cnt_free_coherent);
2151
2152 domain = get_domain(dev);
2153 if (IS_ERR(domain))
2154 goto free_mem;
2155
2156 spin_lock_irqsave(&domain->lock, flags);
2157
2158 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
2159
2160 iommu_flush_complete(domain);
2161
2162 spin_unlock_irqrestore(&domain->lock, flags);
2163
2164 free_mem:
2165 free_pages((unsigned long)virt_addr, get_order(size));
2166 }
2167
2168 /*
2169 * This function is called by the DMA layer to find out if we can handle a
2170 * particular device. It is part of the dma_ops.
2171 */
2172 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2173 {
2174 return check_device(dev);
2175 }
2176
2177 /*
2178 * The function for pre-allocating protection domains.
2179 *
2180 * If the driver core informs the DMA layer if a driver grabs a device
2181 * we don't need to preallocate the protection domains anymore.
2182 * For now we have to.
2183 */
2184 static void prealloc_protection_domains(void)
2185 {
2186 struct pci_dev *dev = NULL;
2187 struct dma_ops_domain *dma_dom;
2188 u16 devid;
2189
2190 for_each_pci_dev(dev) {
2191
2192 /* Do we handle this device? */
2193 if (!check_device(&dev->dev))
2194 continue;
2195
2196 /* Is there already any domain for it? */
2197 if (domain_for_device(&dev->dev))
2198 continue;
2199
2200 devid = get_device_id(&dev->dev);
2201
2202 dma_dom = dma_ops_domain_alloc();
2203 if (!dma_dom)
2204 continue;
2205 init_unity_mappings_for_device(dma_dom, devid);
2206 dma_dom->target_dev = devid;
2207
2208 attach_device(&dev->dev, &dma_dom->domain);
2209
2210 list_add_tail(&dma_dom->list, &iommu_pd_list);
2211 }
2212 }
2213
2214 static struct dma_map_ops amd_iommu_dma_ops = {
2215 .alloc_coherent = alloc_coherent,
2216 .free_coherent = free_coherent,
2217 .map_page = map_page,
2218 .unmap_page = unmap_page,
2219 .map_sg = map_sg,
2220 .unmap_sg = unmap_sg,
2221 .dma_supported = amd_iommu_dma_supported,
2222 };
2223
2224 /*
2225 * The function which clues the AMD IOMMU driver into dma_ops.
2226 */
2227
2228 void __init amd_iommu_init_api(void)
2229 {
2230 register_iommu(&amd_iommu_ops);
2231 }
2232
2233 int __init amd_iommu_init_dma_ops(void)
2234 {
2235 struct amd_iommu *iommu;
2236 int ret;
2237
2238 /*
2239 * first allocate a default protection domain for every IOMMU we
2240 * found in the system. Devices not assigned to any other
2241 * protection domain will be assigned to the default one.
2242 */
2243 for_each_iommu(iommu) {
2244 iommu->default_dom = dma_ops_domain_alloc();
2245 if (iommu->default_dom == NULL)
2246 return -ENOMEM;
2247 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
2248 ret = iommu_init_unity_mappings(iommu);
2249 if (ret)
2250 goto free_domains;
2251 }
2252
2253 /*
2254 * Pre-allocate the protection domains for each device.
2255 */
2256 prealloc_protection_domains();
2257
2258 iommu_detected = 1;
2259 swiotlb = 0;
2260 #ifdef CONFIG_GART_IOMMU
2261 gart_iommu_aperture_disabled = 1;
2262 gart_iommu_aperture = 0;
2263 #endif
2264
2265 /* Make the driver finally visible to the drivers */
2266 dma_ops = &amd_iommu_dma_ops;
2267
2268 amd_iommu_stats_init();
2269
2270 return 0;
2271
2272 free_domains:
2273
2274 for_each_iommu(iommu) {
2275 if (iommu->default_dom)
2276 dma_ops_domain_free(iommu->default_dom);
2277 }
2278
2279 return ret;
2280 }
2281
2282 /*****************************************************************************
2283 *
2284 * The following functions belong to the exported interface of AMD IOMMU
2285 *
2286 * This interface allows access to lower level functions of the IOMMU
2287 * like protection domain handling and assignement of devices to domains
2288 * which is not possible with the dma_ops interface.
2289 *
2290 *****************************************************************************/
2291
2292 static void cleanup_domain(struct protection_domain *domain)
2293 {
2294 struct iommu_dev_data *dev_data, *next;
2295 unsigned long flags;
2296
2297 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2298
2299 list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) {
2300 struct device *dev = dev_data->dev;
2301
2302 __detach_device(dev);
2303 atomic_set(&dev_data->bind, 0);
2304 }
2305
2306 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2307 }
2308
2309 static void protection_domain_free(struct protection_domain *domain)
2310 {
2311 if (!domain)
2312 return;
2313
2314 del_domain_from_list(domain);
2315
2316 if (domain->id)
2317 domain_id_free(domain->id);
2318
2319 kfree(domain);
2320 }
2321
2322 static struct protection_domain *protection_domain_alloc(void)
2323 {
2324 struct protection_domain *domain;
2325
2326 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2327 if (!domain)
2328 return NULL;
2329
2330 spin_lock_init(&domain->lock);
2331 mutex_init(&domain->api_lock);
2332 domain->id = domain_id_alloc();
2333 if (!domain->id)
2334 goto out_err;
2335 INIT_LIST_HEAD(&domain->dev_list);
2336
2337 add_domain_to_list(domain);
2338
2339 return domain;
2340
2341 out_err:
2342 kfree(domain);
2343
2344 return NULL;
2345 }
2346
2347 static int amd_iommu_domain_init(struct iommu_domain *dom)
2348 {
2349 struct protection_domain *domain;
2350
2351 domain = protection_domain_alloc();
2352 if (!domain)
2353 goto out_free;
2354
2355 domain->mode = PAGE_MODE_3_LEVEL;
2356 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2357 if (!domain->pt_root)
2358 goto out_free;
2359
2360 dom->priv = domain;
2361
2362 return 0;
2363
2364 out_free:
2365 protection_domain_free(domain);
2366
2367 return -ENOMEM;
2368 }
2369
2370 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
2371 {
2372 struct protection_domain *domain = dom->priv;
2373
2374 if (!domain)
2375 return;
2376
2377 if (domain->dev_cnt > 0)
2378 cleanup_domain(domain);
2379
2380 BUG_ON(domain->dev_cnt != 0);
2381
2382 free_pagetable(domain);
2383
2384 protection_domain_free(domain);
2385
2386 dom->priv = NULL;
2387 }
2388
2389 static void amd_iommu_detach_device(struct iommu_domain *dom,
2390 struct device *dev)
2391 {
2392 struct iommu_dev_data *dev_data = dev->archdata.iommu;
2393 struct amd_iommu *iommu;
2394 u16 devid;
2395
2396 if (!check_device(dev))
2397 return;
2398
2399 devid = get_device_id(dev);
2400
2401 if (dev_data->domain != NULL)
2402 detach_device(dev);
2403
2404 iommu = amd_iommu_rlookup_table[devid];
2405 if (!iommu)
2406 return;
2407
2408 iommu_flush_device(dev);
2409 iommu_completion_wait(iommu);
2410 }
2411
2412 static int amd_iommu_attach_device(struct iommu_domain *dom,
2413 struct device *dev)
2414 {
2415 struct protection_domain *domain = dom->priv;
2416 struct iommu_dev_data *dev_data;
2417 struct amd_iommu *iommu;
2418 int ret;
2419 u16 devid;
2420
2421 if (!check_device(dev))
2422 return -EINVAL;
2423
2424 dev_data = dev->archdata.iommu;
2425
2426 devid = get_device_id(dev);
2427
2428 iommu = amd_iommu_rlookup_table[devid];
2429 if (!iommu)
2430 return -EINVAL;
2431
2432 if (dev_data->domain)
2433 detach_device(dev);
2434
2435 ret = attach_device(dev, domain);
2436
2437 iommu_completion_wait(iommu);
2438
2439 return ret;
2440 }
2441
2442 static int amd_iommu_map_range(struct iommu_domain *dom,
2443 unsigned long iova, phys_addr_t paddr,
2444 size_t size, int iommu_prot)
2445 {
2446 struct protection_domain *domain = dom->priv;
2447 unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE);
2448 int prot = 0;
2449 int ret;
2450
2451 if (iommu_prot & IOMMU_READ)
2452 prot |= IOMMU_PROT_IR;
2453 if (iommu_prot & IOMMU_WRITE)
2454 prot |= IOMMU_PROT_IW;
2455
2456 iova &= PAGE_MASK;
2457 paddr &= PAGE_MASK;
2458
2459 mutex_lock(&domain->api_lock);
2460
2461 for (i = 0; i < npages; ++i) {
2462 ret = iommu_map_page(domain, iova, paddr, prot, PM_MAP_4k);
2463 if (ret)
2464 return ret;
2465
2466 iova += PAGE_SIZE;
2467 paddr += PAGE_SIZE;
2468 }
2469
2470 mutex_unlock(&domain->api_lock);
2471
2472 return 0;
2473 }
2474
2475 static void amd_iommu_unmap_range(struct iommu_domain *dom,
2476 unsigned long iova, size_t size)
2477 {
2478
2479 struct protection_domain *domain = dom->priv;
2480 unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE);
2481
2482 iova &= PAGE_MASK;
2483
2484 mutex_lock(&domain->api_lock);
2485
2486 for (i = 0; i < npages; ++i) {
2487 iommu_unmap_page(domain, iova, PM_MAP_4k);
2488 iova += PAGE_SIZE;
2489 }
2490
2491 iommu_flush_tlb_pde(domain);
2492
2493 mutex_unlock(&domain->api_lock);
2494 }
2495
2496 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
2497 unsigned long iova)
2498 {
2499 struct protection_domain *domain = dom->priv;
2500 unsigned long offset = iova & ~PAGE_MASK;
2501 phys_addr_t paddr;
2502 u64 *pte;
2503
2504 pte = fetch_pte(domain, iova, PM_MAP_4k);
2505
2506 if (!pte || !IOMMU_PTE_PRESENT(*pte))
2507 return 0;
2508
2509 paddr = *pte & IOMMU_PAGE_MASK;
2510 paddr |= offset;
2511
2512 return paddr;
2513 }
2514
2515 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
2516 unsigned long cap)
2517 {
2518 return 0;
2519 }
2520
2521 static struct iommu_ops amd_iommu_ops = {
2522 .domain_init = amd_iommu_domain_init,
2523 .domain_destroy = amd_iommu_domain_destroy,
2524 .attach_dev = amd_iommu_attach_device,
2525 .detach_dev = amd_iommu_detach_device,
2526 .map = amd_iommu_map_range,
2527 .unmap = amd_iommu_unmap_range,
2528 .iova_to_phys = amd_iommu_iova_to_phys,
2529 .domain_has_cap = amd_iommu_domain_has_cap,
2530 };
2531
2532 /*****************************************************************************
2533 *
2534 * The next functions do a basic initialization of IOMMU for pass through
2535 * mode
2536 *
2537 * In passthrough mode the IOMMU is initialized and enabled but not used for
2538 * DMA-API translation.
2539 *
2540 *****************************************************************************/
2541
2542 int __init amd_iommu_init_passthrough(void)
2543 {
2544 struct amd_iommu *iommu;
2545 struct pci_dev *dev = NULL;
2546 u16 devid;
2547
2548 /* allocate passthrough domain */
2549 pt_domain = protection_domain_alloc();
2550 if (!pt_domain)
2551 return -ENOMEM;
2552
2553 pt_domain->mode |= PAGE_MODE_NONE;
2554
2555 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
2556
2557 if (!check_device(&dev->dev))
2558 continue;
2559
2560 devid = get_device_id(&dev->dev);
2561
2562 iommu = amd_iommu_rlookup_table[devid];
2563 if (!iommu)
2564 continue;
2565
2566 attach_device(&dev->dev, pt_domain);
2567 }
2568
2569 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
2570
2571 return 0;
2572 }
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