drivers/staging/gma500/medfield.h

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /* Medfield DSI controller registers */
  25
  26 #define MIPIA_DEVICE_READY_REG                          0xb000
  27 #define MIPIA_INTR_STAT_REG                             0xb004
  28 #define MIPIA_INTR_EN_REG                               0xb008
  29 #define MIPIA_DSI_FUNC_PRG_REG                          0xb00c
  30 #define MIPIA_HS_TX_TIMEOUT_REG                         0xb010
  31 #define MIPIA_LP_RX_TIMEOUT_REG                         0xb014
  32 #define MIPIA_TURN_AROUND_TIMEOUT_REG                   0xb018
  33 #define MIPIA_DEVICE_RESET_TIMER_REG                    0xb01c
  34 #define MIPIA_DPI_RESOLUTION_REG                        0xb020
  35 #define MIPIA_DBI_FIFO_THROTTLE_REG                     0xb024
  36 #define MIPIA_HSYNC_COUNT_REG                           0xb028
  37 #define MIPIA_HBP_COUNT_REG                             0xb02c
  38 #define MIPIA_HFP_COUNT_REG                             0xb030
  39 #define MIPIA_HACTIVE_COUNT_REG                         0xb034
  40 #define MIPIA_VSYNC_COUNT_REG                           0xb038
  41 #define MIPIA_VBP_COUNT_REG                             0xb03c
  42 #define MIPIA_VFP_COUNT_REG                             0xb040
  43 #define MIPIA_HIGH_LOW_SWITCH_COUNT_REG                 0xb044
  44 #define MIPIA_DPI_CONTROL_REG                           0xb048
  45 #define MIPIA_DPI_DATA_REG                              0xb04c
  46 #define MIPIA_INIT_COUNT_REG                            0xb050
  47 #define MIPIA_MAX_RETURN_PACK_SIZE_REG                  0xb054
  48 #define MIPIA_VIDEO_MODE_FORMAT_REG                     0xb058
  49 #define MIPIA_EOT_DISABLE_REG                           0xb05c
  50 #define MIPIA_LP_BYTECLK_REG                            0xb060
  51 #define MIPIA_LP_GEN_DATA_REG                           0xb064
  52 #define MIPIA_HS_GEN_DATA_REG                           0xb068
  53 #define MIPIA_LP_GEN_CTRL_REG                           0xb06c
  54 #define MIPIA_HS_GEN_CTRL_REG                           0xb070
  55 #define MIPIA_GEN_FIFO_STAT_REG                         0xb074
  56 #define MIPIA_HS_LS_DBI_ENABLE_REG                      0xb078
  57 #define MIPIA_DPHY_PARAM_REG                            0xb080
  58 #define MIPIA_DBI_BW_CTRL_REG                           0xb084
  59 #define MIPIA_CLK_LANE_SWITCH_TIME_CNT_REG              0xb088
  60
  61 #define DSI_DEVICE_READY                                (0x1)
  62 #define DSI_POWER_STATE_ULPS_ENTER                      (0x2 << 1)
  63 #define DSI_POWER_STATE_ULPS_EXIT                       (0x1 << 1)
  64 #define DSI_POWER_STATE_ULPS_OFFSET                     (0x1)
  65
  66
  67 #define DSI_ONE_DATA_LANE                               (0x1)
  68 #define DSI_TWO_DATA_LANE                               (0x2)
  69 #define DSI_THREE_DATA_LANE                             (0X3)
  70 #define DSI_FOUR_DATA_LANE                              (0x4)
  71 #define DSI_DPI_VIRT_CHANNEL_OFFSET                     (0x3)
  72 #define DSI_DBI_VIRT_CHANNEL_OFFSET                     (0x5)
  73 #define DSI_DPI_COLOR_FORMAT_RGB565                     (0x01 << 7)
  74 #define DSI_DPI_COLOR_FORMAT_RGB666                     (0x02 << 7)
  75 #define DSI_DPI_COLOR_FORMAT_RGB666_UNPACK              (0x03 << 7)
  76 #define DSI_DPI_COLOR_FORMAT_RGB888                     (0x04 << 7)
  77 #define DSI_DBI_COLOR_FORMAT_OPTION2                    (0x05 << 13)
  78
  79 #define DSI_INTR_STATE_RXSOTERROR                       1
  80
  81 #define DSI_INTR_STATE_SPL_PKG_SENT                     (1 << 30)
  82 #define DSI_INTR_STATE_TE                               (1 << 31)
  83
  84 #define DSI_HS_TX_TIMEOUT_MASK                          (0xffffff)
  85
  86 #define DSI_LP_RX_TIMEOUT_MASK                          (0xffffff)
  87
  88 #define DSI_TURN_AROUND_TIMEOUT_MASK                    (0x3f)
  89
  90 #define DSI_RESET_TIMER_MASK                            (0xffff)
  91
  92 #define DSI_DBI_FIFO_WM_HALF                            (0x0)
  93 #define DSI_DBI_FIFO_WM_QUARTER                         (0x1)
  94 #define DSI_DBI_FIFO_WM_LOW                             (0x2)
  95
  96 #define DSI_DPI_TIMING_MASK                             (0xffff)
  97
  98 #define DSI_INIT_TIMER_MASK                             (0xffff)
  99
 100 #define DSI_DBI_RETURN_PACK_SIZE_MASK                   (0x3ff)
 101
 102 #define DSI_LP_BYTECLK_MASK                             (0x0ffff)
 103
 104 #define DSI_HS_CTRL_GEN_SHORT_W0                        (0x03)
 105 #define DSI_HS_CTRL_GEN_SHORT_W1                        (0x13)
 106 #define DSI_HS_CTRL_GEN_SHORT_W2                        (0x23)
 107 #define DSI_HS_CTRL_GEN_R0                              (0x04)
 108 #define DSI_HS_CTRL_GEN_R1                              (0x14)
 109 #define DSI_HS_CTRL_GEN_R2                              (0x24)
 110 #define DSI_HS_CTRL_GEN_LONG_W                          (0x29)
 111 #define DSI_HS_CTRL_MCS_SHORT_W0                        (0x05)
 112 #define DSI_HS_CTRL_MCS_SHORT_W1                        (0x15)
 113 #define DSI_HS_CTRL_MCS_R0                              (0x06)
 114 #define DSI_HS_CTRL_MCS_LONG_W                          (0x39)
 115 #define DSI_HS_CTRL_VC_OFFSET                           (0x06)
 116 #define DSI_HS_CTRL_WC_OFFSET                           (0x08)
 117
 118 #define DSI_FIFO_GEN_HS_DATA_FULL                       (1 << 0)
 119 #define DSI_FIFO_GEN_HS_DATA_HALF_EMPTY                 (1 << 1)
 120 #define DSI_FIFO_GEN_HS_DATA_EMPTY                      (1 << 2)
 121 #define DSI_FIFO_GEN_LP_DATA_FULL                       (1 << 8)
 122 #define DSI_FIFO_GEN_LP_DATA_HALF_EMPTY                 (1 << 9)
 123 #define DSI_FIFO_GEN_LP_DATA_EMPTY                      (1 << 10)
 124 #define DSI_FIFO_GEN_HS_CTRL_FULL                       (1 << 16)
 125 #define DSI_FIFO_GEN_HS_CTRL_HALF_EMPTY                 (1 << 17)
 126 #define DSI_FIFO_GEN_HS_CTRL_EMPTY                      (1 << 18)
 127 #define DSI_FIFO_GEN_LP_CTRL_FULL                       (1 << 24)
 128 #define DSI_FIFO_GEN_LP_CTRL_HALF_EMPTY                 (1 << 25)
 129 #define DSI_FIFO_GEN_LP_CTRL_EMPTY                      (1 << 26)
 130 #define DSI_FIFO_DBI_EMPTY                              (1 << 27)
 131 #define DSI_FIFO_DPI_EMPTY                              (1 << 28)
 132
 133 #define DSI_DBI_HS_LP_SWITCH_MASK                       (0x1)
 134
 135 #define DSI_HS_LP_SWITCH_COUNTER_OFFSET                 (0x0)
 136 #define DSI_LP_HS_SWITCH_COUNTER_OFFSET                 (0x16)
 137
 138 #define DSI_DPI_CTRL_HS_SHUTDOWN                        (0x00000001)
 139 #define DSI_DPI_CTRL_HS_TURN_ON                         (0x00000002)
 140
 141 /* Medfield DSI adapter registers */
 142 #define MIPIA_CONTROL_REG                               0xb104
 143 #define MIPIA_DATA_ADD_REG                              0xb108
 144 #define MIPIA_DATA_LEN_REG                              0xb10c
 145 #define MIPIA_CMD_ADD_REG                               0xb110
 146 #define MIPIA_CMD_LEN_REG                               0xb114
 147
 148 /*dsi power modes*/
 149 #define DSI_POWER_MODE_DISPLAY_ON       (1 << 2)
 150 #define DSI_POWER_MODE_NORMAL_ON        (1 << 3)
 151 #define DSI_POWER_MODE_SLEEP_OUT        (1 << 4)
 152 #define DSI_POWER_MODE_PARTIAL_ON       (1 << 5)
 153 #define DSI_POWER_MODE_IDLE_ON          (1 << 6)
 154
 155 enum {
 156         MDFLD_DSI_ENCODER_DBI = 0,
 157         MDFLD_DSI_ENCODER_DPI,
 158 };
 159
 160 enum {
 161         MDFLD_DSI_VIDEO_NON_BURST_MODE_SYNC_PULSE = 1,
 162         MDFLD_DSI_VIDEO_NON_BURST_MODE_SYNC_EVENTS = 2,
 163         MDFLD_DSI_VIDEO_BURST_MODE = 3,
 164 };
 165
 166 #define DSI_DPI_COMPLETE_LAST_LINE                      (1 << 2)
 167 #define DSI_DPI_DISABLE_BTA                             (1 << 3)
 168 /* Panel types */
 169 enum {
 170         TPO_CMD,
 171         TPO_VID,
 172         TMD_CMD,
 173         TMD_VID,
 174         PYR_CMD,
 175         PYR_VID,
 176         TPO,
 177         TMD,
 178         PYR,
 179         HDMI,
 180         GCT_DETECT
 181 };
 182
 183 /* Junk that belongs elsewhere */
 184 #define TPO_PANEL_WIDTH         84
 185 #define TPO_PANEL_HEIGHT        46
 186 #define TMD_PANEL_WIDTH         39
 187 #define TMD_PANEL_HEIGHT        71
 188 #define PYR_PANEL_WIDTH         53
 189 #define PYR_PANEL_HEIGHT        95
 190
 191 /* Panel interface */
 192 struct panel_info {
 193         u32 width_mm;
 194         u32 height_mm;
 195 };
 196
 197 struct mdfld_dsi_dbi_output;
 198
 199 struct mdfld_dsi_connector_state {
 200         u32 mipi_ctrl_reg;
 201 };
 202
 203 struct mdfld_dsi_encoder_state {
 204
 205 };
 206
 207 struct mdfld_dsi_connector {
 208         /*
 209          * This is ugly, but I have to use connector in it! :-(
 210          * FIXME: use drm_connector instead.
 211          */
 212         struct psb_intel_output base;
 213
 214         int pipe;
 215         void *private;
 216         void *pkg_sender;
 217
 218         /* Connection status */
 219         enum drm_connector_status status;
 220 };
 221
 222 struct mdfld_dsi_encoder {
 223         struct drm_encoder base;
 224         void *private;
 225 };
 226
 227 /*
 228  * DSI config, consists of one DSI connector, two DSI encoders.
 229  * DRM will pick up on DSI encoder basing on differents configs.
 230  */
 231 struct mdfld_dsi_config {
 232         struct drm_device *dev;
 233         struct drm_display_mode *fixed_mode;
 234         struct drm_display_mode *mode;
 235
 236         struct mdfld_dsi_connector *connector;
 237         struct mdfld_dsi_encoder *encoders[DRM_CONNECTOR_MAX_ENCODER];
 238         struct mdfld_dsi_encoder *encoder;
 239
 240         int changed;
 241
 242         int bpp;
 243         int type;
 244         int lane_count;
 245         /*Virtual channel number for this encoder*/
 246         int channel_num;
 247         /*video mode configure*/
 248         int video_mode;
 249
 250         int dvr_ic_inited;
 251 };
 252
 253 #define MDFLD_DSI_CONNECTOR(psb_output) \
 254                 (container_of(psb_output, struct mdfld_dsi_connector, base))
 255
 256 #define MDFLD_DSI_ENCODER(encoder) \
 257                 (container_of(encoder, struct mdfld_dsi_encoder, base))
 258
 259 struct panel_funcs {
 260         const struct drm_encoder_funcs *encoder_funcs;
 261         const struct drm_encoder_helper_funcs *encoder_helper_funcs;
 262         struct drm_display_mode *(*get_config_mode) (struct drm_device *);
 263         void (*update_fb) (struct mdfld_dsi_dbi_output *, int);
 264         int (*get_panel_info) (struct drm_device *, int, struct panel_info *);
 265         int (*reset)(int pipe);
 266         void (*drv_ic_init)(struct mdfld_dsi_config *dsi_config, int pipe);
 267 };
 268