drivers/sh/intc/core.c

   1 /*
   2  * Shared interrupt handling code for IPR and INTC2 types of IRQs.
   3  *
   4  * Copyright (C) 2007, 2008 Magnus Damm
   5  * Copyright (C) 2009, 2010 Paul Mundt
   6  *
   7  * Based on intc2.c and ipr.c
   8  *
   9  * Copyright (C) 1999  Niibe Yutaka & Takeshi Yaegashi
  10  * Copyright (C) 2000  Kazumoto Kojima
  11  * Copyright (C) 2001  David J. Mckay (david.mckay@st.com)
  12  * Copyright (C) 2003  Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
  13  * Copyright (C) 2005, 2006  Paul Mundt
  14  *
  15  * This file is subject to the terms and conditions of the GNU General Public
  16  * License.  See the file "COPYING" in the main directory of this archive
  17  * for more details.
  18  */
  19 #define pr_fmt(fmt) "intc: " fmt
  20
  21 #include <linux/init.h>
  22 #include <linux/irq.h>
  23 #include <linux/io.h>
  24 #include <linux/slab.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/sh_intc.h>
  27 #include <linux/sysdev.h>
  28 #include <linux/syscore_ops.h>
  29 #include <linux/list.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/radix-tree.h>
  32 #include "internals.h"
  33
  34 LIST_HEAD(intc_list);
  35 DEFINE_RAW_SPINLOCK(intc_big_lock);
  36 unsigned int nr_intc_controllers;
  37
  38 /*
  39  * Default priority level
  40  * - this needs to be at least 2 for 5-bit priorities on 7780
  41  */
  42 static unsigned int default_prio_level = 2;     /* 2 - 16 */
  43 static unsigned int intc_prio_level[NR_IRQS];   /* for now */
  44
  45 unsigned int intc_get_dfl_prio_level(void)
  46 {
  47         return default_prio_level;
  48 }
  49
  50 unsigned int intc_get_prio_level(unsigned int irq)
  51 {
  52         return intc_prio_level[irq];
  53 }
  54
  55 void intc_set_prio_level(unsigned int irq, unsigned int level)
  56 {
  57         unsigned long flags;
  58
  59         raw_spin_lock_irqsave(&intc_big_lock, flags);
  60         intc_prio_level[irq] = level;
  61         raw_spin_unlock_irqrestore(&intc_big_lock, flags);
  62 }
  63
  64 static void intc_redirect_irq(unsigned int irq, struct irq_desc *desc)
  65 {
  66         generic_handle_irq((unsigned int)irq_get_handler_data(irq));
  67 }
  68
  69 static void __init intc_register_irq(struct intc_desc *desc,
  70                                      struct intc_desc_int *d,
  71                                      intc_enum enum_id,
  72                                      unsigned int irq)
  73 {
  74         struct intc_handle_int *hp;
  75         struct irq_data *irq_data;
  76         unsigned int data[2], primary;
  77         unsigned long flags;
  78
  79         /*
  80          * Register the IRQ position with the global IRQ map, then insert
  81          * it in to the radix tree.
  82          */
  83         irq_reserve_irq(irq);
  84
  85         raw_spin_lock_irqsave(&intc_big_lock, flags);
  86         radix_tree_insert(&d->tree, enum_id, intc_irq_xlate_get(irq));
  87         raw_spin_unlock_irqrestore(&intc_big_lock, flags);
  88
  89         /*
  90          * Prefer single interrupt source bitmap over other combinations:
  91          *
  92          * 1. bitmap, single interrupt source
  93          * 2. priority, single interrupt source
  94          * 3. bitmap, multiple interrupt sources (groups)
  95          * 4. priority, multiple interrupt sources (groups)
  96          */
  97         data[0] = intc_get_mask_handle(desc, d, enum_id, 0);
  98         data[1] = intc_get_prio_handle(desc, d, enum_id, 0);
  99
 100         primary = 0;
 101         if (!data[0] && data[1])
 102                 primary = 1;
 103
 104         if (!data[0] && !data[1])
 105                 pr_warning("missing unique irq mask for irq %d (vect 0x%04x)\n",
 106                            irq, irq2evt(irq));
 107
 108         data[0] = data[0] ? data[0] : intc_get_mask_handle(desc, d, enum_id, 1);
 109         data[1] = data[1] ? data[1] : intc_get_prio_handle(desc, d, enum_id, 1);
 110
 111         if (!data[primary])
 112                 primary ^= 1;
 113
 114         BUG_ON(!data[primary]); /* must have primary masking method */
 115
 116         irq_data = irq_get_irq_data(irq);
 117
 118         disable_irq_nosync(irq);
 119         irq_set_chip_and_handler_name(irq, &d->chip, handle_level_irq,
 120                                       "level");
 121         irq_set_chip_data(irq, (void *)data[primary]);
 122
 123         /*
 124          * set priority level
 125          */
 126         intc_set_prio_level(irq, intc_get_dfl_prio_level());
 127
 128         /* enable secondary masking method if present */
 129         if (data[!primary])
 130                 _intc_enable(irq_data, data[!primary]);
 131
 132         /* add irq to d->prio list if priority is available */
 133         if (data[1]) {
 134                 hp = d->prio + d->nr_prio;
 135                 hp->irq = irq;
 136                 hp->handle = data[1];
 137
 138                 if (primary) {
 139                         /*
 140                          * only secondary priority should access registers, so
 141                          * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
 142                          */
 143                         hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
 144                         hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
 145                 }
 146                 d->nr_prio++;
 147         }
 148
 149         /* add irq to d->sense list if sense is available */
 150         data[0] = intc_get_sense_handle(desc, d, enum_id);
 151         if (data[0]) {
 152                 (d->sense + d->nr_sense)->irq = irq;
 153                 (d->sense + d->nr_sense)->handle = data[0];
 154                 d->nr_sense++;
 155         }
 156
 157         /* irq should be disabled by default */
 158         d->chip.irq_mask(irq_data);
 159
 160         intc_set_ack_handle(irq, desc, d, enum_id);
 161         intc_set_dist_handle(irq, desc, d, enum_id);
 162
 163         activate_irq(irq);
 164 }
 165
 166 static unsigned int __init save_reg(struct intc_desc_int *d,
 167                                     unsigned int cnt,
 168                                     unsigned long value,
 169                                     unsigned int smp)
 170 {
 171         if (value) {
 172                 value = intc_phys_to_virt(d, value);
 173
 174                 d->reg[cnt] = value;
 175 #ifdef CONFIG_SMP
 176                 d->smp[cnt] = smp;
 177 #endif
 178                 return 1;
 179         }
 180
 181         return 0;
 182 }
 183
 184 int __init register_intc_controller(struct intc_desc *desc)
 185 {
 186         unsigned int i, k, smp;
 187         struct intc_hw_desc *hw = &desc->hw;
 188         struct intc_desc_int *d;
 189         struct resource *res;
 190
 191         pr_info("Registered controller '%s' with %u IRQs\n",
 192                 desc->name, hw->nr_vectors);
 193
 194         d = kzalloc(sizeof(*d), GFP_NOWAIT);
 195         if (!d)
 196                 goto err0;
 197
 198         INIT_LIST_HEAD(&d->list);
 199         list_add_tail(&d->list, &intc_list);
 200
 201         raw_spin_lock_init(&d->lock);
 202         INIT_RADIX_TREE(&d->tree, GFP_ATOMIC);
 203
 204         d->index = nr_intc_controllers;
 205
 206         if (desc->num_resources) {
 207                 d->nr_windows = desc->num_resources;
 208                 d->window = kzalloc(d->nr_windows * sizeof(*d->window),
 209                                     GFP_NOWAIT);
 210                 if (!d->window)
 211                         goto err1;
 212
 213                 for (k = 0; k < d->nr_windows; k++) {
 214                         res = desc->resource + k;
 215                         WARN_ON(resource_type(res) != IORESOURCE_MEM);
 216                         d->window[k].phys = res->start;
 217                         d->window[k].size = resource_size(res);
 218                         d->window[k].virt = ioremap_nocache(res->start,
 219                                                          resource_size(res));
 220                         if (!d->window[k].virt)
 221                                 goto err2;
 222                 }
 223         }
 224
 225         d->nr_reg = hw->mask_regs ? hw->nr_mask_regs * 2 : 0;
 226 #ifdef CONFIG_INTC_BALANCING
 227         if (d->nr_reg)
 228                 d->nr_reg += hw->nr_mask_regs;
 229 #endif
 230         d->nr_reg += hw->prio_regs ? hw->nr_prio_regs * 2 : 0;
 231         d->nr_reg += hw->sense_regs ? hw->nr_sense_regs : 0;
 232         d->nr_reg += hw->ack_regs ? hw->nr_ack_regs : 0;
 233         d->nr_reg += hw->subgroups ? hw->nr_subgroups : 0;
 234
 235         d->reg = kzalloc(d->nr_reg * sizeof(*d->reg), GFP_NOWAIT);
 236         if (!d->reg)
 237                 goto err2;
 238
 239 #ifdef CONFIG_SMP
 240         d->smp = kzalloc(d->nr_reg * sizeof(*d->smp), GFP_NOWAIT);
 241         if (!d->smp)
 242                 goto err3;
 243 #endif
 244         k = 0;
 245
 246         if (hw->mask_regs) {
 247                 for (i = 0; i < hw->nr_mask_regs; i++) {
 248                         smp = IS_SMP(hw->mask_regs[i]);
 249                         k += save_reg(d, k, hw->mask_regs[i].set_reg, smp);
 250                         k += save_reg(d, k, hw->mask_regs[i].clr_reg, smp);
 251 #ifdef CONFIG_INTC_BALANCING
 252                         k += save_reg(d, k, hw->mask_regs[i].dist_reg, 0);
 253 #endif
 254                 }
 255         }
 256
 257         if (hw->prio_regs) {
 258                 d->prio = kzalloc(hw->nr_vectors * sizeof(*d->prio),
 259                                   GFP_NOWAIT);
 260                 if (!d->prio)
 261                         goto err4;
 262
 263                 for (i = 0; i < hw->nr_prio_regs; i++) {
 264                         smp = IS_SMP(hw->prio_regs[i]);
 265                         k += save_reg(d, k, hw->prio_regs[i].set_reg, smp);
 266                         k += save_reg(d, k, hw->prio_regs[i].clr_reg, smp);
 267                 }
 268         }
 269
 270         if (hw->sense_regs) {
 271                 d->sense = kzalloc(hw->nr_vectors * sizeof(*d->sense),
 272                                    GFP_NOWAIT);
 273                 if (!d->sense)
 274                         goto err5;
 275
 276                 for (i = 0; i < hw->nr_sense_regs; i++)
 277                         k += save_reg(d, k, hw->sense_regs[i].reg, 0);
 278         }
 279
 280         if (hw->subgroups)
 281                 for (i = 0; i < hw->nr_subgroups; i++)
 282                         if (hw->subgroups[i].reg)
 283                                 k+= save_reg(d, k, hw->subgroups[i].reg, 0);
 284
 285         memcpy(&d->chip, &intc_irq_chip, sizeof(struct irq_chip));
 286         d->chip.name = desc->name;
 287
 288         if (hw->ack_regs)
 289                 for (i = 0; i < hw->nr_ack_regs; i++)
 290                         k += save_reg(d, k, hw->ack_regs[i].set_reg, 0);
 291         else
 292                 d->chip.irq_mask_ack = d->chip.irq_disable;
 293
 294         /* disable bits matching force_disable before registering irqs */
 295         if (desc->force_disable)
 296                 intc_enable_disable_enum(desc, d, desc->force_disable, 0);
 297
 298         /* disable bits matching force_enable before registering irqs */
 299         if (desc->force_enable)
 300                 intc_enable_disable_enum(desc, d, desc->force_enable, 0);
 301
 302         BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
 303
 304         /* register the vectors one by one */
 305         for (i = 0; i < hw->nr_vectors; i++) {
 306                 struct intc_vect *vect = hw->vectors + i;
 307                 unsigned int irq = evt2irq(vect->vect);
 308                 int res;
 309
 310                 if (!vect->enum_id)
 311                         continue;
 312
 313                 res = irq_alloc_desc_at(irq, numa_node_id());
 314                 if (res != irq && res != -EEXIST) {
 315                         pr_err("can't get irq_desc for %d\n", irq);
 316                         continue;
 317                 }
 318
 319                 intc_irq_xlate_set(irq, vect->enum_id, d);
 320                 intc_register_irq(desc, d, vect->enum_id, irq);
 321
 322                 for (k = i + 1; k < hw->nr_vectors; k++) {
 323                         struct intc_vect *vect2 = hw->vectors + k;
 324                         unsigned int irq2 = evt2irq(vect2->vect);
 325
 326                         if (vect->enum_id != vect2->enum_id)
 327                                 continue;
 328
 329                         /*
 330                          * In the case of multi-evt handling and sparse
 331                          * IRQ support, each vector still needs to have
 332                          * its own backing irq_desc.
 333                          */
 334                         res = irq_alloc_desc_at(irq2, numa_node_id());
 335                         if (res != irq2 && res != -EEXIST) {
 336                                 pr_err("can't get irq_desc for %d\n", irq2);
 337                                 continue;
 338                         }
 339
 340                         vect2->enum_id = 0;
 341
 342                         /* redirect this interrupts to the first one */
 343                         irq_set_chip(irq2, &dummy_irq_chip);
 344                         irq_set_chained_handler(irq2, intc_redirect_irq);
 345                         irq_set_handler_data(irq2, (void *)irq);
 346                 }
 347         }
 348
 349         intc_subgroup_init(desc, d);
 350
 351         /* enable bits matching force_enable after registering irqs */
 352         if (desc->force_enable)
 353                 intc_enable_disable_enum(desc, d, desc->force_enable, 1);
 354
 355         nr_intc_controllers++;
 356
 357         return 0;
 358 err5:
 359         kfree(d->prio);
 360 err4:
 361 #ifdef CONFIG_SMP
 362         kfree(d->smp);
 363 err3:
 364 #endif
 365         kfree(d->reg);
 366 err2:
 367         for (k = 0; k < d->nr_windows; k++)
 368                 if (d->window[k].virt)
 369                         iounmap(d->window[k].virt);
 370
 371         kfree(d->window);
 372 err1:
 373         kfree(d);
 374 err0:
 375         pr_err("unable to allocate INTC memory\n");
 376
 377         return -ENOMEM;
 378 }
 379
 380 static int intc_suspend(void)
 381 {
 382         struct intc_desc_int *d;
 383
 384         list_for_each_entry(d, &intc_list, list) {
 385                 int irq;
 386
 387                 /* enable wakeup irqs belonging to this intc controller */
 388                 for_each_active_irq(irq) {
 389                         struct irq_data *data;
 390                         struct irq_chip *chip;
 391
 392                         data = irq_get_irq_data(irq);
 393                         chip = irq_data_get_irq_chip(data);
 394                         if (chip != &d->chip)
 395                                 continue;
 396                         if (irqd_is_wakeup_set(data))
 397                                 chip->irq_enable(data);
 398                 }
 399         }
 400         return 0;
 401 }
 402
 403 static void intc_resume(void)
 404 {
 405         struct intc_desc_int *d;
 406
 407         list_for_each_entry(d, &intc_list, list) {
 408                 int irq;
 409
 410                 for_each_active_irq(irq) {
 411                         struct irq_data *data;
 412                         struct irq_chip *chip;
 413
 414                         data = irq_get_irq_data(irq);
 415                         chip = irq_data_get_irq_chip(data);
 416                         /*
 417                          * This will catch the redirect and VIRQ cases
 418                          * due to the dummy_irq_chip being inserted.
 419                          */
 420                         if (chip != &d->chip)
 421                                 continue;
 422                         if (irqd_irq_disabled(data))
 423                                 chip->irq_disable(data);
 424                         else
 425                                 chip->irq_enable(data);
 426                 }
 427         }
 428 }
 429
 430 struct syscore_ops intc_syscore_ops = {
 431         .suspend        = intc_suspend,
 432         .resume         = intc_resume,
 433 };
 434
 435 struct sysdev_class intc_sysdev_class = {
 436         .name           = "intc",
 437 };
 438
 439 static ssize_t
 440 show_intc_name(struct sys_device *dev, struct sysdev_attribute *attr, char *buf)
 441 {
 442         struct intc_desc_int *d;
 443
 444         d = container_of(dev, struct intc_desc_int, sysdev);
 445
 446         return sprintf(buf, "%s\n", d->chip.name);
 447 }
 448
 449 static SYSDEV_ATTR(name, S_IRUGO, show_intc_name, NULL);
 450
 451 static int __init register_intc_sysdevs(void)
 452 {
 453         struct intc_desc_int *d;
 454         int error;
 455
 456         register_syscore_ops(&intc_syscore_ops);
 457
 458         error = sysdev_class_register(&intc_sysdev_class);
 459         if (!error) {
 460                 list_for_each_entry(d, &intc_list, list) {
 461                         d->sysdev.id = d->index;
 462                         d->sysdev.cls = &intc_sysdev_class;
 463                         error = sysdev_register(&d->sysdev);
 464                         if (error == 0)
 465                                 error = sysdev_create_file(&d->sysdev,
 466                                                            &attr_name);
 467                         if (error)
 468                                 break;
 469                 }
 470         }
 471
 472         if (error)
 473                 pr_err("sysdev registration error\n");
 474
 475         return error;
 476 }
 477 device_initcall(register_intc_sysdevs);