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hrtimers: Fix typo causing erratic timers
[linux-2.6/linux-mips.git] / drivers / pci / probe.c
blob48849ffdd67214265693c92076970e00ab329d2a
1 /*
2 * probe.c - PCI detection and setup code
3 */
4
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
8 #include <linux/pci.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include <linux/pci-aspm.h>
13 #include "pci.h"
14
15 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
16 #define CARDBUS_RESERVE_BUSNR 3
17
18 /* Ugh. Need to stop exporting this to modules. */
19 LIST_HEAD(pci_root_buses);
20 EXPORT_SYMBOL(pci_root_buses);
21
22
23 static int find_anything(struct device *dev, void *data)
24 {
25 return 1;
26 }
27
28 /*
29 * Some device drivers need know if pci is initiated.
30 * Basically, we think pci is not initiated when there
31 * is no device to be found on the pci_bus_type.
32 */
33 int no_pci_devices(void)
34 {
35 struct device *dev;
36 int no_devices;
37
38 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
39 no_devices = (dev == NULL);
40 put_device(dev);
41 return no_devices;
42 }
43 EXPORT_SYMBOL(no_pci_devices);
44
45 /*
46 * PCI Bus Class
47 */
48 static void release_pcibus_dev(struct device *dev)
49 {
50 struct pci_bus *pci_bus = to_pci_bus(dev);
51
52 if (pci_bus->bridge)
53 put_device(pci_bus->bridge);
54 pci_bus_remove_resources(pci_bus);
55 kfree(pci_bus);
56 }
57
58 static struct class pcibus_class = {
59 .name = "pci_bus",
60 .dev_release = &release_pcibus_dev,
61 .dev_attrs = pcibus_dev_attrs,
62 };
63
64 static int __init pcibus_class_init(void)
65 {
66 return class_register(&pcibus_class);
67 }
68 postcore_initcall(pcibus_class_init);
69
70 /*
71 * Translate the low bits of the PCI base
72 * to the resource type
73 */
74 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
75 {
76 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
77 return IORESOURCE_IO;
78
79 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
80 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
81
82 return IORESOURCE_MEM;
83 }
84
85 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
86 {
87 u64 size = mask & maxbase; /* Find the significant bits */
88 if (!size)
89 return 0;
90
91 /* Get the lowest of them to find the decode size, and
92 from that the extent. */
93 size = (size & ~(size-1)) - 1;
94
95 /* base == maxbase can be valid only if the BAR has
96 already been programmed with all 1s. */
97 if (base == maxbase && ((base | size) & mask) != mask)
98 return 0;
99
100 return size;
101 }
102
103 static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar)
104 {
105 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
106 res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
107 return pci_bar_io;
108 }
109
110 res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
111
112 if (res->flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
113 return pci_bar_mem64;
114 return pci_bar_mem32;
115 }
116
117 /**
118 * pci_read_base - read a PCI BAR
119 * @dev: the PCI device
120 * @type: type of the BAR
121 * @res: resource buffer to be filled in
122 * @pos: BAR position in the config space
123 *
124 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
125 */
126 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
127 struct resource *res, unsigned int pos)
128 {
129 u32 l, sz, mask;
130 u16 orig_cmd;
131
132 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
133
134 if (!dev->mmio_always_on) {
135 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
136 pci_write_config_word(dev, PCI_COMMAND,
137 orig_cmd & ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
138 }
139
140 res->name = pci_name(dev);
141
142 pci_read_config_dword(dev, pos, &l);
143 pci_write_config_dword(dev, pos, l | mask);
144 pci_read_config_dword(dev, pos, &sz);
145 pci_write_config_dword(dev, pos, l);
146
147 if (!dev->mmio_always_on)
148 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
149
150 /*
151 * All bits set in sz means the device isn't working properly.
152 * If the BAR isn't implemented, all bits must be 0. If it's a
153 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
154 * 1 must be clear.
155 */
156 if (!sz || sz == 0xffffffff)
157 goto fail;
158
159 /*
160 * I don't know how l can have all bits set. Copied from old code.
161 * Maybe it fixes a bug on some ancient platform.
162 */
163 if (l == 0xffffffff)
164 l = 0;
165
166 if (type == pci_bar_unknown) {
167 type = decode_bar(res, l);
168 res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
169 if (type == pci_bar_io) {
170 l &= PCI_BASE_ADDRESS_IO_MASK;
171 mask = PCI_BASE_ADDRESS_IO_MASK & IO_SPACE_LIMIT;
172 } else {
173 l &= PCI_BASE_ADDRESS_MEM_MASK;
174 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
175 }
176 } else {
177 res->flags |= (l & IORESOURCE_ROM_ENABLE);
178 l &= PCI_ROM_ADDRESS_MASK;
179 mask = (u32)PCI_ROM_ADDRESS_MASK;
180 }
181
182 if (type == pci_bar_mem64) {
183 u64 l64 = l;
184 u64 sz64 = sz;
185 u64 mask64 = mask | (u64)~0 << 32;
186
187 pci_read_config_dword(dev, pos + 4, &l);
188 pci_write_config_dword(dev, pos + 4, ~0);
189 pci_read_config_dword(dev, pos + 4, &sz);
190 pci_write_config_dword(dev, pos + 4, l);
191
192 l64 |= ((u64)l << 32);
193 sz64 |= ((u64)sz << 32);
194
195 sz64 = pci_size(l64, sz64, mask64);
196
197 if (!sz64)
198 goto fail;
199
200 if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
201 dev_err(&dev->dev, "reg %x: can't handle 64-bit BAR\n",
202 pos);
203 goto fail;
204 }
205
206 res->flags |= IORESOURCE_MEM_64;
207 if ((sizeof(resource_size_t) < 8) && l) {
208 /* Address above 32-bit boundary; disable the BAR */
209 pci_write_config_dword(dev, pos, 0);
210 pci_write_config_dword(dev, pos + 4, 0);
211 res->start = 0;
212 res->end = sz64;
213 } else {
214 res->start = l64;
215 res->end = l64 + sz64;
216 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n",
217 pos, res);
218 }
219 } else {
220 sz = pci_size(l, sz, mask);
221
222 if (!sz)
223 goto fail;
224
225 res->start = l;
226 res->end = l + sz;
227
228 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", pos, res);
229 }
230
231 out:
232 return (type == pci_bar_mem64) ? 1 : 0;
233 fail:
234 res->flags = 0;
235 goto out;
236 }
237
238 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
239 {
240 unsigned int pos, reg;
241
242 for (pos = 0; pos < howmany; pos++) {
243 struct resource *res = &dev->resource[pos];
244 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
245 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
246 }
247
248 if (rom) {
249 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
250 dev->rom_base_reg = rom;
251 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
252 IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
253 IORESOURCE_SIZEALIGN;
254 __pci_read_base(dev, pci_bar_mem32, res, rom);
255 }
256 }
257
258 static void __devinit pci_read_bridge_io(struct pci_bus *child)
259 {
260 struct pci_dev *dev = child->self;
261 u8 io_base_lo, io_limit_lo;
262 unsigned long base, limit;
263 struct resource *res;
264
265 res = child->resource[0];
266 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
267 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
268 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
269 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
270
271 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
272 u16 io_base_hi, io_limit_hi;
273 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
274 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
275 base |= (io_base_hi << 16);
276 limit |= (io_limit_hi << 16);
277 }
278
279 if (base && base <= limit) {
280 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
281 if (!res->start)
282 res->start = base;
283 if (!res->end)
284 res->end = limit + 0xfff;
285 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
286 } else {
287 dev_printk(KERN_DEBUG, &dev->dev,
288 " bridge window [io %#06lx-%#06lx] (disabled)\n",
289 base, limit);
290 }
291 }
292
293 static void __devinit pci_read_bridge_mmio(struct pci_bus *child)
294 {
295 struct pci_dev *dev = child->self;
296 u16 mem_base_lo, mem_limit_lo;
297 unsigned long base, limit;
298 struct resource *res;
299
300 res = child->resource[1];
301 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
302 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
303 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
304 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
305 if (base && base <= limit) {
306 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
307 res->start = base;
308 res->end = limit + 0xfffff;
309 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
310 } else {
311 dev_printk(KERN_DEBUG, &dev->dev,
312 " bridge window [mem %#010lx-%#010lx] (disabled)\n",
313 base, limit + 0xfffff);
314 }
315 }
316
317 static void __devinit pci_read_bridge_mmio_pref(struct pci_bus *child)
318 {
319 struct pci_dev *dev = child->self;
320 u16 mem_base_lo, mem_limit_lo;
321 unsigned long base, limit;
322 struct resource *res;
323
324 res = child->resource[2];
325 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
326 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
327 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
328 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
329
330 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
331 u32 mem_base_hi, mem_limit_hi;
332 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
333 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
334
335 /*
336 * Some bridges set the base > limit by default, and some
337 * (broken) BIOSes do not initialize them. If we find
338 * this, just assume they are not being used.
339 */
340 if (mem_base_hi <= mem_limit_hi) {
341 #if BITS_PER_LONG == 64
342 base |= ((long) mem_base_hi) << 32;
343 limit |= ((long) mem_limit_hi) << 32;
344 #else
345 if (mem_base_hi || mem_limit_hi) {
346 dev_err(&dev->dev, "can't handle 64-bit "
347 "address space for bridge\n");
348 return;
349 }
350 #endif
351 }
352 }
353 if (base && base <= limit) {
354 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
355 IORESOURCE_MEM | IORESOURCE_PREFETCH;
356 if (res->flags & PCI_PREF_RANGE_TYPE_64)
357 res->flags |= IORESOURCE_MEM_64;
358 res->start = base;
359 res->end = limit + 0xfffff;
360 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
361 } else {
362 dev_printk(KERN_DEBUG, &dev->dev,
363 " bridge window [mem %#010lx-%#010lx pref] (disabled)\n",
364 base, limit + 0xfffff);
365 }
366 }
367
368 void __devinit pci_read_bridge_bases(struct pci_bus *child)
369 {
370 struct pci_dev *dev = child->self;
371 struct resource *res;
372 int i;
373
374 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
375 return;
376
377 dev_info(&dev->dev, "PCI bridge to [bus %02x-%02x]%s\n",
378 child->secondary, child->subordinate,
379 dev->transparent ? " (subtractive decode)" : "");
380
381 pci_bus_remove_resources(child);
382 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
383 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
384
385 pci_read_bridge_io(child);
386 pci_read_bridge_mmio(child);
387 pci_read_bridge_mmio_pref(child);
388
389 if (dev->transparent) {
390 pci_bus_for_each_resource(child->parent, res, i) {
391 if (res) {
392 pci_bus_add_resource(child, res,
393 PCI_SUBTRACTIVE_DECODE);
394 dev_printk(KERN_DEBUG, &dev->dev,
395 " bridge window %pR (subtractive decode)\n",
396 res);
397 }
398 }
399 }
400 }
401
402 static struct pci_bus * pci_alloc_bus(void)
403 {
404 struct pci_bus *b;
405
406 b = kzalloc(sizeof(*b), GFP_KERNEL);
407 if (b) {
408 INIT_LIST_HEAD(&b->node);
409 INIT_LIST_HEAD(&b->children);
410 INIT_LIST_HEAD(&b->devices);
411 INIT_LIST_HEAD(&b->slots);
412 INIT_LIST_HEAD(&b->resources);
413 b->max_bus_speed = PCI_SPEED_UNKNOWN;
414 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
415 }
416 return b;
417 }
418
419 static unsigned char pcix_bus_speed[] = {
420 PCI_SPEED_UNKNOWN, /* 0 */
421 PCI_SPEED_66MHz_PCIX, /* 1 */
422 PCI_SPEED_100MHz_PCIX, /* 2 */
423 PCI_SPEED_133MHz_PCIX, /* 3 */
424 PCI_SPEED_UNKNOWN, /* 4 */
425 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
426 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
427 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
428 PCI_SPEED_UNKNOWN, /* 8 */
429 PCI_SPEED_66MHz_PCIX_266, /* 9 */
430 PCI_SPEED_100MHz_PCIX_266, /* A */
431 PCI_SPEED_133MHz_PCIX_266, /* B */
432 PCI_SPEED_UNKNOWN, /* C */
433 PCI_SPEED_66MHz_PCIX_533, /* D */
434 PCI_SPEED_100MHz_PCIX_533, /* E */
435 PCI_SPEED_133MHz_PCIX_533 /* F */
436 };
437
438 static unsigned char pcie_link_speed[] = {
439 PCI_SPEED_UNKNOWN, /* 0 */
440 PCIE_SPEED_2_5GT, /* 1 */
441 PCIE_SPEED_5_0GT, /* 2 */
442 PCIE_SPEED_8_0GT, /* 3 */
443 PCI_SPEED_UNKNOWN, /* 4 */
444 PCI_SPEED_UNKNOWN, /* 5 */
445 PCI_SPEED_UNKNOWN, /* 6 */
446 PCI_SPEED_UNKNOWN, /* 7 */
447 PCI_SPEED_UNKNOWN, /* 8 */
448 PCI_SPEED_UNKNOWN, /* 9 */
449 PCI_SPEED_UNKNOWN, /* A */
450 PCI_SPEED_UNKNOWN, /* B */
451 PCI_SPEED_UNKNOWN, /* C */
452 PCI_SPEED_UNKNOWN, /* D */
453 PCI_SPEED_UNKNOWN, /* E */
454 PCI_SPEED_UNKNOWN /* F */
455 };
456
457 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
458 {
459 bus->cur_bus_speed = pcie_link_speed[linksta & 0xf];
460 }
461 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
462
463 static unsigned char agp_speeds[] = {
464 AGP_UNKNOWN,
465 AGP_1X,
466 AGP_2X,
467 AGP_4X,
468 AGP_8X
469 };
470
471 static enum pci_bus_speed agp_speed(int agp3, int agpstat)
472 {
473 int index = 0;
474
475 if (agpstat & 4)
476 index = 3;
477 else if (agpstat & 2)
478 index = 2;
479 else if (agpstat & 1)
480 index = 1;
481 else
482 goto out;
483
484 if (agp3) {
485 index += 2;
486 if (index == 5)
487 index = 0;
488 }
489
490 out:
491 return agp_speeds[index];
492 }
493
494
495 static void pci_set_bus_speed(struct pci_bus *bus)
496 {
497 struct pci_dev *bridge = bus->self;
498 int pos;
499
500 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
501 if (!pos)
502 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
503 if (pos) {
504 u32 agpstat, agpcmd;
505
506 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
507 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
508
509 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
510 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
511 }
512
513 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
514 if (pos) {
515 u16 status;
516 enum pci_bus_speed max;
517 pci_read_config_word(bridge, pos + 2, &status);
518
519 if (status & 0x8000) {
520 max = PCI_SPEED_133MHz_PCIX_533;
521 } else if (status & 0x4000) {
522 max = PCI_SPEED_133MHz_PCIX_266;
523 } else if (status & 0x0002) {
524 if (((status >> 12) & 0x3) == 2) {
525 max = PCI_SPEED_133MHz_PCIX_ECC;
526 } else {
527 max = PCI_SPEED_133MHz_PCIX;
528 }
529 } else {
530 max = PCI_SPEED_66MHz_PCIX;
531 }
532
533 bus->max_bus_speed = max;
534 bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf];
535
536 return;
537 }
538
539 pos = pci_find_capability(bridge, PCI_CAP_ID_EXP);
540 if (pos) {
541 u32 linkcap;
542 u16 linksta;
543
544 pci_read_config_dword(bridge, pos + PCI_EXP_LNKCAP, &linkcap);
545 bus->max_bus_speed = pcie_link_speed[linkcap & 0xf];
546
547 pci_read_config_word(bridge, pos + PCI_EXP_LNKSTA, &linksta);
548 pcie_update_link_speed(bus, linksta);
549 }
550 }
551
552
553 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
554 struct pci_dev *bridge, int busnr)
555 {
556 struct pci_bus *child;
557 int i;
558
559 /*
560 * Allocate a new bus, and inherit stuff from the parent..
561 */
562 child = pci_alloc_bus();
563 if (!child)
564 return NULL;
565
566 child->parent = parent;
567 child->ops = parent->ops;
568 child->sysdata = parent->sysdata;
569 child->bus_flags = parent->bus_flags;
570
571 /* initialize some portions of the bus device, but don't register it
572 * now as the parent is not properly set up yet. This device will get
573 * registered later in pci_bus_add_devices()
574 */
575 child->dev.class = &pcibus_class;
576 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
577
578 /*
579 * Set up the primary, secondary and subordinate
580 * bus numbers.
581 */
582 child->number = child->secondary = busnr;
583 child->primary = parent->secondary;
584 child->subordinate = 0xff;
585
586 if (!bridge)
587 return child;
588
589 child->self = bridge;
590 child->bridge = get_device(&bridge->dev);
591
592 pci_set_bus_speed(child);
593
594 /* Set up default resource pointers and names.. */
595 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
596 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
597 child->resource[i]->name = child->name;
598 }
599 bridge->subordinate = child;
600
601 return child;
602 }
603
604 struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
605 {
606 struct pci_bus *child;
607
608 child = pci_alloc_child_bus(parent, dev, busnr);
609 if (child) {
610 down_write(&pci_bus_sem);
611 list_add_tail(&child->node, &parent->children);
612 up_write(&pci_bus_sem);
613 }
614 return child;
615 }
616
617 static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
618 {
619 struct pci_bus *parent = child->parent;
620
621 /* Attempts to fix that up are really dangerous unless
622 we're going to re-assign all bus numbers. */
623 if (!pcibios_assign_all_busses())
624 return;
625
626 while (parent->parent && parent->subordinate < max) {
627 parent->subordinate = max;
628 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
629 parent = parent->parent;
630 }
631 }
632
633 /*
634 * If it's a bridge, configure it and scan the bus behind it.
635 * For CardBus bridges, we don't scan behind as the devices will
636 * be handled by the bridge driver itself.
637 *
638 * We need to process bridges in two passes -- first we scan those
639 * already configured by the BIOS and after we are done with all of
640 * them, we proceed to assigning numbers to the remaining buses in
641 * order to avoid overlaps between old and new bus numbers.
642 */
643 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
644 {
645 struct pci_bus *child;
646 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
647 u32 buses, i, j = 0;
648 u16 bctl;
649 u8 primary, secondary, subordinate;
650 int broken = 0;
651
652 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
653 primary = buses & 0xFF;
654 secondary = (buses >> 8) & 0xFF;
655 subordinate = (buses >> 16) & 0xFF;
656
657 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
658 secondary, subordinate, pass);
659
660 /* Check if setup is sensible at all */
661 if (!pass &&
662 (primary != bus->number || secondary <= bus->number)) {
663 dev_dbg(&dev->dev, "bus configuration invalid, reconfiguring\n");
664 broken = 1;
665 }
666
667 /* Disable MasterAbortMode during probing to avoid reporting
668 of bus errors (in some architectures) */
669 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
670 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
671 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
672
673 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
674 !is_cardbus && !broken) {
675 unsigned int cmax;
676 /*
677 * Bus already configured by firmware, process it in the first
678 * pass and just note the configuration.
679 */
680 if (pass)
681 goto out;
682
683 /*
684 * If we already got to this bus through a different bridge,
685 * don't re-add it. This can happen with the i450NX chipset.
686 *
687 * However, we continue to descend down the hierarchy and
688 * scan remaining child buses.
689 */
690 child = pci_find_bus(pci_domain_nr(bus), secondary);
691 if (!child) {
692 child = pci_add_new_bus(bus, dev, secondary);
693 if (!child)
694 goto out;
695 child->primary = primary;
696 child->subordinate = subordinate;
697 child->bridge_ctl = bctl;
698 }
699
700 cmax = pci_scan_child_bus(child);
701 if (cmax > max)
702 max = cmax;
703 if (child->subordinate > max)
704 max = child->subordinate;
705 } else {
706 /*
707 * We need to assign a number to this bus which we always
708 * do in the second pass.
709 */
710 if (!pass) {
711 if (pcibios_assign_all_busses() || broken)
712 /* Temporarily disable forwarding of the
713 configuration cycles on all bridges in
714 this bus segment to avoid possible
715 conflicts in the second pass between two
716 bridges programmed with overlapping
717 bus ranges. */
718 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
719 buses & ~0xffffff);
720 goto out;
721 }
722
723 /* Clear errors */
724 pci_write_config_word(dev, PCI_STATUS, 0xffff);
725
726 /* Prevent assigning a bus number that already exists.
727 * This can happen when a bridge is hot-plugged */
728 if (pci_find_bus(pci_domain_nr(bus), max+1))
729 goto out;
730 child = pci_add_new_bus(bus, dev, ++max);
731 if (!child)
732 goto out;
733 buses = (buses & 0xff000000)
734 | ((unsigned int)(child->primary) << 0)
735 | ((unsigned int)(child->secondary) << 8)
736 | ((unsigned int)(child->subordinate) << 16);
737
738 /*
739 * yenta.c forces a secondary latency timer of 176.
740 * Copy that behaviour here.
741 */
742 if (is_cardbus) {
743 buses &= ~0xff000000;
744 buses |= CARDBUS_LATENCY_TIMER << 24;
745 }
746
747 /*
748 * We need to blast all three values with a single write.
749 */
750 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
751
752 if (!is_cardbus) {
753 child->bridge_ctl = bctl;
754 /*
755 * Adjust subordinate busnr in parent buses.
756 * We do this before scanning for children because
757 * some devices may not be detected if the bios
758 * was lazy.
759 */
760 pci_fixup_parent_subordinate_busnr(child, max);
761 /* Now we can scan all subordinate buses... */
762 max = pci_scan_child_bus(child);
763 /*
764 * now fix it up again since we have found
765 * the real value of max.
766 */
767 pci_fixup_parent_subordinate_busnr(child, max);
768 } else {
769 /*
770 * For CardBus bridges, we leave 4 bus numbers
771 * as cards with a PCI-to-PCI bridge can be
772 * inserted later.
773 */
774 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
775 struct pci_bus *parent = bus;
776 if (pci_find_bus(pci_domain_nr(bus),
777 max+i+1))
778 break;
779 while (parent->parent) {
780 if ((!pcibios_assign_all_busses()) &&
781 (parent->subordinate > max) &&
782 (parent->subordinate <= max+i)) {
783 j = 1;
784 }
785 parent = parent->parent;
786 }
787 if (j) {
788 /*
789 * Often, there are two cardbus bridges
790 * -- try to leave one valid bus number
791 * for each one.
792 */
793 i /= 2;
794 break;
795 }
796 }
797 max += i;
798 pci_fixup_parent_subordinate_busnr(child, max);
799 }
800 /*
801 * Set the subordinate bus number to its real value.
802 */
803 child->subordinate = max;
804 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
805 }
806
807 sprintf(child->name,
808 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
809 pci_domain_nr(bus), child->number);
810
811 /* Has only triggered on CardBus, fixup is in yenta_socket */
812 while (bus->parent) {
813 if ((child->subordinate > bus->subordinate) ||
814 (child->number > bus->subordinate) ||
815 (child->number < bus->number) ||
816 (child->subordinate < bus->number)) {
817 dev_info(&child->dev, "[bus %02x-%02x] %s "
818 "hidden behind%s bridge %s [bus %02x-%02x]\n",
819 child->number, child->subordinate,
820 (bus->number > child->subordinate &&
821 bus->subordinate < child->number) ?
822 "wholly" : "partially",
823 bus->self->transparent ? " transparent" : "",
824 dev_name(&bus->dev),
825 bus->number, bus->subordinate);
826 }
827 bus = bus->parent;
828 }
829
830 out:
831 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
832
833 return max;
834 }
835
836 /*
837 * Read interrupt line and base address registers.
838 * The architecture-dependent code can tweak these, of course.
839 */
840 static void pci_read_irq(struct pci_dev *dev)
841 {
842 unsigned char irq;
843
844 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
845 dev->pin = irq;
846 if (irq)
847 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
848 dev->irq = irq;
849 }
850
851 void set_pcie_port_type(struct pci_dev *pdev)
852 {
853 int pos;
854 u16 reg16;
855
856 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
857 if (!pos)
858 return;
859 pdev->is_pcie = 1;
860 pdev->pcie_cap = pos;
861 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
862 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
863 }
864
865 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
866 {
867 int pos;
868 u16 reg16;
869 u32 reg32;
870
871 pos = pci_pcie_cap(pdev);
872 if (!pos)
873 return;
874 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
875 if (!(reg16 & PCI_EXP_FLAGS_SLOT))
876 return;
877 pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, &reg32);
878 if (reg32 & PCI_EXP_SLTCAP_HPC)
879 pdev->is_hotplug_bridge = 1;
880 }
881
882 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
883
884 /**
885 * pci_setup_device - fill in class and map information of a device
886 * @dev: the device structure to fill
887 *
888 * Initialize the device structure with information about the device's
889 * vendor,class,memory and IO-space addresses,IRQ lines etc.
890 * Called at initialisation of the PCI subsystem and by CardBus services.
891 * Returns 0 on success and negative if unknown type of device (not normal,
892 * bridge or CardBus).
893 */
894 int pci_setup_device(struct pci_dev *dev)
895 {
896 u32 class;
897 u8 hdr_type;
898 struct pci_slot *slot;
899 int pos = 0;
900
901 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
902 return -EIO;
903
904 dev->sysdata = dev->bus->sysdata;
905 dev->dev.parent = dev->bus->bridge;
906 dev->dev.bus = &pci_bus_type;
907 dev->hdr_type = hdr_type & 0x7f;
908 dev->multifunction = !!(hdr_type & 0x80);
909 dev->error_state = pci_channel_io_normal;
910 set_pcie_port_type(dev);
911
912 list_for_each_entry(slot, &dev->bus->slots, list)
913 if (PCI_SLOT(dev->devfn) == slot->number)
914 dev->slot = slot;
915
916 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
917 set this higher, assuming the system even supports it. */
918 dev->dma_mask = 0xffffffff;
919
920 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
921 dev->bus->number, PCI_SLOT(dev->devfn),
922 PCI_FUNC(dev->devfn));
923
924 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
925 dev->revision = class & 0xff;
926 class >>= 8; /* upper 3 bytes */
927 dev->class = class;
928 class >>= 8;
929
930 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %d class %#08x\n",
931 dev->vendor, dev->device, dev->hdr_type, class);
932
933 /* need to have dev->class ready */
934 dev->cfg_size = pci_cfg_space_size(dev);
935
936 /* "Unknown power state" */
937 dev->current_state = PCI_UNKNOWN;
938
939 /* Early fixups, before probing the BARs */
940 pci_fixup_device(pci_fixup_early, dev);
941 /* device class may be changed after fixup */
942 class = dev->class >> 8;
943
944 switch (dev->hdr_type) { /* header type */
945 case PCI_HEADER_TYPE_NORMAL: /* standard header */
946 if (class == PCI_CLASS_BRIDGE_PCI)
947 goto bad;
948 pci_read_irq(dev);
949 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
950 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
951 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
952
953 /*
954 * Do the ugly legacy mode stuff here rather than broken chip
955 * quirk code. Legacy mode ATA controllers have fixed
956 * addresses. These are not always echoed in BAR0-3, and
957 * BAR0-3 in a few cases contain junk!
958 */
959 if (class == PCI_CLASS_STORAGE_IDE) {
960 u8 progif;
961 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
962 if ((progif & 1) == 0) {
963 dev->resource[0].start = 0x1F0;
964 dev->resource[0].end = 0x1F7;
965 dev->resource[0].flags = LEGACY_IO_RESOURCE;
966 dev->resource[1].start = 0x3F6;
967 dev->resource[1].end = 0x3F6;
968 dev->resource[1].flags = LEGACY_IO_RESOURCE;
969 }
970 if ((progif & 4) == 0) {
971 dev->resource[2].start = 0x170;
972 dev->resource[2].end = 0x177;
973 dev->resource[2].flags = LEGACY_IO_RESOURCE;
974 dev->resource[3].start = 0x376;
975 dev->resource[3].end = 0x376;
976 dev->resource[3].flags = LEGACY_IO_RESOURCE;
977 }
978 }
979 break;
980
981 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
982 if (class != PCI_CLASS_BRIDGE_PCI)
983 goto bad;
984 /* The PCI-to-PCI bridge spec requires that subtractive
985 decoding (i.e. transparent) bridge must have programming
986 interface code of 0x01. */
987 pci_read_irq(dev);
988 dev->transparent = ((dev->class & 0xff) == 1);
989 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
990 set_pcie_hotplug_bridge(dev);
991 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
992 if (pos) {
993 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
994 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
995 }
996 break;
997
998 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
999 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1000 goto bad;
1001 pci_read_irq(dev);
1002 pci_read_bases(dev, 1, 0);
1003 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1004 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1005 break;
1006
1007 default: /* unknown header */
1008 dev_err(&dev->dev, "unknown header type %02x, "
1009 "ignoring device\n", dev->hdr_type);
1010 return -EIO;
1011
1012 bad:
1013 dev_err(&dev->dev, "ignoring class %02x (doesn't match header "
1014 "type %02x)\n", class, dev->hdr_type);
1015 dev->class = PCI_CLASS_NOT_DEFINED;
1016 }
1017
1018 /* We found a fine healthy device, go go go... */
1019 return 0;
1020 }
1021
1022 static void pci_release_capabilities(struct pci_dev *dev)
1023 {
1024 pci_vpd_release(dev);
1025 pci_iov_release(dev);
1026 }
1027
1028 /**
1029 * pci_release_dev - free a pci device structure when all users of it are finished.
1030 * @dev: device that's been disconnected
1031 *
1032 * Will be called only by the device core when all users of this pci device are
1033 * done.
1034 */
1035 static void pci_release_dev(struct device *dev)
1036 {
1037 struct pci_dev *pci_dev;
1038
1039 pci_dev = to_pci_dev(dev);
1040 pci_release_capabilities(pci_dev);
1041 kfree(pci_dev);
1042 }
1043
1044 /**
1045 * pci_cfg_space_size - get the configuration space size of the PCI device.
1046 * @dev: PCI device
1047 *
1048 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1049 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1050 * access it. Maybe we don't have a way to generate extended config space
1051 * accesses, or the device is behind a reverse Express bridge. So we try
1052 * reading the dword at 0x100 which must either be 0 or a valid extended
1053 * capability header.
1054 */
1055 int pci_cfg_space_size_ext(struct pci_dev *dev)
1056 {
1057 u32 status;
1058 int pos = PCI_CFG_SPACE_SIZE;
1059
1060 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1061 goto fail;
1062 if (status == 0xffffffff)
1063 goto fail;
1064
1065 return PCI_CFG_SPACE_EXP_SIZE;
1066
1067 fail:
1068 return PCI_CFG_SPACE_SIZE;
1069 }
1070
1071 int pci_cfg_space_size(struct pci_dev *dev)
1072 {
1073 int pos;
1074 u32 status;
1075 u16 class;
1076
1077 class = dev->class >> 8;
1078 if (class == PCI_CLASS_BRIDGE_HOST)
1079 return pci_cfg_space_size_ext(dev);
1080
1081 pos = pci_pcie_cap(dev);
1082 if (!pos) {
1083 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1084 if (!pos)
1085 goto fail;
1086
1087 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1088 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
1089 goto fail;
1090 }
1091
1092 return pci_cfg_space_size_ext(dev);
1093
1094 fail:
1095 return PCI_CFG_SPACE_SIZE;
1096 }
1097
1098 static void pci_release_bus_bridge_dev(struct device *dev)
1099 {
1100 kfree(dev);
1101 }
1102
1103 struct pci_dev *alloc_pci_dev(void)
1104 {
1105 struct pci_dev *dev;
1106
1107 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1108 if (!dev)
1109 return NULL;
1110
1111 INIT_LIST_HEAD(&dev->bus_list);
1112
1113 return dev;
1114 }
1115 EXPORT_SYMBOL(alloc_pci_dev);
1116
1117 /*
1118 * Read the config data for a PCI device, sanity-check it
1119 * and fill in the dev structure...
1120 */
1121 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
1122 {
1123 struct pci_dev *dev;
1124 u32 l;
1125 int delay = 1;
1126
1127 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
1128 return NULL;
1129
1130 /* some broken boards return 0 or ~0 if a slot is empty: */
1131 if (l == 0xffffffff || l == 0x00000000 ||
1132 l == 0x0000ffff || l == 0xffff0000)
1133 return NULL;
1134
1135 /* Configuration request Retry Status */
1136 while (l == 0xffff0001) {
1137 msleep(delay);
1138 delay *= 2;
1139 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
1140 return NULL;
1141 /* Card hasn't responded in 60 seconds? Must be stuck. */
1142 if (delay > 60 * 1000) {
1143 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not "
1144 "responding\n", pci_domain_nr(bus),
1145 bus->number, PCI_SLOT(devfn),
1146 PCI_FUNC(devfn));
1147 return NULL;
1148 }
1149 }
1150
1151 dev = alloc_pci_dev();
1152 if (!dev)
1153 return NULL;
1154
1155 dev->bus = bus;
1156 dev->devfn = devfn;
1157 dev->vendor = l & 0xffff;
1158 dev->device = (l >> 16) & 0xffff;
1159
1160 if (pci_setup_device(dev)) {
1161 kfree(dev);
1162 return NULL;
1163 }
1164
1165 return dev;
1166 }
1167
1168 static void pci_init_capabilities(struct pci_dev *dev)
1169 {
1170 /* MSI/MSI-X list */
1171 pci_msi_init_pci_dev(dev);
1172
1173 /* Buffers for saving PCIe and PCI-X capabilities */
1174 pci_allocate_cap_save_buffers(dev);
1175
1176 /* Power Management */
1177 pci_pm_init(dev);
1178 platform_pci_wakeup_init(dev);
1179
1180 /* Vital Product Data */
1181 pci_vpd_pci22_init(dev);
1182
1183 /* Alternative Routing-ID Forwarding */
1184 pci_enable_ari(dev);
1185
1186 /* Single Root I/O Virtualization */
1187 pci_iov_init(dev);
1188
1189 /* Enable ACS P2P upstream forwarding */
1190 pci_enable_acs(dev);
1191 }
1192
1193 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1194 {
1195 device_initialize(&dev->dev);
1196 dev->dev.release = pci_release_dev;
1197 pci_dev_get(dev);
1198
1199 dev->dev.dma_mask = &dev->dma_mask;
1200 dev->dev.dma_parms = &dev->dma_parms;
1201 dev->dev.coherent_dma_mask = 0xffffffffull;
1202
1203 pci_set_dma_max_seg_size(dev, 65536);
1204 pci_set_dma_seg_boundary(dev, 0xffffffff);
1205
1206 /* Fix up broken headers */
1207 pci_fixup_device(pci_fixup_header, dev);
1208
1209 /* Clear the state_saved flag. */
1210 dev->state_saved = false;
1211
1212 /* Initialize various capabilities */
1213 pci_init_capabilities(dev);
1214
1215 /*
1216 * Add the device to our list of discovered devices
1217 * and the bus list for fixup functions, etc.
1218 */
1219 down_write(&pci_bus_sem);
1220 list_add_tail(&dev->bus_list, &bus->devices);
1221 up_write(&pci_bus_sem);
1222 }
1223
1224 struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
1225 {
1226 struct pci_dev *dev;
1227
1228 dev = pci_get_slot(bus, devfn);
1229 if (dev) {
1230 pci_dev_put(dev);
1231 return dev;
1232 }
1233
1234 dev = pci_scan_device(bus, devfn);
1235 if (!dev)
1236 return NULL;
1237
1238 pci_device_add(dev, bus);
1239
1240 return dev;
1241 }
1242 EXPORT_SYMBOL(pci_scan_single_device);
1243
1244 static unsigned next_ari_fn(struct pci_dev *dev, unsigned fn)
1245 {
1246 u16 cap;
1247 unsigned pos, next_fn;
1248
1249 if (!dev)
1250 return 0;
1251
1252 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1253 if (!pos)
1254 return 0;
1255 pci_read_config_word(dev, pos + 4, &cap);
1256 next_fn = cap >> 8;
1257 if (next_fn <= fn)
1258 return 0;
1259 return next_fn;
1260 }
1261
1262 static unsigned next_trad_fn(struct pci_dev *dev, unsigned fn)
1263 {
1264 return (fn + 1) % 8;
1265 }
1266
1267 static unsigned no_next_fn(struct pci_dev *dev, unsigned fn)
1268 {
1269 return 0;
1270 }
1271
1272 static int only_one_child(struct pci_bus *bus)
1273 {
1274 struct pci_dev *parent = bus->self;
1275 if (!parent || !pci_is_pcie(parent))
1276 return 0;
1277 if (parent->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
1278 parent->pcie_type == PCI_EXP_TYPE_DOWNSTREAM)
1279 return 1;
1280 return 0;
1281 }
1282
1283 /**
1284 * pci_scan_slot - scan a PCI slot on a bus for devices.
1285 * @bus: PCI bus to scan
1286 * @devfn: slot number to scan (must have zero function.)
1287 *
1288 * Scan a PCI slot on the specified PCI bus for devices, adding
1289 * discovered devices to the @bus->devices list. New devices
1290 * will not have is_added set.
1291 *
1292 * Returns the number of new devices found.
1293 */
1294 int pci_scan_slot(struct pci_bus *bus, int devfn)
1295 {
1296 unsigned fn, nr = 0;
1297 struct pci_dev *dev;
1298 unsigned (*next_fn)(struct pci_dev *, unsigned) = no_next_fn;
1299
1300 if (only_one_child(bus) && (devfn > 0))
1301 return 0; /* Already scanned the entire slot */
1302
1303 dev = pci_scan_single_device(bus, devfn);
1304 if (!dev)
1305 return 0;
1306 if (!dev->is_added)
1307 nr++;
1308
1309 if (pci_ari_enabled(bus))
1310 next_fn = next_ari_fn;
1311 else if (dev->multifunction)
1312 next_fn = next_trad_fn;
1313
1314 for (fn = next_fn(dev, 0); fn > 0; fn = next_fn(dev, fn)) {
1315 dev = pci_scan_single_device(bus, devfn + fn);
1316 if (dev) {
1317 if (!dev->is_added)
1318 nr++;
1319 dev->multifunction = 1;
1320 }
1321 }
1322
1323 /* only one slot has pcie device */
1324 if (bus->self && nr)
1325 pcie_aspm_init_link_state(bus->self);
1326
1327 return nr;
1328 }
1329
1330 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
1331 {
1332 unsigned int devfn, pass, max = bus->secondary;
1333 struct pci_dev *dev;
1334
1335 dev_dbg(&bus->dev, "scanning bus\n");
1336
1337 /* Go find them, Rover! */
1338 for (devfn = 0; devfn < 0x100; devfn += 8)
1339 pci_scan_slot(bus, devfn);
1340
1341 /* Reserve buses for SR-IOV capability. */
1342 max += pci_iov_bus_range(bus);
1343
1344 /*
1345 * After performing arch-dependent fixup of the bus, look behind
1346 * all PCI-to-PCI bridges on this bus.
1347 */
1348 if (!bus->is_added) {
1349 dev_dbg(&bus->dev, "fixups for bus\n");
1350 pcibios_fixup_bus(bus);
1351 if (pci_is_root_bus(bus))
1352 bus->is_added = 1;
1353 }
1354
1355 for (pass=0; pass < 2; pass++)
1356 list_for_each_entry(dev, &bus->devices, bus_list) {
1357 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1358 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1359 max = pci_scan_bridge(bus, dev, max, pass);
1360 }
1361
1362 /*
1363 * We've scanned the bus and so we know all about what's on
1364 * the other side of any bridges that may be on this bus plus
1365 * any devices.
1366 *
1367 * Return how far we've got finding sub-buses.
1368 */
1369 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
1370 return max;
1371 }
1372
1373 struct pci_bus * pci_create_bus(struct device *parent,
1374 int bus, struct pci_ops *ops, void *sysdata)
1375 {
1376 int error;
1377 struct pci_bus *b, *b2;
1378 struct device *dev;
1379
1380 b = pci_alloc_bus();
1381 if (!b)
1382 return NULL;
1383
1384 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1385 if (!dev){
1386 kfree(b);
1387 return NULL;
1388 }
1389
1390 b->sysdata = sysdata;
1391 b->ops = ops;
1392
1393 b2 = pci_find_bus(pci_domain_nr(b), bus);
1394 if (b2) {
1395 /* If we already got to this bus through a different bridge, ignore it */
1396 dev_dbg(&b2->dev, "bus already known\n");
1397 goto err_out;
1398 }
1399
1400 down_write(&pci_bus_sem);
1401 list_add_tail(&b->node, &pci_root_buses);
1402 up_write(&pci_bus_sem);
1403
1404 dev->parent = parent;
1405 dev->release = pci_release_bus_bridge_dev;
1406 dev_set_name(dev, "pci%04x:%02x", pci_domain_nr(b), bus);
1407 error = device_register(dev);
1408 if (error)
1409 goto dev_reg_err;
1410 b->bridge = get_device(dev);
1411 device_enable_async_suspend(b->bridge);
1412
1413 if (!parent)
1414 set_dev_node(b->bridge, pcibus_to_node(b));
1415
1416 b->dev.class = &pcibus_class;
1417 b->dev.parent = b->bridge;
1418 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
1419 error = device_register(&b->dev);
1420 if (error)
1421 goto class_dev_reg_err;
1422
1423 /* Create legacy_io and legacy_mem files for this bus */
1424 pci_create_legacy_files(b);
1425
1426 b->number = b->secondary = bus;
1427 b->resource[0] = &ioport_resource;
1428 b->resource[1] = &iomem_resource;
1429
1430 return b;
1431
1432 class_dev_reg_err:
1433 device_unregister(dev);
1434 dev_reg_err:
1435 down_write(&pci_bus_sem);
1436 list_del(&b->node);
1437 up_write(&pci_bus_sem);
1438 err_out:
1439 kfree(dev);
1440 kfree(b);
1441 return NULL;
1442 }
1443
1444 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1445 int bus, struct pci_ops *ops, void *sysdata)
1446 {
1447 struct pci_bus *b;
1448
1449 b = pci_create_bus(parent, bus, ops, sysdata);
1450 if (b)
1451 b->subordinate = pci_scan_child_bus(b);
1452 return b;
1453 }
1454 EXPORT_SYMBOL(pci_scan_bus_parented);
1455
1456 #ifdef CONFIG_HOTPLUG
1457 /**
1458 * pci_rescan_bus - scan a PCI bus for devices.
1459 * @bus: PCI bus to scan
1460 *
1461 * Scan a PCI bus and child buses for new devices, adds them,
1462 * and enables them.
1463 *
1464 * Returns the max number of subordinate bus discovered.
1465 */
1466 unsigned int __ref pci_rescan_bus(struct pci_bus *bus)
1467 {
1468 unsigned int max;
1469 struct pci_dev *dev;
1470
1471 max = pci_scan_child_bus(bus);
1472
1473 down_read(&pci_bus_sem);
1474 list_for_each_entry(dev, &bus->devices, bus_list)
1475 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1476 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1477 if (dev->subordinate)
1478 pci_bus_size_bridges(dev->subordinate);
1479 up_read(&pci_bus_sem);
1480
1481 pci_bus_assign_resources(bus);
1482 pci_enable_bridges(bus);
1483 pci_bus_add_devices(bus);
1484
1485 return max;
1486 }
1487 EXPORT_SYMBOL_GPL(pci_rescan_bus);
1488
1489 EXPORT_SYMBOL(pci_add_new_bus);
1490 EXPORT_SYMBOL(pci_scan_slot);
1491 EXPORT_SYMBOL(pci_scan_bridge);
1492 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1493 #endif
1494
1495 static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b)
1496 {
1497 const struct pci_dev *a = to_pci_dev(d_a);
1498 const struct pci_dev *b = to_pci_dev(d_b);
1499
1500 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1501 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
1502
1503 if (a->bus->number < b->bus->number) return -1;
1504 else if (a->bus->number > b->bus->number) return 1;
1505
1506 if (a->devfn < b->devfn) return -1;
1507 else if (a->devfn > b->devfn) return 1;
1508
1509 return 0;
1510 }
1511
1512 void __init pci_sort_breadthfirst(void)
1513 {
1514 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
1515 }
Mirror of the linux-mips.org kernel tree