2 * QLogic iSCSI HBA Driver
3 * Copyright (c) 2003-2010 QLogic Corporation
5 * See LICENSE.qla4xxx for copyright and licensing details.
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/types.h>
14 #include <linux/module.h>
15 #include <linux/list.h>
16 #include <linux/pci.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/sched.h>
19 #include <linux/slab.h>
20 #include <linux/dmapool.h>
21 #include <linux/mempool.h>
22 #include <linux/spinlock.h>
23 #include <linux/workqueue.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/mutex.h>
27 #include <linux/aer.h>
28 #include <linux/bsg-lib.h>
31 #include <scsi/scsi.h>
32 #include <scsi/scsi_host.h>
33 #include <scsi/scsi_device.h>
34 #include <scsi/scsi_cmnd.h>
35 #include <scsi/scsi_transport.h>
36 #include <scsi/scsi_transport_iscsi.h>
37 #include <scsi/scsi_bsg_iscsi.h>
38 #include <scsi/scsi_netlink.h>
39 #include <scsi/libiscsi.h>
44 #include "ql4_nvram.h"
46 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4010
47 #define PCI_DEVICE_ID_QLOGIC_ISP4010 0x4010
50 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4022
51 #define PCI_DEVICE_ID_QLOGIC_ISP4022 0x4022
54 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4032
55 #define PCI_DEVICE_ID_QLOGIC_ISP4032 0x4032
58 #ifndef PCI_DEVICE_ID_QLOGIC_ISP8022
59 #define PCI_DEVICE_ID_QLOGIC_ISP8022 0x8022
62 #define ISP4XXX_PCI_FN_1 0x1
63 #define ISP4XXX_PCI_FN_2 0x3
69 * Data bit definitions
87 #define BIT_16 0x10000
88 #define BIT_17 0x20000
89 #define BIT_18 0x40000
90 #define BIT_19 0x80000
91 #define BIT_20 0x100000
92 #define BIT_21 0x200000
93 #define BIT_22 0x400000
94 #define BIT_23 0x800000
95 #define BIT_24 0x1000000
96 #define BIT_25 0x2000000
97 #define BIT_26 0x4000000
98 #define BIT_27 0x8000000
99 #define BIT_28 0x10000000
100 #define BIT_29 0x20000000
101 #define BIT_30 0x40000000
102 #define BIT_31 0x80000000
105 * Macros to help code, maintain, etc.
107 #define ql4_printk(level, ha, format, arg...) \
108 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
112 * Host adapter default definitions
113 ***********************************/
116 #define MAX_TARGETS MAX_DEV_DB_ENTRIES
117 #define MAX_LUNS 0xffff
118 #define MAX_AEN_ENTRIES MAX_DEV_DB_ENTRIES
119 #define MAX_DDB_ENTRIES MAX_DEV_DB_ENTRIES
120 #define MAX_PDU_ENTRIES 32
121 #define INVALID_ENTRY 0xFFFF
122 #define MAX_CMDS_TO_RISC 1024
123 #define MAX_SRBS MAX_CMDS_TO_RISC
124 #define MBOX_AEN_REG_COUNT 8
125 #define MAX_INIT_RETRIES 5
130 #define REQUEST_QUEUE_DEPTH MAX_CMDS_TO_RISC
131 #define RESPONSE_QUEUE_DEPTH 64
132 #define QUEUE_SIZE 64
133 #define DMA_BUFFER_SIZE 512
138 #define MAC_ADDR_LEN 6 /* in bytes */
139 #define IP_ADDR_LEN 4 /* in bytes */
140 #define IPv6_ADDR_LEN 16 /* IPv6 address size */
141 #define DRIVER_NAME "qla4xxx"
143 #define MAX_LINKED_CMDS_PER_LUN 3
144 #define MAX_REQS_SERVICED_PER_INTR 1
146 #define ISCSI_IPADDR_SIZE 4 /* IP address size */
147 #define ISCSI_ALIAS_SIZE 32 /* ISCSI Alias name size */
148 #define ISCSI_NAME_SIZE 0xE0 /* ISCSI Name size */
150 #define QL4_SESS_RECOVERY_TMO 30 /* iSCSI session */
151 /* recovery timeout */
153 #define LSDW(x) ((u32)((u64)(x)))
154 #define MSDW(x) ((u32)((((u64)(x)) >> 16) >> 16))
157 * Retry & Timeout Values
160 #define SOFT_RESET_TOV 30
161 #define RESET_INTR_TOV 3
162 #define SEMAPHORE_TOV 10
163 #define ADAPTER_INIT_TOV 30
164 #define ADAPTER_RESET_TOV 180
165 #define EXTEND_CMD_TOV 60
166 #define WAIT_CMD_TOV 30
167 #define EH_WAIT_CMD_TOV 120
168 #define FIRMWARE_UP_TOV 60
169 #define RESET_FIRMWARE_TOV 30
170 #define LOGOUT_TOV 10
171 #define IOCB_TOV_MARGIN 10
172 #define RELOGIN_TOV 18
173 #define ISNS_DEREG_TOV 5
174 #define HBA_ONLINE_TOV 30
175 #define DISABLE_ACB_TOV 30
177 #define MAX_RESET_HA_RETRIES 2
179 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
182 * SCSI Request Block structure (srb) that is placed
183 * on cmd->SCp location of every I/O [We have 22 bytes available]
186 struct list_head list
; /* (8) */
187 struct scsi_qla_host
*ha
; /* HA the SP is queued on */
188 struct ddb_entry
*ddb
;
189 uint16_t flags
; /* (1) Status flags. */
191 #define SRB_DMA_VALID BIT_3 /* DMA Buffer mapped. */
192 #define SRB_GOT_SENSE BIT_4 /* sense data received. */
193 uint8_t state
; /* (1) Status flags. */
195 #define SRB_NO_QUEUE_STATE 0 /* Request is in between states */
196 #define SRB_FREE_STATE 1
197 #define SRB_ACTIVE_STATE 3
198 #define SRB_ACTIVE_TIMEOUT_STATE 4
199 #define SRB_SUSPENDED_STATE 7 /* Request in suspended state */
201 struct scsi_cmnd
*cmd
; /* (4) SCSI command block */
202 dma_addr_t dma_handle
; /* (4) for unmap of single transfers */
203 struct kref srb_ref
; /* reference count for this srb */
204 uint8_t err_id
; /* error id */
205 #define SRB_ERR_PORT 1 /* Request failed because "port down" */
206 #define SRB_ERR_LOOP 2 /* Request failed because "loop down" */
207 #define SRB_ERR_DEVICE 3 /* Request failed because "device error" */
208 #define SRB_ERR_OTHER 4
212 uint16_t iocb_cnt
; /* Number of used iocbs */
215 /* Used for extended sense / status continuation */
216 uint8_t *req_sense_ptr
;
217 uint16_t req_sense_len
;
222 * Asynchronous Event Queue structure
225 uint32_t mbox_sts
[MBOX_AEN_REG_COUNT
];
230 struct aen entry
[MAX_AEN_ENTRIES
];
234 * Device Database (DDB) structure
237 struct scsi_qla_host
*ha
;
238 struct iscsi_cls_session
*sess
;
239 struct iscsi_cls_conn
*conn
;
241 uint16_t fw_ddb_index
; /* DDB firmware index */
242 uint32_t fw_ddb_device_state
; /* F/W Device State -- see ql4_fw.h */
248 #define DDB_STATE_DEAD 0 /* We can no longer talk to
250 #define DDB_STATE_ONLINE 1 /* Device ready to accept
252 #define DDB_STATE_MISSING 2 /* Device logged off, trying
258 #define DF_RELOGIN 0 /* Relogin to device */
259 #define DF_ISNS_DISCOVERED 2 /* Device was discovered via iSNS */
260 #define DF_FO_MASKED 3
264 struct ql82xx_hw_data
{
265 /* Offsets for flash/nvram access (set to ~0 if not used). */
266 uint32_t flash_conf_off
;
267 uint32_t flash_data_off
;
269 uint32_t fdt_wrt_disable
;
270 uint32_t fdt_erase_cmd
;
271 uint32_t fdt_block_size
;
272 uint32_t fdt_unprotect_sec_cmd
;
273 uint32_t fdt_protect_sec_cmd
;
275 uint32_t flt_region_flt
;
276 uint32_t flt_region_fdt
;
277 uint32_t flt_region_boot
;
278 uint32_t flt_region_bootload
;
279 uint32_t flt_region_fw
;
281 uint32_t flt_iscsi_param
;
282 uint32_t flt_region_chap
;
283 uint32_t flt_chap_size
;
286 struct qla4_8xxx_legacy_intr_set
{
287 uint32_t int_vec_bit
;
288 uint32_t tgt_status_reg
;
289 uint32_t tgt_mask_reg
;
290 uint32_t pci_int_reg
;
295 #define QLA_MSIX_DEFAULT 0x00
296 #define QLA_MSIX_RSP_Q 0x01
298 #define QLA_MSIX_ENTRIES 2
299 #define QLA_MIDX_DEFAULT 0
300 #define QLA_MIDX_RSP_Q 1
302 struct ql4_msix_entry
{
304 uint16_t msix_vector
;
311 struct isp_operations
{
312 int (*iospace_config
) (struct scsi_qla_host
*ha
);
313 void (*pci_config
) (struct scsi_qla_host
*);
314 void (*disable_intrs
) (struct scsi_qla_host
*);
315 void (*enable_intrs
) (struct scsi_qla_host
*);
316 int (*start_firmware
) (struct scsi_qla_host
*);
317 irqreturn_t (*intr_handler
) (int , void *);
318 void (*interrupt_service_routine
) (struct scsi_qla_host
*, uint32_t);
319 int (*reset_chip
) (struct scsi_qla_host
*);
320 int (*reset_firmware
) (struct scsi_qla_host
*);
321 void (*queue_iocb
) (struct scsi_qla_host
*);
322 void (*complete_iocb
) (struct scsi_qla_host
*);
323 uint16_t (*rd_shdw_req_q_out
) (struct scsi_qla_host
*);
324 uint16_t (*rd_shdw_rsp_q_in
) (struct scsi_qla_host
*);
325 int (*get_sys_info
) (struct scsi_qla_host
*);
328 /*qla4xxx ipaddress configuration details */
329 struct ipaddress_config
{
330 uint16_t ipv4_options
;
331 uint16_t tcp_options
;
332 uint16_t ipv4_vlan_tag
;
333 uint8_t ipv4_addr_state
;
334 uint8_t ip_address
[IP_ADDR_LEN
];
335 uint8_t subnet_mask
[IP_ADDR_LEN
];
336 uint8_t gateway
[IP_ADDR_LEN
];
337 uint32_t ipv6_options
;
338 uint32_t ipv6_addl_options
;
339 uint8_t ipv6_link_local_state
;
340 uint8_t ipv6_addr0_state
;
341 uint8_t ipv6_addr1_state
;
342 uint8_t ipv6_default_router_state
;
343 uint16_t ipv6_vlan_tag
;
344 struct in6_addr ipv6_link_local_addr
;
345 struct in6_addr ipv6_addr0
;
346 struct in6_addr ipv6_addr1
;
347 struct in6_addr ipv6_default_router_addr
;
348 uint16_t eth_mtu_size
;
353 #define QL4_CHAP_MAX_NAME_LEN 256
354 #define QL4_CHAP_MAX_SECRET_LEN 100
358 struct ql4_chap_format
{
359 u8 intr_chap_name
[QL4_CHAP_MAX_NAME_LEN
];
360 u8 intr_secret
[QL4_CHAP_MAX_SECRET_LEN
];
361 u8 target_chap_name
[QL4_CHAP_MAX_NAME_LEN
];
362 u8 target_secret
[QL4_CHAP_MAX_SECRET_LEN
];
363 u16 intr_chap_name_length
;
364 u16 intr_secret_length
;
365 u16 target_chap_name_length
;
366 u16 target_secret_length
;
369 struct ip_address_format
{
374 struct ql4_conn_info
{
376 struct ip_address_format dest_ipaddr
;
377 struct ql4_chap_format chap
;
380 struct ql4_boot_session_info
{
382 struct ql4_conn_info conn_list
[1];
385 struct ql4_boot_tgt_info
{
386 struct ql4_boot_session_info boot_pri_sess
;
387 struct ql4_boot_session_info boot_sec_sess
;
391 * Linux Host Adapter structure
393 struct scsi_qla_host
{
394 /* Linux adapter configuration data */
397 #define AF_ONLINE 0 /* 0x00000001 */
398 #define AF_INIT_DONE 1 /* 0x00000002 */
399 #define AF_MBOX_COMMAND 2 /* 0x00000004 */
400 #define AF_MBOX_COMMAND_DONE 3 /* 0x00000008 */
401 #define AF_INTERRUPTS_ON 6 /* 0x00000040 */
402 #define AF_GET_CRASH_RECORD 7 /* 0x00000080 */
403 #define AF_LINK_UP 8 /* 0x00000100 */
404 #define AF_IRQ_ATTACHED 10 /* 0x00000400 */
405 #define AF_DISABLE_ACB_COMPLETE 11 /* 0x00000800 */
406 #define AF_HA_REMOVAL 12 /* 0x00001000 */
407 #define AF_INTx_ENABLED 15 /* 0x00008000 */
408 #define AF_MSI_ENABLED 16 /* 0x00010000 */
409 #define AF_MSIX_ENABLED 17 /* 0x00020000 */
410 #define AF_MBOX_COMMAND_NOPOLL 18 /* 0x00040000 */
411 #define AF_FW_RECOVERY 19 /* 0x00080000 */
412 #define AF_EEH_BUSY 20 /* 0x00100000 */
413 #define AF_PCI_CHANNEL_IO_PERM_FAILURE 21 /* 0x00200000 */
415 unsigned long dpc_flags
;
417 #define DPC_RESET_HA 1 /* 0x00000002 */
418 #define DPC_RETRY_RESET_HA 2 /* 0x00000004 */
419 #define DPC_RELOGIN_DEVICE 3 /* 0x00000008 */
420 #define DPC_RESET_HA_FW_CONTEXT 4 /* 0x00000010 */
421 #define DPC_RESET_HA_INTR 5 /* 0x00000020 */
422 #define DPC_ISNS_RESTART 7 /* 0x00000080 */
423 #define DPC_AEN 9 /* 0x00000200 */
424 #define DPC_GET_DHCP_IP_ADDR 15 /* 0x00008000 */
425 #define DPC_LINK_CHANGED 18 /* 0x00040000 */
426 #define DPC_RESET_ACTIVE 20 /* 0x00040000 */
427 #define DPC_HA_UNRECOVERABLE 21 /* 0x00080000 ISP-82xx only*/
428 #define DPC_HA_NEED_QUIESCENT 22 /* 0x00100000 ISP-82xx only*/
431 struct Scsi_Host
*host
; /* pointer to host data */
437 #define SRB_MIN_REQ 128
438 mempool_t
*srb_mempool
;
440 /* pci information */
441 struct pci_dev
*pdev
;
443 struct isp_reg __iomem
*reg
; /* Base I/O address */
444 unsigned long pio_address
;
445 unsigned long pio_length
;
446 #define MIN_IOBASE_LEN 0x100
448 uint16_t req_q_count
;
450 unsigned long host_no
;
452 /* NVRAM registers */
453 struct eeprom_data
*nvram
;
454 spinlock_t hardware_lock ____cacheline_aligned
;
455 uint32_t eeprom_cmd_data
;
457 /* Counters for general statistics */
459 uint64_t adapter_error_count
;
460 uint64_t device_error_count
;
461 uint64_t total_io_count
;
462 uint64_t total_mbytes_xferred
;
463 uint64_t link_failure_count
;
464 uint64_t invalid_crc_count
;
465 uint32_t bytes_xfered
;
466 uint32_t spurious_int_count
;
467 uint32_t aborted_io_count
;
468 uint32_t io_timeout_count
;
469 uint32_t mailbox_timeout_count
;
470 uint32_t seconds_since_last_intr
;
471 uint32_t seconds_since_last_heartbeat
;
474 /* Info Needed for Management App */
475 /* --- From GetFwVersion --- */
476 uint32_t firmware_version
[2];
477 uint32_t patch_number
;
478 uint32_t build_number
;
481 /* --- From Init_FW --- */
482 /* init_cb_t *init_cb; */
483 uint16_t firmware_options
;
485 uint8_t name_string
[256];
486 uint8_t heartbeat_interval
;
488 /* --- From FlashSysInfo --- */
489 uint8_t my_mac
[MAC_ADDR_LEN
];
490 uint8_t serial_number
[16];
492 /* --- From GetFwState --- */
493 uint32_t firmware_state
;
494 uint32_t addl_fw_state
;
496 /* Linux kernel thread */
497 struct workqueue_struct
*dpc_thread
;
498 struct work_struct dpc_work
;
500 /* Linux timer thread */
501 struct timer_list timer
;
502 uint32_t timer_active
;
504 /* Recovery Timers */
505 atomic_t check_relogin_timeouts
;
506 uint32_t retry_reset_ha_cnt
;
507 uint32_t isp_reset_timer
; /* reset test timer */
508 uint32_t nic_reset_timer
; /* simulated nic reset test timer */
510 struct list_head free_srb_q
;
511 uint16_t free_srb_q_count
;
512 uint16_t num_srbs_allocated
;
514 /* DMA Memory Block */
516 dma_addr_t queues_dma
;
517 unsigned long queues_len
;
519 #define MEM_ALIGN_VALUE \
520 ((max(REQUEST_QUEUE_DEPTH, RESPONSE_QUEUE_DEPTH)) * \
521 sizeof(struct queue_entry))
522 /* request and response queue variables */
523 dma_addr_t request_dma
;
524 struct queue_entry
*request_ring
;
525 struct queue_entry
*request_ptr
;
526 dma_addr_t response_dma
;
527 struct queue_entry
*response_ring
;
528 struct queue_entry
*response_ptr
;
529 dma_addr_t shadow_regs_dma
;
530 struct shadow_regs
*shadow_regs
;
531 uint16_t request_in
; /* Current indexes. */
532 uint16_t request_out
;
533 uint16_t response_in
;
534 uint16_t response_out
;
536 /* aen queue variables */
537 uint16_t aen_q_count
; /* Number of available aen_q entries */
538 uint16_t aen_in
; /* Current indexes */
540 struct aen aen_q
[MAX_AEN_ENTRIES
];
542 struct ql4_aen_log aen_log
;/* tracks all aens */
544 /* This mutex protects several threads to do mailbox commands
547 struct mutex mbox_sem
;
549 /* temporary mailbox status registers */
550 volatile uint8_t mbox_status_count
;
551 volatile uint32_t mbox_status
[MBOX_REG_COUNT
];
553 /* FW ddb index map */
554 struct ddb_entry
*fw_ddb_index_map
[MAX_DDB_ENTRIES
];
556 /* Saved srb for status continuation entry processing */
557 struct srb
*status_srb
;
561 /* qla82xx specific fields */
562 struct device_reg_82xx __iomem
*qla4_8xxx_reg
; /* Base I/O address */
563 unsigned long nx_pcibase
; /* Base I/O address */
564 uint8_t *nx_db_rd_ptr
; /* Doorbell read pointer */
565 unsigned long nx_db_wr_ptr
; /* Door bell write pointer */
566 unsigned long first_page_group_start
;
567 unsigned long first_page_group_end
;
570 uint32_t curr_window
;
571 uint32_t ddr_mn_window
;
572 unsigned long mn_win_crb
;
573 unsigned long ms_win_crb
;
579 struct qla4_8xxx_legacy_intr_set nx_legacy_intr
;
583 uint32_t fw_heartbeat_counter
;
585 struct isp_operations
*isp_ops
;
586 struct ql82xx_hw_data hw
;
588 struct ql4_msix_entry msix_entries
[QLA_MSIX_ENTRIES
];
590 uint32_t nx_dev_init_timeout
;
591 uint32_t nx_reset_timeout
;
593 struct completion mbx_intr_comp
;
595 struct ipaddress_config ip_config
;
596 struct iscsi_iface
*iface_ipv4
;
597 struct iscsi_iface
*iface_ipv6_0
;
598 struct iscsi_iface
*iface_ipv6_1
;
600 /* --- From About Firmware --- */
601 uint16_t iscsi_major
;
602 uint16_t iscsi_minor
;
603 uint16_t bootload_major
;
604 uint16_t bootload_minor
;
605 uint16_t bootload_patch
;
606 uint16_t bootload_build
;
608 uint32_t flash_state
;
609 #define QLFLASH_WAITING 0
610 #define QLFLASH_READING 1
611 #define QLFLASH_WRITING 2
612 struct dma_pool
*chap_dma_pool
;
613 uint8_t *chap_list
; /* CHAP table cache */
614 struct mutex chap_sem
;
615 #define CHAP_DMA_BLOCK_SIZE 512
616 struct workqueue_struct
*task_wq
;
617 unsigned long ddb_idx_map
[MAX_DDB_ENTRIES
/ BITS_PER_LONG
];
618 #define SYSFS_FLAG_FW_SEL_BOOT 2
619 struct iscsi_boot_kset
*boot_kset
;
620 struct ql4_boot_tgt_info boot_tgt
;
621 uint16_t phy_port_num
;
622 uint16_t phy_port_cnt
;
623 uint16_t iscsi_pci_func_cnt
;
624 uint8_t model_name
[16];
625 struct completion disable_acb_comp
;
628 struct ql4_task_data
{
629 struct scsi_qla_host
*ha
;
630 uint8_t iocb_req_cnt
;
638 struct iscsi_task
*task
;
639 struct passthru_status sts
;
640 struct work_struct task_work
;
643 struct qla_endpoint
{
644 struct Scsi_Host
*host
;
645 struct sockaddr dst_addr
;
649 struct qla_endpoint
*qla_ep
;
652 static inline int is_ipv4_enabled(struct scsi_qla_host
*ha
)
654 return ((ha
->ip_config
.ipv4_options
& IPOPT_IPV4_PROTOCOL_ENABLE
) != 0);
657 static inline int is_ipv6_enabled(struct scsi_qla_host
*ha
)
659 return ((ha
->ip_config
.ipv6_options
&
660 IPV6_OPT_IPV6_PROTOCOL_ENABLE
) != 0);
663 static inline int is_qla4010(struct scsi_qla_host
*ha
)
665 return ha
->pdev
->device
== PCI_DEVICE_ID_QLOGIC_ISP4010
;
668 static inline int is_qla4022(struct scsi_qla_host
*ha
)
670 return ha
->pdev
->device
== PCI_DEVICE_ID_QLOGIC_ISP4022
;
673 static inline int is_qla4032(struct scsi_qla_host
*ha
)
675 return ha
->pdev
->device
== PCI_DEVICE_ID_QLOGIC_ISP4032
;
678 static inline int is_qla40XX(struct scsi_qla_host
*ha
)
680 return is_qla4032(ha
) || is_qla4022(ha
) || is_qla4010(ha
);
683 static inline int is_qla8022(struct scsi_qla_host
*ha
)
685 return ha
->pdev
->device
== PCI_DEVICE_ID_QLOGIC_ISP8022
;
688 /* Note: Currently AER/EEH is now supported only for 8022 cards
689 * This function needs to be updated when AER/EEH is enabled
692 static inline int is_aer_supported(struct scsi_qla_host
*ha
)
694 return ha
->pdev
->device
== PCI_DEVICE_ID_QLOGIC_ISP8022
;
697 static inline int adapter_up(struct scsi_qla_host
*ha
)
699 return (test_bit(AF_ONLINE
, &ha
->flags
) != 0) &&
700 (test_bit(AF_LINK_UP
, &ha
->flags
) != 0);
703 static inline struct scsi_qla_host
* to_qla_host(struct Scsi_Host
*shost
)
705 return (struct scsi_qla_host
*)iscsi_host_priv(shost
);
708 static inline void __iomem
* isp_semaphore(struct scsi_qla_host
*ha
)
710 return (is_qla4010(ha
) ?
711 &ha
->reg
->u1
.isp4010
.nvram
:
712 &ha
->reg
->u1
.isp4022
.semaphore
);
715 static inline void __iomem
* isp_nvram(struct scsi_qla_host
*ha
)
717 return (is_qla4010(ha
) ?
718 &ha
->reg
->u1
.isp4010
.nvram
:
719 &ha
->reg
->u1
.isp4022
.nvram
);
722 static inline void __iomem
* isp_ext_hw_conf(struct scsi_qla_host
*ha
)
724 return (is_qla4010(ha
) ?
725 &ha
->reg
->u2
.isp4010
.ext_hw_conf
:
726 &ha
->reg
->u2
.isp4022
.p0
.ext_hw_conf
);
729 static inline void __iomem
* isp_port_status(struct scsi_qla_host
*ha
)
731 return (is_qla4010(ha
) ?
732 &ha
->reg
->u2
.isp4010
.port_status
:
733 &ha
->reg
->u2
.isp4022
.p0
.port_status
);
736 static inline void __iomem
* isp_port_ctrl(struct scsi_qla_host
*ha
)
738 return (is_qla4010(ha
) ?
739 &ha
->reg
->u2
.isp4010
.port_ctrl
:
740 &ha
->reg
->u2
.isp4022
.p0
.port_ctrl
);
743 static inline void __iomem
* isp_port_error_status(struct scsi_qla_host
*ha
)
745 return (is_qla4010(ha
) ?
746 &ha
->reg
->u2
.isp4010
.port_err_status
:
747 &ha
->reg
->u2
.isp4022
.p0
.port_err_status
);
750 static inline void __iomem
* isp_gp_out(struct scsi_qla_host
*ha
)
752 return (is_qla4010(ha
) ?
753 &ha
->reg
->u2
.isp4010
.gp_out
:
754 &ha
->reg
->u2
.isp4022
.p0
.gp_out
);
757 static inline int eeprom_ext_hw_conf_offset(struct scsi_qla_host
*ha
)
759 return (is_qla4010(ha
) ?
760 offsetof(struct eeprom_data
, isp4010
.ext_hw_conf
) / 2 :
761 offsetof(struct eeprom_data
, isp4022
.ext_hw_conf
) / 2);
764 int ql4xxx_sem_spinlock(struct scsi_qla_host
* ha
, u32 sem_mask
, u32 sem_bits
);
765 void ql4xxx_sem_unlock(struct scsi_qla_host
* ha
, u32 sem_mask
);
766 int ql4xxx_sem_lock(struct scsi_qla_host
* ha
, u32 sem_mask
, u32 sem_bits
);
768 static inline int ql4xxx_lock_flash(struct scsi_qla_host
*a
)
771 return ql4xxx_sem_spinlock(a
, QL4010_FLASH_SEM_MASK
,
772 QL4010_FLASH_SEM_BITS
);
774 return ql4xxx_sem_spinlock(a
, QL4022_FLASH_SEM_MASK
,
775 (QL4022_RESOURCE_BITS_BASE_CODE
|
776 (a
->mac_index
)) << 13);
779 static inline void ql4xxx_unlock_flash(struct scsi_qla_host
*a
)
782 ql4xxx_sem_unlock(a
, QL4010_FLASH_SEM_MASK
);
784 ql4xxx_sem_unlock(a
, QL4022_FLASH_SEM_MASK
);
787 static inline int ql4xxx_lock_nvram(struct scsi_qla_host
*a
)
790 return ql4xxx_sem_spinlock(a
, QL4010_NVRAM_SEM_MASK
,
791 QL4010_NVRAM_SEM_BITS
);
793 return ql4xxx_sem_spinlock(a
, QL4022_NVRAM_SEM_MASK
,
794 (QL4022_RESOURCE_BITS_BASE_CODE
|
795 (a
->mac_index
)) << 10);
798 static inline void ql4xxx_unlock_nvram(struct scsi_qla_host
*a
)
801 ql4xxx_sem_unlock(a
, QL4010_NVRAM_SEM_MASK
);
803 ql4xxx_sem_unlock(a
, QL4022_NVRAM_SEM_MASK
);
806 static inline int ql4xxx_lock_drvr(struct scsi_qla_host
*a
)
809 return ql4xxx_sem_lock(a
, QL4010_DRVR_SEM_MASK
,
810 QL4010_DRVR_SEM_BITS
);
812 return ql4xxx_sem_lock(a
, QL4022_DRVR_SEM_MASK
,
813 (QL4022_RESOURCE_BITS_BASE_CODE
|
814 (a
->mac_index
)) << 1);
817 static inline void ql4xxx_unlock_drvr(struct scsi_qla_host
*a
)
820 ql4xxx_sem_unlock(a
, QL4010_DRVR_SEM_MASK
);
822 ql4xxx_sem_unlock(a
, QL4022_DRVR_SEM_MASK
);
825 static inline int ql4xxx_reset_active(struct scsi_qla_host
*ha
)
827 return test_bit(DPC_RESET_ACTIVE
, &ha
->dpc_flags
) ||
828 test_bit(DPC_RESET_HA
, &ha
->dpc_flags
) ||
829 test_bit(DPC_RETRY_RESET_HA
, &ha
->dpc_flags
) ||
830 test_bit(DPC_RESET_HA_INTR
, &ha
->dpc_flags
) ||
831 test_bit(DPC_RESET_HA_FW_CONTEXT
, &ha
->dpc_flags
) ||
832 test_bit(DPC_HA_UNRECOVERABLE
, &ha
->dpc_flags
);
835 /*---------------------------------------------------------------------------*/
837 /* Defines for qla4xxx_initialize_adapter() and qla4xxx_recover_adapter() */
838 #define PRESERVE_DDB_LIST 0
839 #define REBUILD_DDB_LIST 1
841 /* Defines for process_aen() */
842 #define PROCESS_ALL_AENS 0
843 #define FLUSH_DDB_CHANGED_AENS 1
845 #endif /*_QLA4XXX_H */