x86: cache_info: Kill the atomic allocation in amd_init_l3_cache()
[linux-2.6/linux-mips.git] / drivers / ata / pata_cmd64x.c
blob7bafc16cf5e0c89202752125773916ce71fb7fee
1 /*
2 * pata_cmd64x.c - CMD64x PATA for new ATA layer
3 * (C) 2005 Red Hat Inc
4 * Alan Cox <alan@lxorguk.ukuu.org.uk>
5 * (C) 2009-2010 Bartlomiej Zolnierkiewicz
7 * Based upon
8 * linux/drivers/ide/pci/cmd64x.c Version 1.30 Sept 10, 2002
10 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
11 * Note, this driver is not used at all on other systems because
12 * there the "BIOS" has done all of the following already.
13 * Due to massive hardware bugs, UltraDMA is only supported
14 * on the 646U2 and not on the 646U.
16 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
17 * Copyright (C) 1998 David S. Miller (davem@redhat.com)
19 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
21 * TODO
22 * Testing work
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/init.h>
29 #include <linux/blkdev.h>
30 #include <linux/delay.h>
31 #include <scsi/scsi_host.h>
32 #include <linux/libata.h>
34 #define DRV_NAME "pata_cmd64x"
35 #define DRV_VERSION "0.2.5"
38 * CMD64x specific registers definition.
41 enum {
42 CFR = 0x50,
43 CFR_INTR_CH0 = 0x04,
44 CNTRL = 0x51,
45 CNTRL_CH0 = 0x04,
46 CNTRL_CH1 = 0x08,
47 CMDTIM = 0x52,
48 ARTTIM0 = 0x53,
49 DRWTIM0 = 0x54,
50 ARTTIM1 = 0x55,
51 DRWTIM1 = 0x56,
52 ARTTIM23 = 0x57,
53 ARTTIM23_DIS_RA2 = 0x04,
54 ARTTIM23_DIS_RA3 = 0x08,
55 ARTTIM23_INTR_CH1 = 0x10,
56 DRWTIM2 = 0x58,
57 BRST = 0x59,
58 DRWTIM3 = 0x5b,
59 BMIDECR0 = 0x70,
60 MRDMODE = 0x71,
61 MRDMODE_INTR_CH0 = 0x04,
62 MRDMODE_INTR_CH1 = 0x08,
63 BMIDESR0 = 0x72,
64 UDIDETCR0 = 0x73,
65 DTPR0 = 0x74,
66 BMIDECR1 = 0x78,
67 BMIDECSR = 0x79,
68 UDIDETCR1 = 0x7B,
69 DTPR1 = 0x7C
72 static int cmd648_cable_detect(struct ata_port *ap)
74 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
75 u8 r;
77 /* Check cable detect bits */
78 pci_read_config_byte(pdev, BMIDECSR, &r);
79 if (r & (1 << ap->port_no))
80 return ATA_CBL_PATA80;
81 return ATA_CBL_PATA40;
84 /**
85 * cmd64x_set_piomode - set PIO and MWDMA timing
86 * @ap: ATA interface
87 * @adev: ATA device
88 * @mode: mode
90 * Called to do the PIO and MWDMA mode setup.
93 static void cmd64x_set_timing(struct ata_port *ap, struct ata_device *adev, u8 mode)
95 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
96 struct ata_timing t;
97 const unsigned long T = 1000000 / 33;
98 const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 };
100 u8 reg;
102 /* Port layout is not logical so use a table */
103 const u8 arttim_port[2][2] = {
104 { ARTTIM0, ARTTIM1 },
105 { ARTTIM23, ARTTIM23 }
107 const u8 drwtim_port[2][2] = {
108 { DRWTIM0, DRWTIM1 },
109 { DRWTIM2, DRWTIM3 }
112 int arttim = arttim_port[ap->port_no][adev->devno];
113 int drwtim = drwtim_port[ap->port_no][adev->devno];
115 /* ata_timing_compute is smart and will produce timings for MWDMA
116 that don't violate the drives PIO capabilities. */
117 if (ata_timing_compute(adev, mode, &t, T, 0) < 0) {
118 printk(KERN_ERR DRV_NAME ": mode computation failed.\n");
119 return;
121 if (ap->port_no) {
122 /* Slave has shared address setup */
123 struct ata_device *pair = ata_dev_pair(adev);
125 if (pair) {
126 struct ata_timing tp;
127 ata_timing_compute(pair, pair->pio_mode, &tp, T, 0);
128 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
132 printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n",
133 t.active, t.recover, t.setup);
134 if (t.recover > 16) {
135 t.active += t.recover - 16;
136 t.recover = 16;
138 if (t.active > 16)
139 t.active = 16;
141 /* Now convert the clocks into values we can actually stuff into
142 the chip */
144 if (t.recover == 16)
145 t.recover = 0;
146 else if (t.recover > 1)
147 t.recover--;
148 else
149 t.recover = 15;
151 if (t.setup > 4)
152 t.setup = 0xC0;
153 else
154 t.setup = setup_data[t.setup];
156 t.active &= 0x0F; /* 0 = 16 */
158 /* Load setup timing */
159 pci_read_config_byte(pdev, arttim, &reg);
160 reg &= 0x3F;
161 reg |= t.setup;
162 pci_write_config_byte(pdev, arttim, reg);
164 /* Load active/recovery */
165 pci_write_config_byte(pdev, drwtim, (t.active << 4) | t.recover);
169 * cmd64x_set_piomode - set initial PIO mode data
170 * @ap: ATA interface
171 * @adev: ATA device
173 * Used when configuring the devices ot set the PIO timings. All the
174 * actual work is done by the PIO/MWDMA setting helper
177 static void cmd64x_set_piomode(struct ata_port *ap, struct ata_device *adev)
179 cmd64x_set_timing(ap, adev, adev->pio_mode);
183 * cmd64x_set_dmamode - set initial DMA mode data
184 * @ap: ATA interface
185 * @adev: ATA device
187 * Called to do the DMA mode setup.
190 static void cmd64x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
192 static const u8 udma_data[] = {
193 0x30, 0x20, 0x10, 0x20, 0x10, 0x00
196 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
197 u8 regU, regD;
199 int pciU = UDIDETCR0 + 8 * ap->port_no;
200 int pciD = BMIDESR0 + 8 * ap->port_no;
201 int shift = 2 * adev->devno;
203 pci_read_config_byte(pdev, pciD, &regD);
204 pci_read_config_byte(pdev, pciU, &regU);
206 /* DMA bits off */
207 regD &= ~(0x20 << adev->devno);
208 /* DMA control bits */
209 regU &= ~(0x30 << shift);
210 /* DMA timing bits */
211 regU &= ~(0x05 << adev->devno);
213 if (adev->dma_mode >= XFER_UDMA_0) {
214 /* Merge the timing value */
215 regU |= udma_data[adev->dma_mode - XFER_UDMA_0] << shift;
216 /* Merge the control bits */
217 regU |= 1 << adev->devno; /* UDMA on */
218 if (adev->dma_mode > XFER_UDMA_2) /* 15nS timing */
219 regU |= 4 << adev->devno;
220 } else {
221 regU &= ~ (1 << adev->devno); /* UDMA off */
222 cmd64x_set_timing(ap, adev, adev->dma_mode);
225 regD |= 0x20 << adev->devno;
227 pci_write_config_byte(pdev, pciU, regU);
228 pci_write_config_byte(pdev, pciD, regD);
232 * cmd648_dma_stop - DMA stop callback
233 * @qc: Command in progress
235 * DMA has completed.
238 static void cmd648_bmdma_stop(struct ata_queued_cmd *qc)
240 struct ata_port *ap = qc->ap;
241 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
242 u8 dma_intr;
243 int dma_mask = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0;
244 int dma_reg = ap->port_no ? ARTTIM23 : CFR;
246 ata_bmdma_stop(qc);
248 pci_read_config_byte(pdev, dma_reg, &dma_intr);
249 pci_write_config_byte(pdev, dma_reg, dma_intr | dma_mask);
253 * cmd646r1_dma_stop - DMA stop callback
254 * @qc: Command in progress
256 * Stub for now while investigating the r1 quirk in the old driver.
259 static void cmd646r1_bmdma_stop(struct ata_queued_cmd *qc)
261 ata_bmdma_stop(qc);
264 static struct scsi_host_template cmd64x_sht = {
265 ATA_BMDMA_SHT(DRV_NAME),
268 static const struct ata_port_operations cmd64x_base_ops = {
269 .inherits = &ata_bmdma_port_ops,
270 .set_piomode = cmd64x_set_piomode,
271 .set_dmamode = cmd64x_set_dmamode,
274 static struct ata_port_operations cmd64x_port_ops = {
275 .inherits = &cmd64x_base_ops,
276 .cable_detect = ata_cable_40wire,
279 static struct ata_port_operations cmd646r1_port_ops = {
280 .inherits = &cmd64x_base_ops,
281 .bmdma_stop = cmd646r1_bmdma_stop,
282 .cable_detect = ata_cable_40wire,
285 static struct ata_port_operations cmd648_port_ops = {
286 .inherits = &cmd64x_base_ops,
287 .bmdma_stop = cmd648_bmdma_stop,
288 .cable_detect = cmd648_cable_detect,
291 static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
293 static const struct ata_port_info cmd_info[6] = {
294 { /* CMD 643 - no UDMA */
295 .flags = ATA_FLAG_SLAVE_POSS,
296 .pio_mask = ATA_PIO4,
297 .mwdma_mask = ATA_MWDMA2,
298 .port_ops = &cmd64x_port_ops
300 { /* CMD 646 with broken UDMA */
301 .flags = ATA_FLAG_SLAVE_POSS,
302 .pio_mask = ATA_PIO4,
303 .mwdma_mask = ATA_MWDMA2,
304 .port_ops = &cmd64x_port_ops
306 { /* CMD 646 with working UDMA */
307 .flags = ATA_FLAG_SLAVE_POSS,
308 .pio_mask = ATA_PIO4,
309 .mwdma_mask = ATA_MWDMA2,
310 .udma_mask = ATA_UDMA2,
311 .port_ops = &cmd64x_port_ops
313 { /* CMD 646 rev 1 */
314 .flags = ATA_FLAG_SLAVE_POSS,
315 .pio_mask = ATA_PIO4,
316 .mwdma_mask = ATA_MWDMA2,
317 .port_ops = &cmd646r1_port_ops
319 { /* CMD 648 */
320 .flags = ATA_FLAG_SLAVE_POSS,
321 .pio_mask = ATA_PIO4,
322 .mwdma_mask = ATA_MWDMA2,
323 .udma_mask = ATA_UDMA4,
324 .port_ops = &cmd648_port_ops
326 { /* CMD 649 */
327 .flags = ATA_FLAG_SLAVE_POSS,
328 .pio_mask = ATA_PIO4,
329 .mwdma_mask = ATA_MWDMA2,
330 .udma_mask = ATA_UDMA5,
331 .port_ops = &cmd648_port_ops
334 const struct ata_port_info *ppi[] = {
335 &cmd_info[id->driver_data],
336 &cmd_info[id->driver_data],
337 NULL
339 u8 mrdmode, reg;
340 int rc;
341 struct pci_dev *bridge = pdev->bus->self;
342 /* mobility split bridges don't report enabled ports correctly */
343 int port_ok = !(bridge && bridge->vendor ==
344 PCI_VENDOR_ID_MOBILITY_ELECTRONICS);
345 /* all (with exceptions below) apart from 643 have CNTRL_CH0 bit */
346 int cntrl_ch0_ok = (id->driver_data != 0);
348 rc = pcim_enable_device(pdev);
349 if (rc)
350 return rc;
352 if (id->driver_data == 0) /* 643 */
353 ata_pci_bmdma_clear_simplex(pdev);
355 if (pdev->device == PCI_DEVICE_ID_CMD_646) {
356 /* Does UDMA work ? */
357 if (pdev->revision > 4) {
358 ppi[0] = &cmd_info[2];
359 ppi[1] = &cmd_info[2];
361 /* Early rev with other problems ? */
362 else if (pdev->revision == 1) {
363 ppi[0] = &cmd_info[3];
364 ppi[1] = &cmd_info[3];
366 /* revs 1,2 have no CNTRL_CH0 */
367 if (pdev->revision < 3)
368 cntrl_ch0_ok = 0;
371 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
372 pci_read_config_byte(pdev, MRDMODE, &mrdmode);
373 mrdmode &= ~ 0x30; /* IRQ set up */
374 mrdmode |= 0x02; /* Memory read line enable */
375 pci_write_config_byte(pdev, MRDMODE, mrdmode);
377 /* check for enabled ports */
378 pci_read_config_byte(pdev, CNTRL, &reg);
379 if (!port_ok)
380 dev_printk(KERN_NOTICE, &pdev->dev, "Mobility Bridge detected, ignoring CNTRL port enable/disable\n");
381 if (port_ok && cntrl_ch0_ok && !(reg & CNTRL_CH0)) {
382 dev_printk(KERN_NOTICE, &pdev->dev, "Primary port is disabled\n");
383 ppi[0] = &ata_dummy_port_info;
386 if (port_ok && !(reg & CNTRL_CH1)) {
387 dev_printk(KERN_NOTICE, &pdev->dev, "Secondary port is disabled\n");
388 ppi[1] = &ata_dummy_port_info;
391 /* Force PIO 0 here.. */
393 /* PPC specific fixup copied from old driver */
394 #ifdef CONFIG_PPC
395 pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
396 #endif
398 return ata_pci_bmdma_init_one(pdev, ppi, &cmd64x_sht, NULL, 0);
401 #ifdef CONFIG_PM
402 static int cmd64x_reinit_one(struct pci_dev *pdev)
404 struct ata_host *host = dev_get_drvdata(&pdev->dev);
405 u8 mrdmode;
406 int rc;
408 rc = ata_pci_device_do_resume(pdev);
409 if (rc)
410 return rc;
412 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
413 pci_read_config_byte(pdev, MRDMODE, &mrdmode);
414 mrdmode &= ~ 0x30; /* IRQ set up */
415 mrdmode |= 0x02; /* Memory read line enable */
416 pci_write_config_byte(pdev, MRDMODE, mrdmode);
417 #ifdef CONFIG_PPC
418 pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
419 #endif
420 ata_host_resume(host);
421 return 0;
423 #endif
425 static const struct pci_device_id cmd64x[] = {
426 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
427 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
428 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 4 },
429 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 5 },
431 { },
434 static struct pci_driver cmd64x_pci_driver = {
435 .name = DRV_NAME,
436 .id_table = cmd64x,
437 .probe = cmd64x_init_one,
438 .remove = ata_pci_remove_one,
439 #ifdef CONFIG_PM
440 .suspend = ata_pci_device_suspend,
441 .resume = cmd64x_reinit_one,
442 #endif
445 static int __init cmd64x_init(void)
447 return pci_register_driver(&cmd64x_pci_driver);
450 static void __exit cmd64x_exit(void)
452 pci_unregister_driver(&cmd64x_pci_driver);
455 MODULE_AUTHOR("Alan Cox");
456 MODULE_DESCRIPTION("low-level driver for CMD64x series PATA controllers");
457 MODULE_LICENSE("GPL");
458 MODULE_DEVICE_TABLE(pci, cmd64x);
459 MODULE_VERSION(DRV_VERSION);
461 module_init(cmd64x_init);
462 module_exit(cmd64x_exit);