MIPS: Octeon: Rewrite interrupt handling code.
commit0c3263870f5f80cf7b6cb322bd8e708ce568d36b
authorDavid Daney <ddaney@caviumnetworks.com>
Fri, 25 Mar 2011 19:38:51 +0000 (25 12:38 -0700)
committerThomas Gleixner <tglx@linutronix.de>
Tue, 29 Mar 2011 12:48:06 +0000 (29 14:48 +0200)
treeb1e2ed41a6b9b10a16fdb290f6f54cb148ccaf1a
parenta458465641bf61a00f4ca54da7265202a911f975
MIPS: Octeon: Rewrite interrupt handling code.

This includes conversion to new style irq_chip functions, and
correctly enabling/disabling per-CPU interrupts.

The hardware interrupt bit to irq number mapping is now done with a
flexible map, instead of by bit twiddling the irq number.

[ tglx: Adjusted to new irq_cpu_on/offline callbacks and
        __irq_set_affinity_lock ]

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Cc: ralf@linux-mips.org
LKML-Reference: <1301081931-11240-5-git-send-email-ddaney@caviumnetworks.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
arch/mips/cavium-octeon/octeon-irq.c
arch/mips/cavium-octeon/setup.c
arch/mips/cavium-octeon/smp.c
arch/mips/include/asm/mach-cavium-octeon/irq.h
arch/mips/include/asm/octeon/octeon.h
arch/mips/pci/msi-octeon.c