include/linux/mlx4/device.h

   1 /*
   2  * Copyright (c) 2006, 2007 Cisco Systems, Inc.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef MLX4_DEVICE_H
  34 #define MLX4_DEVICE_H
  35
  36 #include <linux/pci.h>
  37 #include <linux/completion.h>
  38 #include <linux/radix-tree.h>
  39
  40 #include <asm/atomic.h>
  41
  42 enum {
  43         MLX4_FLAG_MSI_X         = 1 << 0,
  44         MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
  45 };
  46
  47 enum {
  48         MLX4_MAX_PORTS          = 2
  49 };
  50
  51 enum {
  52         MLX4_BOARD_ID_LEN = 64
  53 };
  54
  55 enum {
  56         MLX4_DEV_CAP_FLAG_RC            = 1 <<  0,
  57         MLX4_DEV_CAP_FLAG_UC            = 1 <<  1,
  58         MLX4_DEV_CAP_FLAG_UD            = 1 <<  2,
  59         MLX4_DEV_CAP_FLAG_SRQ           = 1 <<  6,
  60         MLX4_DEV_CAP_FLAG_IPOIB_CSUM    = 1 <<  7,
  61         MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1 <<  8,
  62         MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1 <<  9,
  63         MLX4_DEV_CAP_FLAG_MEM_WINDOW    = 1 << 16,
  64         MLX4_DEV_CAP_FLAG_APM           = 1 << 17,
  65         MLX4_DEV_CAP_FLAG_ATOMIC        = 1 << 18,
  66         MLX4_DEV_CAP_FLAG_RAW_MCAST     = 1 << 19,
  67         MLX4_DEV_CAP_FLAG_UD_AV_PORT    = 1 << 20,
  68         MLX4_DEV_CAP_FLAG_UD_MCAST      = 1 << 21
  69 };
  70
  71 enum mlx4_event {
  72         MLX4_EVENT_TYPE_COMP               = 0x00,
  73         MLX4_EVENT_TYPE_PATH_MIG           = 0x01,
  74         MLX4_EVENT_TYPE_COMM_EST           = 0x02,
  75         MLX4_EVENT_TYPE_SQ_DRAINED         = 0x03,
  76         MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE    = 0x13,
  77         MLX4_EVENT_TYPE_SRQ_LIMIT          = 0x14,
  78         MLX4_EVENT_TYPE_CQ_ERROR           = 0x04,
  79         MLX4_EVENT_TYPE_WQ_CATAS_ERROR     = 0x05,
  80         MLX4_EVENT_TYPE_EEC_CATAS_ERROR    = 0x06,
  81         MLX4_EVENT_TYPE_PATH_MIG_FAILED    = 0x07,
  82         MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
  83         MLX4_EVENT_TYPE_WQ_ACCESS_ERROR    = 0x11,
  84         MLX4_EVENT_TYPE_SRQ_CATAS_ERROR    = 0x12,
  85         MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR  = 0x08,
  86         MLX4_EVENT_TYPE_PORT_CHANGE        = 0x09,
  87         MLX4_EVENT_TYPE_EQ_OVERFLOW        = 0x0f,
  88         MLX4_EVENT_TYPE_ECC_DETECT         = 0x0e,
  89         MLX4_EVENT_TYPE_CMD                = 0x0a
  90 };
  91
  92 enum {
  93         MLX4_PORT_CHANGE_SUBTYPE_DOWN   = 1,
  94         MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
  95 };
  96
  97 enum {
  98         MLX4_PERM_LOCAL_READ    = 1 << 10,
  99         MLX4_PERM_LOCAL_WRITE   = 1 << 11,
 100         MLX4_PERM_REMOTE_READ   = 1 << 12,
 101         MLX4_PERM_REMOTE_WRITE  = 1 << 13,
 102         MLX4_PERM_ATOMIC        = 1 << 14
 103 };
 104
 105 enum {
 106         MLX4_OPCODE_NOP                 = 0x00,
 107         MLX4_OPCODE_SEND_INVAL          = 0x01,
 108         MLX4_OPCODE_RDMA_WRITE          = 0x08,
 109         MLX4_OPCODE_RDMA_WRITE_IMM      = 0x09,
 110         MLX4_OPCODE_SEND                = 0x0a,
 111         MLX4_OPCODE_SEND_IMM            = 0x0b,
 112         MLX4_OPCODE_LSO                 = 0x0e,
 113         MLX4_OPCODE_RDMA_READ           = 0x10,
 114         MLX4_OPCODE_ATOMIC_CS           = 0x11,
 115         MLX4_OPCODE_ATOMIC_FA           = 0x12,
 116         MLX4_OPCODE_ATOMIC_MASK_CS      = 0x14,
 117         MLX4_OPCODE_ATOMIC_MASK_FA      = 0x15,
 118         MLX4_OPCODE_BIND_MW             = 0x18,
 119         MLX4_OPCODE_FMR                 = 0x19,
 120         MLX4_OPCODE_LOCAL_INVAL         = 0x1b,
 121         MLX4_OPCODE_CONFIG_CMD          = 0x1f,
 122
 123         MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
 124         MLX4_RECV_OPCODE_SEND           = 0x01,
 125         MLX4_RECV_OPCODE_SEND_IMM       = 0x02,
 126         MLX4_RECV_OPCODE_SEND_INVAL     = 0x03,
 127
 128         MLX4_CQE_OPCODE_ERROR           = 0x1e,
 129         MLX4_CQE_OPCODE_RESIZE          = 0x16,
 130 };
 131
 132 enum {
 133         MLX4_STAT_RATE_OFFSET   = 5
 134 };
 135
 136 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
 137 {
 138         return (major << 32) | (minor << 16) | subminor;
 139 }
 140
 141 struct mlx4_caps {
 142         u64                     fw_ver;
 143         int                     num_ports;
 144         int                     vl_cap[MLX4_MAX_PORTS + 1];
 145         int                     mtu_cap[MLX4_MAX_PORTS + 1];
 146         int                     gid_table_len[MLX4_MAX_PORTS + 1];
 147         int                     pkey_table_len[MLX4_MAX_PORTS + 1];
 148         int                     local_ca_ack_delay;
 149         int                     num_uars;
 150         int                     bf_reg_size;
 151         int                     bf_regs_per_page;
 152         int                     max_sq_sg;
 153         int                     max_rq_sg;
 154         int                     num_qps;
 155         int                     max_wqes;
 156         int                     max_sq_desc_sz;
 157         int                     max_rq_desc_sz;
 158         int                     max_qp_init_rdma;
 159         int                     max_qp_dest_rdma;
 160         int                     reserved_qps;
 161         int                     sqp_start;
 162         int                     num_srqs;
 163         int                     max_srq_wqes;
 164         int                     max_srq_sge;
 165         int                     reserved_srqs;
 166         int                     num_cqs;
 167         int                     max_cqes;
 168         int                     reserved_cqs;
 169         int                     num_eqs;
 170         int                     reserved_eqs;
 171         int                     num_mpts;
 172         int                     num_mtt_segs;
 173         int                     fmr_reserved_mtts;
 174         int                     reserved_mtts;
 175         int                     reserved_mrws;
 176         int                     reserved_uars;
 177         int                     num_mgms;
 178         int                     num_amgms;
 179         int                     reserved_mcgs;
 180         int                     num_qp_per_mgm;
 181         int                     num_pds;
 182         int                     reserved_pds;
 183         int                     mtt_entry_sz;
 184         u32                     max_msg_sz;
 185         u32                     page_size_cap;
 186         u32                     flags;
 187         u16                     stat_rate_support;
 188         u8                      port_width_cap[MLX4_MAX_PORTS + 1];
 189         int                     max_gso_sz;
 190 };
 191
 192 struct mlx4_buf_list {
 193         void                   *buf;
 194         dma_addr_t              map;
 195 };
 196
 197 struct mlx4_buf {
 198         struct mlx4_buf_list    direct;
 199         struct mlx4_buf_list   *page_list;
 200         int                     nbufs;
 201         int                     npages;
 202         int                     page_shift;
 203 };
 204
 205 struct mlx4_mtt {
 206         u32                     first_seg;
 207         int                     order;
 208         int                     page_shift;
 209 };
 210
 211 enum {
 212         MLX4_DB_PER_PAGE = PAGE_SIZE / 4
 213 };
 214
 215 struct mlx4_db_pgdir {
 216         struct list_head        list;
 217         DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
 218         DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
 219         unsigned long          *bits[2];
 220         __be32                 *db_page;
 221         dma_addr_t              db_dma;
 222 };
 223
 224 struct mlx4_ib_user_db_page;
 225
 226 struct mlx4_db {
 227         __be32                  *db;
 228         union {
 229                 struct mlx4_db_pgdir            *pgdir;
 230                 struct mlx4_ib_user_db_page     *user_page;
 231         }                       u;
 232         dma_addr_t              dma;
 233         int                     index;
 234         int                     order;
 235 };
 236
 237 struct mlx4_hwq_resources {
 238         struct mlx4_db          db;
 239         struct mlx4_mtt         mtt;
 240         struct mlx4_buf         buf;
 241 };
 242
 243 struct mlx4_mr {
 244         struct mlx4_mtt         mtt;
 245         u64                     iova;
 246         u64                     size;
 247         u32                     key;
 248         u32                     pd;
 249         u32                     access;
 250         int                     enabled;
 251 };
 252
 253 struct mlx4_fmr {
 254         struct mlx4_mr          mr;
 255         struct mlx4_mpt_entry  *mpt;
 256         __be64                 *mtts;
 257         dma_addr_t              dma_handle;
 258         int                     max_pages;
 259         int                     max_maps;
 260         int                     maps;
 261         u8                      page_shift;
 262 };
 263
 264 struct mlx4_uar {
 265         unsigned long           pfn;
 266         int                     index;
 267 };
 268
 269 struct mlx4_cq {
 270         void (*comp)            (struct mlx4_cq *);
 271         void (*event)           (struct mlx4_cq *, enum mlx4_event);
 272
 273         struct mlx4_uar        *uar;
 274
 275         u32                     cons_index;
 276
 277         __be32                 *set_ci_db;
 278         __be32                 *arm_db;
 279         int                     arm_sn;
 280
 281         int                     cqn;
 282
 283         atomic_t                refcount;
 284         struct completion       free;
 285 };
 286
 287 struct mlx4_qp {
 288         void (*event)           (struct mlx4_qp *, enum mlx4_event);
 289
 290         int                     qpn;
 291
 292         atomic_t                refcount;
 293         struct completion       free;
 294 };
 295
 296 struct mlx4_srq {
 297         void (*event)           (struct mlx4_srq *, enum mlx4_event);
 298
 299         int                     srqn;
 300         int                     max;
 301         int                     max_gs;
 302         int                     wqe_shift;
 303
 304         atomic_t                refcount;
 305         struct completion       free;
 306 };
 307
 308 struct mlx4_av {
 309         __be32                  port_pd;
 310         u8                      reserved1;
 311         u8                      g_slid;
 312         __be16                  dlid;
 313         u8                      reserved2;
 314         u8                      gid_index;
 315         u8                      stat_rate;
 316         u8                      hop_limit;
 317         __be32                  sl_tclass_flowlabel;
 318         u8                      dgid[16];
 319 };
 320
 321 struct mlx4_dev {
 322         struct pci_dev         *pdev;
 323         unsigned long           flags;
 324         struct mlx4_caps        caps;
 325         struct radix_tree_root  qp_table_tree;
 326         u32                     rev_id;
 327         char                    board_id[MLX4_BOARD_ID_LEN];
 328 };
 329
 330 struct mlx4_init_port_param {
 331         int                     set_guid0;
 332         int                     set_node_guid;
 333         int                     set_si_guid;
 334         u16                     mtu;
 335         int                     port_width_cap;
 336         u16                     vl_cap;
 337         u16                     max_gid;
 338         u16                     max_pkey;
 339         u64                     guid0;
 340         u64                     node_guid;
 341         u64                     si_guid;
 342 };
 343
 344 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
 345                    struct mlx4_buf *buf);
 346 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
 347 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
 348 {
 349         if (BITS_PER_LONG == 64 || buf->nbufs == 1)
 350                 return buf->direct.buf + offset;
 351         else
 352                 return buf->page_list[offset >> PAGE_SHIFT].buf +
 353                         (offset & (PAGE_SIZE - 1));
 354 }
 355
 356 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
 357 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
 358
 359 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
 360 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
 361
 362 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
 363                   struct mlx4_mtt *mtt);
 364 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
 365 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
 366
 367 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
 368                   int npages, int page_shift, struct mlx4_mr *mr);
 369 void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
 370 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
 371 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
 372                    int start_index, int npages, u64 *page_list);
 373 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
 374                        struct mlx4_buf *buf);
 375
 376 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
 377 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
 378
 379 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
 380                        int size, int max_direct);
 381 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
 382                        int size);
 383
 384 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
 385                   struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
 386                   int collapsed);
 387 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
 388
 389 int mlx4_qp_alloc(struct mlx4_dev *dev, int sqpn, struct mlx4_qp *qp);
 390 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
 391
 392 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, struct mlx4_mtt *mtt,
 393                    u64 db_rec, struct mlx4_srq *srq);
 394 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
 395 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
 396 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
 397
 398 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
 399 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
 400
 401 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16]);
 402 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16]);
 403
 404 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
 405                       int npages, u64 iova, u32 *lkey, u32 *rkey);
 406 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
 407                    int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
 408 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
 409 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
 410                     u32 *lkey, u32 *rkey);
 411 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
 412 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
 413
 414 #endif /* MLX4_DEVICE_H */