include/asm-mips/rtlx.h

   1 /*
   2  * Copyright (C) 2004, 2005 MIPS Technologies, Inc.  All rights reserved.
   3  *
   4  */
   5
   6 #ifndef __ASM_RTLX_H
   7 #define __ASM_RTLX_H_
   8
   9 #define LX_NODE_BASE 10
  10
  11 #define MIPSCPU_INT_BASE       16
  12 #define MIPS_CPU_RTLX_IRQ 0
  13
  14 #define RTLX_VERSION 2
  15 #define RTLX_xID 0x12345600
  16 #define RTLX_ID (RTLX_xID | RTLX_VERSION)
  17 #define RTLX_CHANNELS 8
  18
  19 #define RTLX_CHANNEL_STDIO      0
  20 #define RTLX_CHANNEL_DBG        1
  21 #define RTLX_CHANNEL_SYSIO      2
  22
  23 extern int rtlx_open(int index, int can_sleep);
  24 extern int rtlx_release(int index);
  25 extern ssize_t rtlx_read(int index, void *buff, size_t count, int user);
  26 extern ssize_t rtlx_write(int index, void *buffer, size_t count, int user);
  27 extern unsigned int rtlx_read_poll(int index, int can_sleep);
  28 extern unsigned int rtlx_write_poll(int index);
  29
  30 enum rtlx_state {
  31         RTLX_STATE_UNUSED,
  32         RTLX_STATE_INITIALISED,
  33         RTLX_STATE_REMOTE_READY,
  34         RTLX_STATE_OPENED
  35 };
  36
  37 #define RTLX_BUFFER_SIZE 1024
  38
  39 /* each channel supports read and write.
  40    linux (vpe0) reads lx_buffer  and writes rt_buffer
  41    SP (vpe1) reads rt_buffer and writes lx_buffer
  42 */
  43 struct rtlx_channel {
  44         enum rtlx_state rt_state;
  45         enum rtlx_state lx_state;
  46
  47         int buffer_size;
  48
  49         /* read and write indexes per buffer */
  50         int rt_write, rt_read;
  51         char *rt_buffer;
  52
  53         int lx_write, lx_read;
  54         char *lx_buffer;
  55 };
  56
  57 struct rtlx_info {
  58         unsigned long id;
  59         enum rtlx_state state;
  60
  61         struct rtlx_channel channel[RTLX_CHANNELS];
  62 };
  63
  64 #endif /* __ASM_RTLX_H_ */