| commit | 847b9dfccad7dd34b2e44b1c6ceeb1c4cb88084a | |
| author | Chris Dearman <chris@mips.com> | |
| Mon, 7 Aug 2006 14:08:01 +0000 (7 15:08 +0100) | ||
| committer | Ralf Baechle <ralf@linux-mips.org> | |
| Wed, 27 Sep 2006 12:37:33 +0000 (27 13:37 +0100) | ||
| tree | 46374a118b2f42c17aef00ec478021043e56e38b | treesnapshot (tar.gz zip) |
| parent | bca70d24c09b740d6fd96b972011644cba8383d6 | commitdiff |
[MIPS] MT: Initialise all writable bits in Cause register to zero.
Recent 34Ks come out of reset with WP enabled on VPE 1 so we take an
immediate exception when starting the second VPE.
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Recent 34Ks come out of reset with WP enabled on VPE 1 so we take an
immediate exception when starting the second VPE.
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| arch/mips/kernel/smp-mt.c | diffblobblamehistory |