arch/mips/sgi-ip32/ip32-irq.c

   1 /*
   2  * Code to handle IP32 IRQs
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 2000 Harald Koerfgen
   9  * Copyright (C) 2001 Keith M Wesolowski
  10  */
  11 #include <linux/init.h>
  12 #include <linux/kernel_stat.h>
  13 #include <linux/types.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/irq.h>
  16 #include <linux/bitops.h>
  17 #include <linux/kernel.h>
  18 #include <linux/slab.h>
  19 #include <linux/mm.h>
  20 #include <linux/random.h>
  21 #include <linux/sched.h>
  22
  23 #include <asm/irq_cpu.h>
  24 #include <asm/mipsregs.h>
  25 #include <asm/signal.h>
  26 #include <asm/system.h>
  27 #include <asm/time.h>
  28 #include <asm/ip32/crime.h>
  29 #include <asm/ip32/mace.h>
  30 #include <asm/ip32/ip32_ints.h>
  31
  32 /* issue a PIO read to make sure no PIO writes are pending */
  33 static void inline flush_crime_bus(void)
  34 {
  35         crime->control;
  36 }
  37
  38 static void inline flush_mace_bus(void)
  39 {
  40         mace->perif.ctrl.misc;
  41 }
  42
  43 #undef DEBUG_IRQ
  44 #ifdef DEBUG_IRQ
  45 #define DBG(x...) printk(x)
  46 #else
  47 #define DBG(x...)
  48 #endif
  49
  50 /*
  51  * O2 irq map
  52  *
  53  * IP0 -> software (ignored)
  54  * IP1 -> software (ignored)
  55  * IP2 -> (irq0) C crime 1.1 all interrupts; crime 1.5 ???
  56  * IP3 -> (irq1) X unknown
  57  * IP4 -> (irq2) X unknown
  58  * IP5 -> (irq3) X unknown
  59  * IP6 -> (irq4) X unknown
  60  * IP7 -> (irq5) 7 CPU count/compare timer (system timer)
  61  *
  62  * crime: (C)
  63  *
  64  * CRIME_INT_STAT 31:0:
  65  *
  66  * 0  ->  8  Video in 1
  67  * 1  ->  9 Video in 2
  68  * 2  -> 10  Video out
  69  * 3  -> 11  Mace ethernet
  70  * 4  -> S  SuperIO sub-interrupt
  71  * 5  -> M  Miscellaneous sub-interrupt
  72  * 6  -> A  Audio sub-interrupt
  73  * 7  -> 15  PCI bridge errors
  74  * 8  -> 16  PCI SCSI aic7xxx 0
  75  * 9  -> 17 PCI SCSI aic7xxx 1
  76  * 10 -> 18 PCI slot 0
  77  * 11 -> 19 unused (PCI slot 1)
  78  * 12 -> 20 unused (PCI slot 2)
  79  * 13 -> 21 unused (PCI shared 0)
  80  * 14 -> 22 unused (PCI shared 1)
  81  * 15 -> 23 unused (PCI shared 2)
  82  * 16 -> 24 GBE0 (E)
  83  * 17 -> 25 GBE1 (E)
  84  * 18 -> 26 GBE2 (E)
  85  * 19 -> 27 GBE3 (E)
  86  * 20 -> 28 CPU errors
  87  * 21 -> 29 Memory errors
  88  * 22 -> 30 RE empty edge (E)
  89  * 23 -> 31 RE full edge (E)
  90  * 24 -> 32 RE idle edge (E)
  91  * 25 -> 33 RE empty level
  92  * 26 -> 34 RE full level
  93  * 27 -> 35 RE idle level
  94  * 28 -> 36 unused (software 0) (E)
  95  * 29 -> 37 unused (software 1) (E)
  96  * 30 -> 38 unused (software 2) - crime 1.5 CPU SysCorError (E)
  97  * 31 -> 39 VICE
  98  *
  99  * S, M, A: Use the MACE ISA interrupt register
 100  * MACE_ISA_INT_STAT 31:0
 101  *
 102  * 0-7 -> 40-47 Audio
 103  * 8 -> 48 RTC
 104  * 9 -> 49 Keyboard
 105  * 10 -> X Keyboard polled
 106  * 11 -> 51 Mouse
 107  * 12 -> X Mouse polled
 108  * 13-15 -> 53-55 Count/compare timers
 109  * 16-19 -> 56-59 Parallel (16 E)
 110  * 20-25 -> 60-62 Serial 1 (22 E)
 111  * 26-31 -> 66-71 Serial 2 (28 E)
 112  *
 113  * Note that this means IRQs 12-14, 50, and 52 do not exist.  This is a
 114  * different IRQ map than IRIX uses, but that's OK as Linux irq handling
 115  * is quite different anyway.
 116  */
 117
 118 /* Some initial interrupts to set up */
 119 extern irqreturn_t crime_memerr_intr(int irq, void *dev_id);
 120 extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id);
 121
 122 struct irqaction memerr_irq = {
 123         .handler = crime_memerr_intr,
 124         .flags = IRQF_DISABLED,
 125         .mask = CPU_MASK_NONE,
 126         .name = "CRIME memory error",
 127 };
 128 struct irqaction cpuerr_irq = {
 129         .handler = crime_cpuerr_intr,
 130         .flags = IRQF_DISABLED,
 131         .mask = CPU_MASK_NONE,
 132         .name = "CRIME CPU error",
 133 };
 134
 135 /*
 136  * This is for pure CRIME interrupts - ie not MACE.  The advantage?
 137  * We get to split the register in half and do faster lookups.
 138  */
 139
 140 static uint64_t crime_mask;
 141
 142 static void enable_crime_irq(unsigned int irq)
 143 {
 144         crime_mask |= 1 << (irq - 1);
 145         crime->imask = crime_mask;
 146 }
 147
 148 static void disable_crime_irq(unsigned int irq)
 149 {
 150         crime_mask &= ~(1 << (irq - 1));
 151         crime->imask = crime_mask;
 152         flush_crime_bus();
 153 }
 154
 155 static void mask_and_ack_crime_irq(unsigned int irq)
 156 {
 157         /* Edge triggered interrupts must be cleared. */
 158         if ((irq >= CRIME_GBE0_IRQ && irq <= CRIME_GBE3_IRQ)
 159             || (irq >= CRIME_RE_EMPTY_E_IRQ && irq <= CRIME_RE_IDLE_E_IRQ)
 160             || (irq >= CRIME_SOFT0_IRQ && irq <= CRIME_SOFT2_IRQ)) {
 161                 uint64_t crime_int;
 162                 crime_int = crime->hard_int;
 163                 crime_int &= ~(1 << (irq - 1));
 164                 crime->hard_int = crime_int;
 165         }
 166         disable_crime_irq(irq);
 167 }
 168
 169 static void end_crime_irq(unsigned int irq)
 170 {
 171         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
 172                 enable_crime_irq(irq);
 173 }
 174
 175 static struct irq_chip ip32_crime_interrupt = {
 176         .name = "IP32 CRIME",
 177         .ack = mask_and_ack_crime_irq,
 178         .mask = disable_crime_irq,
 179         .mask_ack = mask_and_ack_crime_irq,
 180         .unmask = enable_crime_irq,
 181         .end = end_crime_irq,
 182 };
 183
 184 /*
 185  * This is for MACE PCI interrupts.  We can decrease bus traffic by masking
 186  * as close to the source as possible.  This also means we can take the
 187  * next chunk of the CRIME register in one piece.
 188  */
 189
 190 static unsigned long macepci_mask;
 191
 192 static void enable_macepci_irq(unsigned int irq)
 193 {
 194         macepci_mask |= MACEPCI_CONTROL_INT(irq - 9);
 195         mace->pci.control = macepci_mask;
 196         crime_mask |= 1 << (irq - 1);
 197         crime->imask = crime_mask;
 198 }
 199
 200 static void disable_macepci_irq(unsigned int irq)
 201 {
 202         crime_mask &= ~(1 << (irq - 1));
 203         crime->imask = crime_mask;
 204         flush_crime_bus();
 205         macepci_mask &= ~MACEPCI_CONTROL_INT(irq - 9);
 206         mace->pci.control = macepci_mask;
 207         flush_mace_bus();
 208 }
 209
 210 static void end_macepci_irq(unsigned int irq)
 211 {
 212         if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
 213                 enable_macepci_irq(irq);
 214 }
 215
 216 static struct irq_chip ip32_macepci_interrupt = {
 217         .name = "IP32 MACE PCI",
 218         .ack = disable_macepci_irq,
 219         .mask = disable_macepci_irq,
 220         .mask_ack = disable_macepci_irq,
 221         .unmask = enable_macepci_irq,
 222         .end = end_macepci_irq,
 223 };
 224
 225 /* This is used for MACE ISA interrupts.  That means bits 4-6 in the
 226  * CRIME register.
 227  */
 228
 229 #define MACEISA_AUDIO_INT       (MACEISA_AUDIO_SW_INT |         \
 230                                  MACEISA_AUDIO_SC_INT |         \
 231                                  MACEISA_AUDIO1_DMAT_INT |      \
 232                                  MACEISA_AUDIO1_OF_INT |        \
 233                                  MACEISA_AUDIO2_DMAT_INT |      \
 234                                  MACEISA_AUDIO2_MERR_INT |      \
 235                                  MACEISA_AUDIO3_DMAT_INT |      \
 236                                  MACEISA_AUDIO3_MERR_INT)
 237 #define MACEISA_MISC_INT        (MACEISA_RTC_INT |              \
 238                                  MACEISA_KEYB_INT |             \
 239                                  MACEISA_KEYB_POLL_INT |        \
 240                                  MACEISA_MOUSE_INT |            \
 241                                  MACEISA_MOUSE_POLL_INT |       \
 242                                  MACEISA_TIMER0_INT |           \
 243                                  MACEISA_TIMER1_INT |           \
 244                                  MACEISA_TIMER2_INT)
 245 #define MACEISA_SUPERIO_INT     (MACEISA_PARALLEL_INT |         \
 246                                  MACEISA_PAR_CTXA_INT |         \
 247                                  MACEISA_PAR_CTXB_INT |         \
 248                                  MACEISA_PAR_MERR_INT |         \
 249                                  MACEISA_SERIAL1_INT |          \
 250                                  MACEISA_SERIAL1_TDMAT_INT |    \
 251                                  MACEISA_SERIAL1_TDMAPR_INT |   \
 252                                  MACEISA_SERIAL1_TDMAME_INT |   \
 253                                  MACEISA_SERIAL1_RDMAT_INT |    \
 254                                  MACEISA_SERIAL1_RDMAOR_INT |   \
 255                                  MACEISA_SERIAL2_INT |          \
 256                                  MACEISA_SERIAL2_TDMAT_INT |    \
 257                                  MACEISA_SERIAL2_TDMAPR_INT |   \
 258                                  MACEISA_SERIAL2_TDMAME_INT |   \
 259                                  MACEISA_SERIAL2_RDMAT_INT |    \
 260                                  MACEISA_SERIAL2_RDMAOR_INT)
 261
 262 static unsigned long maceisa_mask;
 263
 264 static void enable_maceisa_irq(unsigned int irq)
 265 {
 266         unsigned int crime_int = 0;
 267
 268         DBG("maceisa enable: %u\n", irq);
 269
 270         switch (irq) {
 271         case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ:
 272                 crime_int = MACE_AUDIO_INT;
 273                 break;
 274         case MACEISA_RTC_IRQ ... MACEISA_TIMER2_IRQ:
 275                 crime_int = MACE_MISC_INT;
 276                 break;
 277         case MACEISA_PARALLEL_IRQ ... MACEISA_SERIAL2_RDMAOR_IRQ:
 278                 crime_int = MACE_SUPERIO_INT;
 279                 break;
 280         }
 281         DBG("crime_int %08x enabled\n", crime_int);
 282         crime_mask |= crime_int;
 283         crime->imask = crime_mask;
 284         maceisa_mask |= 1 << (irq - 33);
 285         mace->perif.ctrl.imask = maceisa_mask;
 286 }
 287
 288 static void disable_maceisa_irq(unsigned int irq)
 289 {
 290         unsigned int crime_int = 0;
 291
 292         maceisa_mask &= ~(1 << (irq - 33));
 293         if(!(maceisa_mask & MACEISA_AUDIO_INT))
 294                 crime_int |= MACE_AUDIO_INT;
 295         if(!(maceisa_mask & MACEISA_MISC_INT))
 296                 crime_int |= MACE_MISC_INT;
 297         if(!(maceisa_mask & MACEISA_SUPERIO_INT))
 298                 crime_int |= MACE_SUPERIO_INT;
 299         crime_mask &= ~crime_int;
 300         crime->imask = crime_mask;
 301         flush_crime_bus();
 302         mace->perif.ctrl.imask = maceisa_mask;
 303         flush_mace_bus();
 304 }
 305
 306 static void mask_and_ack_maceisa_irq(unsigned int irq)
 307 {
 308         unsigned long mace_int;
 309
 310         switch (irq) {
 311         case MACEISA_PARALLEL_IRQ:
 312         case MACEISA_SERIAL1_TDMAPR_IRQ:
 313         case MACEISA_SERIAL2_TDMAPR_IRQ:
 314                 /* edge triggered */
 315                 mace_int = mace->perif.ctrl.istat;
 316                 mace_int &= ~(1 << (irq - 33));
 317                 mace->perif.ctrl.istat = mace_int;
 318                 break;
 319         }
 320         disable_maceisa_irq(irq);
 321 }
 322
 323 static void end_maceisa_irq(unsigned irq)
 324 {
 325         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
 326                 enable_maceisa_irq(irq);
 327 }
 328
 329 static struct irq_chip ip32_maceisa_interrupt = {
 330         .name = "IP32 MACE ISA",
 331         .ack = mask_and_ack_maceisa_irq,
 332         .mask = disable_maceisa_irq,
 333         .mask_ack = mask_and_ack_maceisa_irq,
 334         .unmask = enable_maceisa_irq,
 335         .end = end_maceisa_irq,
 336 };
 337
 338 /* This is used for regular non-ISA, non-PCI MACE interrupts.  That means
 339  * bits 0-3 and 7 in the CRIME register.
 340  */
 341
 342 static void enable_mace_irq(unsigned int irq)
 343 {
 344         crime_mask |= 1 << (irq - 1);
 345         crime->imask = crime_mask;
 346 }
 347
 348 static void disable_mace_irq(unsigned int irq)
 349 {
 350         crime_mask &= ~(1 << (irq - 1));
 351         crime->imask = crime_mask;
 352         flush_crime_bus();
 353 }
 354
 355 static void end_mace_irq(unsigned int irq)
 356 {
 357         if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
 358                 enable_mace_irq(irq);
 359 }
 360
 361 static struct irq_chip ip32_mace_interrupt = {
 362         .name = "IP32 MACE",
 363         .ack = disable_mace_irq,
 364         .mask = disable_mace_irq,
 365         .mask_ack = disable_mace_irq,
 366         .unmask = enable_mace_irq,
 367         .end = end_mace_irq,
 368 };
 369
 370 static void ip32_unknown_interrupt(void)
 371 {
 372         printk("Unknown interrupt occurred!\n");
 373         printk("cp0_status: %08x\n", read_c0_status());
 374         printk("cp0_cause: %08x\n", read_c0_cause());
 375         printk("CRIME intr mask: %016lx\n", crime->imask);
 376         printk("CRIME intr status: %016lx\n", crime->istat);
 377         printk("CRIME hardware intr register: %016lx\n", crime->hard_int);
 378         printk("MACE ISA intr mask: %08lx\n", mace->perif.ctrl.imask);
 379         printk("MACE ISA intr status: %08lx\n", mace->perif.ctrl.istat);
 380         printk("MACE PCI control register: %08x\n", mace->pci.control);
 381
 382         printk("Register dump:\n");
 383         show_regs(get_irq_regs());
 384
 385         printk("Please mail this report to linux-mips@linux-mips.org\n");
 386         printk("Spinning...");
 387         while(1) ;
 388 }
 389
 390 /* CRIME 1.1 appears to deliver all interrupts to this one pin. */
 391 /* change this to loop over all edge-triggered irqs, exception masked out ones */
 392 static void ip32_irq0(void)
 393 {
 394         uint64_t crime_int;
 395         int irq = 0;
 396
 397         /*
 398          * Sanity check interrupt numbering enum.
 399          * MACE got 32 interrupts and there are 32 MACE ISA interrupts daisy
 400          * chained.
 401          */
 402         BUILD_BUG_ON(CRIME_VICE_IRQ - MACE_VID_IN1_IRQ != 31);
 403         BUILD_BUG_ON(MACEISA_SERIAL2_RDMAOR_IRQ - MACEISA_AUDIO_SW_IRQ != 31);
 404
 405         crime_int = crime->istat & crime_mask;
 406         irq = MACE_VID_IN1_IRQ + __ffs(crime_int);
 407         crime_int = 1 << irq;
 408
 409         if (crime_int & CRIME_MACEISA_INT_MASK) {
 410                 unsigned long mace_int = mace->perif.ctrl.istat;
 411                 irq = __ffs(mace_int & maceisa_mask) + MACEISA_AUDIO_SW_IRQ;
 412         }
 413
 414         DBG("*irq %u*\n", irq);
 415         do_IRQ(irq);
 416 }
 417
 418 static void ip32_irq1(void)
 419 {
 420         ip32_unknown_interrupt();
 421 }
 422
 423 static void ip32_irq2(void)
 424 {
 425         ip32_unknown_interrupt();
 426 }
 427
 428 static void ip32_irq3(void)
 429 {
 430         ip32_unknown_interrupt();
 431 }
 432
 433 static void ip32_irq4(void)
 434 {
 435         ip32_unknown_interrupt();
 436 }
 437
 438 static void ip32_irq5(void)
 439 {
 440         do_IRQ(MIPS_CPU_IRQ_BASE + 7);
 441 }
 442
 443 asmlinkage void plat_irq_dispatch(void)
 444 {
 445         unsigned int pending = read_c0_status() & read_c0_cause();
 446
 447         if (likely(pending & IE_IRQ0))
 448                 ip32_irq0();
 449         else if (unlikely(pending & IE_IRQ1))
 450                 ip32_irq1();
 451         else if (unlikely(pending & IE_IRQ2))
 452                 ip32_irq2();
 453         else if (unlikely(pending & IE_IRQ3))
 454                 ip32_irq3();
 455         else if (unlikely(pending & IE_IRQ4))
 456                 ip32_irq4();
 457         else if (likely(pending & IE_IRQ5))
 458                 ip32_irq5();
 459 }
 460
 461 void __init arch_init_irq(void)
 462 {
 463         unsigned int irq;
 464
 465         /* Install our interrupt handler, then clear and disable all
 466          * CRIME and MACE interrupts. */
 467         crime->imask = 0;
 468         crime->hard_int = 0;
 469         crime->soft_int = 0;
 470         mace->perif.ctrl.istat = 0;
 471         mace->perif.ctrl.imask = 0;
 472
 473         mips_cpu_irq_init();
 474         for (irq = MIPS_CPU_IRQ_BASE + 8; irq <= IP32_IRQ_MAX; irq++) {
 475                 struct irq_chip *chip;
 476
 477                 switch (irq) {
 478                 case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ:
 479                         chip = &ip32_mace_interrupt;
 480                         break;
 481                 case MACEPCI_SCSI0_IRQ ...  MACEPCI_SHARED2_IRQ:
 482                         chip = &ip32_macepci_interrupt;
 483                         break;
 484                 case CRIME_GBE0_IRQ ... CRIME_VICE_IRQ:
 485                         chip = &ip32_crime_interrupt;
 486                         break;
 487                 default:
 488                         chip = &ip32_maceisa_interrupt;
 489                 }
 490
 491                 set_irq_chip(irq, chip);
 492         }
 493         setup_irq(CRIME_MEMERR_IRQ, &memerr_irq);
 494         setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq);
 495
 496 #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
 497         change_c0_status(ST0_IM, ALLINTS);
 498 }