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cris: add arch/cris/include/asm/serial.h
[linux-2.6/next.git] / drivers / atm / firestream.c
blob5072f8ac16fdc13d072d4fea67843388f07c41d2
1
2 /* drivers/atm/firestream.c - FireStream 155 (MB86697) and
3 * FireStream 50 (MB86695) device driver
4 */
5
6 /* Written & (C) 2000 by R.E.Wolff@BitWizard.nl
7 * Copied snippets from zatm.c by Werner Almesberger, EPFL LRC/ICA
8 * and ambassador.c Copyright (C) 1995-1999 Madge Networks Ltd
9 */
10
11 /*
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
16
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25
26 The GNU GPL is contained in /usr/doc/copyright/GPL on a Debian
27 system and in the file COPYING in the Linux kernel source.
28 */
29
30
31 #include <linux/module.h>
32 #include <linux/sched.h>
33 #include <linux/kernel.h>
34 #include <linux/mm.h>
35 #include <linux/pci.h>
36 #include <linux/poison.h>
37 #include <linux/errno.h>
38 #include <linux/atm.h>
39 #include <linux/atmdev.h>
40 #include <linux/sonet.h>
41 #include <linux/skbuff.h>
42 #include <linux/netdevice.h>
43 #include <linux/delay.h>
44 #include <linux/ioport.h> /* for request_region */
45 #include <linux/uio.h>
46 #include <linux/init.h>
47 #include <linux/interrupt.h>
48 #include <linux/capability.h>
49 #include <linux/bitops.h>
50 #include <linux/slab.h>
51 #include <asm/byteorder.h>
52 #include <asm/system.h>
53 #include <asm/string.h>
54 #include <asm/io.h>
55 #include <linux/atomic.h>
56 #include <asm/uaccess.h>
57 #include <linux/wait.h>
58
59 #include "firestream.h"
60
61 static int loopback = 0;
62 static int num=0x5a;
63
64 /* According to measurements (but they look suspicious to me!) done in
65 * '97, 37% of the packets are one cell in size. So it pays to have
66 * buffers allocated at that size. A large jump in percentage of
67 * packets occurs at packets around 536 bytes in length. So it also
68 * pays to have those pre-allocated. Unfortunately, we can't fully
69 * take advantage of this as the majority of the packets is likely to
70 * be TCP/IP (As where obviously the measurement comes from) There the
71 * link would be opened with say a 1500 byte MTU, and we can't handle
72 * smaller buffers more efficiently than the larger ones. -- REW
73 */
74
75 /* Due to the way Linux memory management works, specifying "576" as
76 * an allocation size here isn't going to help. They are allocated
77 * from 1024-byte regions anyway. With the size of the sk_buffs (quite
78 * large), it doesn't pay to allocate the smallest size (64) -- REW */
79
80 /* This is all guesswork. Hard numbers to back this up or disprove this,
81 * are appreciated. -- REW */
82
83 /* The last entry should be about 64k. However, the "buffer size" is
84 * passed to the chip in a 16 bit field. I don't know how "65536"
85 * would be interpreted. -- REW */
86
87 #define NP FS_NR_FREE_POOLS
88 static int rx_buf_sizes[NP] = {128, 256, 512, 1024, 2048, 4096, 16384, 65520};
89 /* log2: 7 8 9 10 11 12 14 16 */
90
91 #if 0
92 static int rx_pool_sizes[NP] = {1024, 1024, 512, 256, 128, 64, 32, 32};
93 #else
94 /* debug */
95 static int rx_pool_sizes[NP] = {128, 128, 128, 64, 64, 64, 32, 32};
96 #endif
97 /* log2: 10 10 9 8 7 6 5 5 */
98 /* sumlog2: 17 18 18 18 18 18 19 21 */
99 /* mem allocated: 128k 256k 256k 256k 256k 256k 512k 2M */
100 /* tot mem: almost 4M */
101
102 /* NP is shorter, so that it fits on a single line. */
103 #undef NP
104
105
106 /* Small hardware gotcha:
107
108 The FS50 CAM (VP/VC match registers) always take the lowest channel
109 number that matches. This is not a problem.
110
111 However, they also ignore whether the channel is enabled or
112 not. This means that if you allocate channel 0 to 1.2 and then
113 channel 1 to 0.0, then disabeling channel 0 and writing 0 to the
114 match channel for channel 0 will "steal" the traffic from channel
115 1, even if you correctly disable channel 0.
116
117 Workaround:
118
119 - When disabling channels, write an invalid VP/VC value to the
120 match register. (We use 0xffffffff, which in the worst case
121 matches VP/VC = <maxVP>/<maxVC>, but I expect it not to match
122 anything as some "when not in use, program to 0" bits are now
123 programmed to 1...)
124
125 - Don't initialize the match registers to 0, as 0.0 is a valid
126 channel.
127 */
128
129
130 /* Optimization hints and tips.
131
132 The FireStream chips are very capable of reducing the amount of
133 "interrupt-traffic" for the CPU. This driver requests an interrupt on EVERY
134 action. You could try to minimize this a bit.
135
136 Besides that, the userspace->kernel copy and the PCI bus are the
137 performance limiting issues for this driver.
138
139 You could queue up a bunch of outgoing packets without telling the
140 FireStream. I'm not sure that's going to win you much though. The
141 Linux layer won't tell us in advance when it's not going to give us
142 any more packets in a while. So this is tricky to implement right without
143 introducing extra delays.
144
145 -- REW
146 */
147
148
149
150
151 /* The strings that define what the RX queue entry is all about. */
152 /* Fujitsu: Please tell me which ones can have a pointer to a
153 freepool descriptor! */
154 static char *res_strings[] = {
155 "RX OK: streaming not EOP",
156 "RX OK: streaming EOP",
157 "RX OK: Single buffer packet",
158 "RX OK: packet mode",
159 "RX OK: F4 OAM (end to end)",
160 "RX OK: F4 OAM (Segment)",
161 "RX OK: F5 OAM (end to end)",
162 "RX OK: F5 OAM (Segment)",
163 "RX OK: RM cell",
164 "RX OK: TRANSP cell",
165 "RX OK: TRANSPC cell",
166 "Unmatched cell",
167 "reserved 12",
168 "reserved 13",
169 "reserved 14",
170 "Unrecognized cell",
171 "reserved 16",
172 "reassemby abort: AAL5 abort",
173 "packet purged",
174 "packet ageing timeout",
175 "channel ageing timeout",
176 "calculated length error",
177 "programmed length limit error",
178 "aal5 crc32 error",
179 "oam transp or transpc crc10 error",
180 "reserved 25",
181 "reserved 26",
182 "reserved 27",
183 "reserved 28",
184 "reserved 29",
185 "reserved 30",
186 "reassembly abort: no buffers",
187 "receive buffer overflow",
188 "change in GFC",
189 "receive buffer full",
190 "low priority discard - no receive descriptor",
191 "low priority discard - missing end of packet",
192 "reserved 41",
193 "reserved 42",
194 "reserved 43",
195 "reserved 44",
196 "reserved 45",
197 "reserved 46",
198 "reserved 47",
199 "reserved 48",
200 "reserved 49",
201 "reserved 50",
202 "reserved 51",
203 "reserved 52",
204 "reserved 53",
205 "reserved 54",
206 "reserved 55",
207 "reserved 56",
208 "reserved 57",
209 "reserved 58",
210 "reserved 59",
211 "reserved 60",
212 "reserved 61",
213 "reserved 62",
214 "reserved 63",
215 };
216
217 static char *irq_bitname[] = {
218 "LPCO",
219 "DPCO",
220 "RBRQ0_W",
221 "RBRQ1_W",
222 "RBRQ2_W",
223 "RBRQ3_W",
224 "RBRQ0_NF",
225 "RBRQ1_NF",
226 "RBRQ2_NF",
227 "RBRQ3_NF",
228 "BFP_SC",
229 "INIT",
230 "INIT_ERR",
231 "USCEO",
232 "UPEC0",
233 "VPFCO",
234 "CRCCO",
235 "HECO",
236 "TBRQ_W",
237 "TBRQ_NF",
238 "CTPQ_E",
239 "GFC_C0",
240 "PCI_FTL",
241 "CSQ_W",
242 "CSQ_NF",
243 "EXT_INT",
244 "RXDMA_S"
245 };
246
247
248 #define PHY_EOF -1
249 #define PHY_CLEARALL -2
250
251 struct reginit_item {
252 int reg, val;
253 };
254
255
256 static struct reginit_item PHY_NTC_INIT[] __devinitdata = {
257 { PHY_CLEARALL, 0x40 },
258 { 0x12, 0x0001 },
259 { 0x13, 0x7605 },
260 { 0x1A, 0x0001 },
261 { 0x1B, 0x0005 },
262 { 0x38, 0x0003 },
263 { 0x39, 0x0006 }, /* changed here to make loopback */
264 { 0x01, 0x5262 },
265 { 0x15, 0x0213 },
266 { 0x00, 0x0003 },
267 { PHY_EOF, 0}, /* -1 signals end of list */
268 };
269
270
271 /* Safetyfeature: If the card interrupts more than this number of times
272 in a jiffy (1/100th of a second) then we just disable the interrupt and
273 print a message. This prevents the system from hanging.
274
275 150000 packets per second is close to the limit a PC is going to have
276 anyway. We therefore have to disable this for production. -- REW */
277 #undef IRQ_RATE_LIMIT // 100
278
279 /* Interrupts work now. Unlike serial cards, ATM cards don't work all
280 that great without interrupts. -- REW */
281 #undef FS_POLL_FREQ // 100
282
283 /*
284 This driver can spew a whole lot of debugging output at you. If you
285 need maximum performance, you should disable the DEBUG define. To
286 aid in debugging in the field, I'm leaving the compile-time debug
287 features enabled, and disable them "runtime". That allows me to
288 instruct people with problems to enable debugging without requiring
289 them to recompile... -- REW
290 */
291 #define DEBUG
292
293 #ifdef DEBUG
294 #define fs_dprintk(f, str...) if (fs_debug & f) printk (str)
295 #else
296 #define fs_dprintk(f, str...) /* nothing */
297 #endif
298
299
300 static int fs_keystream = 0;
301
302 #ifdef DEBUG
303 /* I didn't forget to set this to zero before shipping. Hit me with a stick
304 if you get this with the debug default not set to zero again. -- REW */
305 static int fs_debug = 0;
306 #else
307 #define fs_debug 0
308 #endif
309
310 #ifdef MODULE
311 #ifdef DEBUG
312 module_param(fs_debug, int, 0644);
313 #endif
314 module_param(loopback, int, 0);
315 module_param(num, int, 0);
316 module_param(fs_keystream, int, 0);
317 /* XXX Add rx_buf_sizes, and rx_pool_sizes As per request Amar. -- REW */
318 #endif
319
320
321 #define FS_DEBUG_FLOW 0x00000001
322 #define FS_DEBUG_OPEN 0x00000002
323 #define FS_DEBUG_QUEUE 0x00000004
324 #define FS_DEBUG_IRQ 0x00000008
325 #define FS_DEBUG_INIT 0x00000010
326 #define FS_DEBUG_SEND 0x00000020
327 #define FS_DEBUG_PHY 0x00000040
328 #define FS_DEBUG_CLEANUP 0x00000080
329 #define FS_DEBUG_QOS 0x00000100
330 #define FS_DEBUG_TXQ 0x00000200
331 #define FS_DEBUG_ALLOC 0x00000400
332 #define FS_DEBUG_TXMEM 0x00000800
333 #define FS_DEBUG_QSIZE 0x00001000
334
335
336 #define func_enter() fs_dprintk(FS_DEBUG_FLOW, "fs: enter %s\n", __func__)
337 #define func_exit() fs_dprintk(FS_DEBUG_FLOW, "fs: exit %s\n", __func__)
338
339
340 static struct fs_dev *fs_boards = NULL;
341
342 #ifdef DEBUG
343
344 static void my_hd (void *addr, int len)
345 {
346 int j, ch;
347 unsigned char *ptr = addr;
348
349 while (len > 0) {
350 printk ("%p ", ptr);
351 for (j=0;j < ((len < 16)?len:16);j++) {
352 printk ("%02x %s", ptr[j], (j==7)?" ":"");
353 }
354 for ( ;j < 16;j++) {
355 printk (" %s", (j==7)?" ":"");
356 }
357 for (j=0;j < ((len < 16)?len:16);j++) {
358 ch = ptr[j];
359 printk ("%c", (ch < 0x20)?'.':((ch > 0x7f)?'.':ch));
360 }
361 printk ("\n");
362 ptr += 16;
363 len -= 16;
364 }
365 }
366 #else /* DEBUG */
367 static void my_hd (void *addr, int len){}
368 #endif /* DEBUG */
369
370 /********** free an skb (as per ATM device driver documentation) **********/
371
372 /* Hmm. If this is ATM specific, why isn't there an ATM routine for this?
373 * I copied it over from the ambassador driver. -- REW */
374
375 static inline void fs_kfree_skb (struct sk_buff * skb)
376 {
377 if (ATM_SKB(skb)->vcc->pop)
378 ATM_SKB(skb)->vcc->pop (ATM_SKB(skb)->vcc, skb);
379 else
380 dev_kfree_skb_any (skb);
381 }
382
383
384
385
386 /* It seems the ATM forum recommends this horribly complicated 16bit
387 * floating point format. Turns out the Ambassador uses the exact same
388 * encoding. I just copied it over. If Mitch agrees, I'll move it over
389 * to the atm_misc file or something like that. (and remove it from
390 * here and the ambassador driver) -- REW
391 */
392
393 /* The good thing about this format is that it is monotonic. So,
394 a conversion routine need not be very complicated. To be able to
395 round "nearest" we need to take along a few extra bits. Lets
396 put these after 16 bits, so that we can just return the top 16
397 bits of the 32bit number as the result:
398
399 int mr (unsigned int rate, int r)
400 {
401 int e = 16+9;
402 static int round[4]={0, 0, 0xffff, 0x8000};
403 if (!rate) return 0;
404 while (rate & 0xfc000000) {
405 rate >>= 1;
406 e++;
407 }
408 while (! (rate & 0xfe000000)) {
409 rate <<= 1;
410 e--;
411 }
412
413 // Now the mantissa is in positions bit 16-25. Excepf for the "hidden 1" that's in bit 26.
414 rate &= ~0x02000000;
415 // Next add in the exponent
416 rate |= e << (16+9);
417 // And perform the rounding:
418 return (rate + round[r]) >> 16;
419 }
420
421 14 lines-of-code. Compare that with the 120 that the Ambassador
422 guys needed. (would be 8 lines shorter if I'd try to really reduce
423 the number of lines:
424
425 int mr (unsigned int rate, int r)
426 {
427 int e = 16+9;
428 static int round[4]={0, 0, 0xffff, 0x8000};
429 if (!rate) return 0;
430 for (; rate & 0xfc000000 ;rate >>= 1, e++);
431 for (;!(rate & 0xfe000000);rate <<= 1, e--);
432 return ((rate & ~0x02000000) | (e << (16+9)) + round[r]) >> 16;
433 }
434
435 Exercise for the reader: Remove one more line-of-code, without
436 cheating. (Just joining two lines is cheating). (I know it's
437 possible, don't think you've beat me if you found it... If you
438 manage to lose two lines or more, keep me updated! ;-)
439
440 -- REW */
441
442
443 #define ROUND_UP 1
444 #define ROUND_DOWN 2
445 #define ROUND_NEAREST 3
446 /********** make rate (not quite as much fun as Horizon) **********/
447
448 static int make_rate(unsigned int rate, int r,
449 u16 *bits, unsigned int *actual)
450 {
451 unsigned char exp = -1; /* hush gcc */
452 unsigned int man = -1; /* hush gcc */
453
454 fs_dprintk (FS_DEBUG_QOS, "make_rate %u", rate);
455
456 /* rates in cells per second, ITU format (nasty 16-bit floating-point)
457 given 5-bit e and 9-bit m:
458 rate = EITHER (1+m/2^9)*2^e OR 0
459 bits = EITHER 1<<14 | e<<9 | m OR 0
460 (bit 15 is "reserved", bit 14 "non-zero")
461 smallest rate is 0 (special representation)
462 largest rate is (1+511/512)*2^31 = 4290772992 (< 2^32-1)
463 smallest non-zero rate is (1+0/512)*2^0 = 1 (> 0)
464 simple algorithm:
465 find position of top bit, this gives e
466 remove top bit and shift (rounding if feeling clever) by 9-e
467 */
468 /* Ambassador ucode bug: please don't set bit 14! so 0 rate not
469 representable. // This should move into the ambassador driver
470 when properly merged. -- REW */
471
472 if (rate > 0xffc00000U) {
473 /* larger than largest representable rate */
474
475 if (r == ROUND_UP) {
476 return -EINVAL;
477 } else {
478 exp = 31;
479 man = 511;
480 }
481
482 } else if (rate) {
483 /* representable rate */
484
485 exp = 31;
486 man = rate;
487
488 /* invariant: rate = man*2^(exp-31) */
489 while (!(man & (1<<31))) {
490 exp = exp - 1;
491 man = man<<1;
492 }
493
494 /* man has top bit set
495 rate = (2^31+(man-2^31))*2^(exp-31)
496 rate = (1+(man-2^31)/2^31)*2^exp
497 */
498 man = man<<1;
499 man &= 0xffffffffU; /* a nop on 32-bit systems */
500 /* rate = (1+man/2^32)*2^exp
501
502 exp is in the range 0 to 31, man is in the range 0 to 2^32-1
503 time to lose significance... we want m in the range 0 to 2^9-1
504 rounding presents a minor problem... we first decide which way
505 we are rounding (based on given rounding direction and possibly
506 the bits of the mantissa that are to be discarded).
507 */
508
509 switch (r) {
510 case ROUND_DOWN: {
511 /* just truncate */
512 man = man>>(32-9);
513 break;
514 }
515 case ROUND_UP: {
516 /* check all bits that we are discarding */
517 if (man & (~0U>>9)) {
518 man = (man>>(32-9)) + 1;
519 if (man == (1<<9)) {
520 /* no need to check for round up outside of range */
521 man = 0;
522 exp += 1;
523 }
524 } else {
525 man = (man>>(32-9));
526 }
527 break;
528 }
529 case ROUND_NEAREST: {
530 /* check msb that we are discarding */
531 if (man & (1<<(32-9-1))) {
532 man = (man>>(32-9)) + 1;
533 if (man == (1<<9)) {
534 /* no need to check for round up outside of range */
535 man = 0;
536 exp += 1;
537 }
538 } else {
539 man = (man>>(32-9));
540 }
541 break;
542 }
543 }
544
545 } else {
546 /* zero rate - not representable */
547
548 if (r == ROUND_DOWN) {
549 return -EINVAL;
550 } else {
551 exp = 0;
552 man = 0;
553 }
554 }
555
556 fs_dprintk (FS_DEBUG_QOS, "rate: man=%u, exp=%hu", man, exp);
557
558 if (bits)
559 *bits = /* (1<<14) | */ (exp<<9) | man;
560
561 if (actual)
562 *actual = (exp >= 9)
563 ? (1 << exp) + (man << (exp-9))
564 : (1 << exp) + ((man + (1<<(9-exp-1))) >> (9-exp));
565
566 return 0;
567 }
568
569
570
571
572 /* FireStream access routines */
573 /* For DEEP-DOWN debugging these can be rigged to intercept accesses to
574 certain registers or to just log all accesses. */
575
576 static inline void write_fs (struct fs_dev *dev, int offset, u32 val)
577 {
578 writel (val, dev->base + offset);
579 }
580
581
582 static inline u32 read_fs (struct fs_dev *dev, int offset)
583 {
584 return readl (dev->base + offset);
585 }
586
587
588
589 static inline struct FS_QENTRY *get_qentry (struct fs_dev *dev, struct queue *q)
590 {
591 return bus_to_virt (read_fs (dev, Q_WP(q->offset)) & Q_ADDR_MASK);
592 }
593
594
595 static void submit_qentry (struct fs_dev *dev, struct queue *q, struct FS_QENTRY *qe)
596 {
597 u32 wp;
598 struct FS_QENTRY *cqe;
599
600 /* XXX Sanity check: the write pointer can be checked to be
601 still the same as the value passed as qe... -- REW */
602 /* udelay (5); */
603 while ((wp = read_fs (dev, Q_WP (q->offset))) & Q_FULL) {
604 fs_dprintk (FS_DEBUG_TXQ, "Found queue at %x full. Waiting.\n",
605 q->offset);
606 schedule ();
607 }
608
609 wp &= ~0xf;
610 cqe = bus_to_virt (wp);
611 if (qe != cqe) {
612 fs_dprintk (FS_DEBUG_TXQ, "q mismatch! %p %p\n", qe, cqe);
613 }
614
615 write_fs (dev, Q_WP(q->offset), Q_INCWRAP);
616
617 {
618 static int c;
619 if (!(c++ % 100))
620 {
621 int rp, wp;
622 rp = read_fs (dev, Q_RP(q->offset));
623 wp = read_fs (dev, Q_WP(q->offset));
624 fs_dprintk (FS_DEBUG_TXQ, "q at %d: %x-%x: %x entries.\n",
625 q->offset, rp, wp, wp-rp);
626 }
627 }
628 }
629
630 #ifdef DEBUG_EXTRA
631 static struct FS_QENTRY pq[60];
632 static int qp;
633
634 static struct FS_BPENTRY dq[60];
635 static int qd;
636 static void *da[60];
637 #endif
638
639 static void submit_queue (struct fs_dev *dev, struct queue *q,
640 u32 cmd, u32 p1, u32 p2, u32 p3)
641 {
642 struct FS_QENTRY *qe;
643
644 qe = get_qentry (dev, q);
645 qe->cmd = cmd;
646 qe->p0 = p1;
647 qe->p1 = p2;
648 qe->p2 = p3;
649 submit_qentry (dev, q, qe);
650
651 #ifdef DEBUG_EXTRA
652 pq[qp].cmd = cmd;
653 pq[qp].p0 = p1;
654 pq[qp].p1 = p2;
655 pq[qp].p2 = p3;
656 qp++;
657 if (qp >= 60) qp = 0;
658 #endif
659 }
660
661 /* Test the "other" way one day... -- REW */
662 #if 1
663 #define submit_command submit_queue
664 #else
665
666 static void submit_command (struct fs_dev *dev, struct queue *q,
667 u32 cmd, u32 p1, u32 p2, u32 p3)
668 {
669 write_fs (dev, CMDR0, cmd);
670 write_fs (dev, CMDR1, p1);
671 write_fs (dev, CMDR2, p2);
672 write_fs (dev, CMDR3, p3);
673 }
674 #endif
675
676
677
678 static void process_return_queue (struct fs_dev *dev, struct queue *q)
679 {
680 long rq;
681 struct FS_QENTRY *qe;
682 void *tc;
683
684 while (!((rq = read_fs (dev, Q_RP(q->offset))) & Q_EMPTY)) {
685 fs_dprintk (FS_DEBUG_QUEUE, "reaping return queue entry at %lx\n", rq);
686 qe = bus_to_virt (rq);
687
688 fs_dprintk (FS_DEBUG_QUEUE, "queue entry: %08x %08x %08x %08x. (%d)\n",
689 qe->cmd, qe->p0, qe->p1, qe->p2, STATUS_CODE (qe));
690
691 switch (STATUS_CODE (qe)) {
692 case 5:
693 tc = bus_to_virt (qe->p0);
694 fs_dprintk (FS_DEBUG_ALLOC, "Free tc: %p\n", tc);
695 kfree (tc);
696 break;
697 }
698
699 write_fs (dev, Q_RP(q->offset), Q_INCWRAP);
700 }
701 }
702
703
704 static void process_txdone_queue (struct fs_dev *dev, struct queue *q)
705 {
706 long rq;
707 long tmp;
708 struct FS_QENTRY *qe;
709 struct sk_buff *skb;
710 struct FS_BPENTRY *td;
711
712 while (!((rq = read_fs (dev, Q_RP(q->offset))) & Q_EMPTY)) {
713 fs_dprintk (FS_DEBUG_QUEUE, "reaping txdone entry at %lx\n", rq);
714 qe = bus_to_virt (rq);
715
716 fs_dprintk (FS_DEBUG_QUEUE, "queue entry: %08x %08x %08x %08x: %d\n",
717 qe->cmd, qe->p0, qe->p1, qe->p2, STATUS_CODE (qe));
718
719 if (STATUS_CODE (qe) != 2)
720 fs_dprintk (FS_DEBUG_TXMEM, "queue entry: %08x %08x %08x %08x: %d\n",
721 qe->cmd, qe->p0, qe->p1, qe->p2, STATUS_CODE (qe));
722
723
724 switch (STATUS_CODE (qe)) {
725 case 0x01: /* This is for AAL0 where we put the chip in streaming mode */
726 /* Fall through */
727 case 0x02:
728 /* Process a real txdone entry. */
729 tmp = qe->p0;
730 if (tmp & 0x0f)
731 printk (KERN_WARNING "td not aligned: %ld\n", tmp);
732 tmp &= ~0x0f;
733 td = bus_to_virt (tmp);
734
735 fs_dprintk (FS_DEBUG_QUEUE, "Pool entry: %08x %08x %08x %08x %p.\n",
736 td->flags, td->next, td->bsa, td->aal_bufsize, td->skb );
737
738 skb = td->skb;
739 if (skb == FS_VCC (ATM_SKB(skb)->vcc)->last_skb) {
740 wake_up_interruptible (& FS_VCC (ATM_SKB(skb)->vcc)->close_wait);
741 FS_VCC (ATM_SKB(skb)->vcc)->last_skb = NULL;
742 }
743 td->dev->ntxpckts--;
744
745 {
746 static int c=0;
747
748 if (!(c++ % 100)) {
749 fs_dprintk (FS_DEBUG_QSIZE, "[%d]", td->dev->ntxpckts);
750 }
751 }
752
753 atomic_inc(&ATM_SKB(skb)->vcc->stats->tx);
754
755 fs_dprintk (FS_DEBUG_TXMEM, "i");
756 fs_dprintk (FS_DEBUG_ALLOC, "Free t-skb: %p\n", skb);
757 fs_kfree_skb (skb);
758
759 fs_dprintk (FS_DEBUG_ALLOC, "Free trans-d: %p\n", td);
760 memset (td, ATM_POISON_FREE, sizeof(struct FS_BPENTRY));
761 kfree (td);
762 break;
763 default:
764 /* Here we get the tx purge inhibit command ... */
765 /* Action, I believe, is "don't do anything". -- REW */
766 ;
767 }
768
769 write_fs (dev, Q_RP(q->offset), Q_INCWRAP);
770 }
771 }
772
773
774 static void process_incoming (struct fs_dev *dev, struct queue *q)
775 {
776 long rq;
777 struct FS_QENTRY *qe;
778 struct FS_BPENTRY *pe;
779 struct sk_buff *skb;
780 unsigned int channo;
781 struct atm_vcc *atm_vcc;
782
783 while (!((rq = read_fs (dev, Q_RP(q->offset))) & Q_EMPTY)) {
784 fs_dprintk (FS_DEBUG_QUEUE, "reaping incoming queue entry at %lx\n", rq);
785 qe = bus_to_virt (rq);
786
787 fs_dprintk (FS_DEBUG_QUEUE, "queue entry: %08x %08x %08x %08x. ",
788 qe->cmd, qe->p0, qe->p1, qe->p2);
789
790 fs_dprintk (FS_DEBUG_QUEUE, "-> %x: %s\n",
791 STATUS_CODE (qe),
792 res_strings[STATUS_CODE(qe)]);
793
794 pe = bus_to_virt (qe->p0);
795 fs_dprintk (FS_DEBUG_QUEUE, "Pool entry: %08x %08x %08x %08x %p %p.\n",
796 pe->flags, pe->next, pe->bsa, pe->aal_bufsize,
797 pe->skb, pe->fp);
798
799 channo = qe->cmd & 0xffff;
800
801 if (channo < dev->nchannels)
802 atm_vcc = dev->atm_vccs[channo];
803 else
804 atm_vcc = NULL;
805
806 /* Single buffer packet */
807 switch (STATUS_CODE (qe)) {
808 case 0x1:
809 /* Fall through for streaming mode */
810 case 0x2:/* Packet received OK.... */
811 if (atm_vcc) {
812 skb = pe->skb;
813 pe->fp->n--;
814 #if 0
815 fs_dprintk (FS_DEBUG_QUEUE, "Got skb: %p\n", skb);
816 if (FS_DEBUG_QUEUE & fs_debug) my_hd (bus_to_virt (pe->bsa), 0x20);
817 #endif
818 skb_put (skb, qe->p1 & 0xffff);
819 ATM_SKB(skb)->vcc = atm_vcc;
820 atomic_inc(&atm_vcc->stats->rx);
821 __net_timestamp(skb);
822 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-skb: %p (pushed)\n", skb);
823 atm_vcc->push (atm_vcc, skb);
824 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-d: %p\n", pe);
825 kfree (pe);
826 } else {
827 printk (KERN_ERR "Got a receive on a non-open channel %d.\n", channo);
828 }
829 break;
830 case 0x17:/* AAL 5 CRC32 error. IFF the length field is nonzero, a buffer
831 has been consumed and needs to be processed. -- REW */
832 if (qe->p1 & 0xffff) {
833 pe = bus_to_virt (qe->p0);
834 pe->fp->n--;
835 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-skb: %p\n", pe->skb);
836 dev_kfree_skb_any (pe->skb);
837 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-d: %p\n", pe);
838 kfree (pe);
839 }
840 if (atm_vcc)
841 atomic_inc(&atm_vcc->stats->rx_drop);
842 break;
843 case 0x1f: /* Reassembly abort: no buffers. */
844 /* Silently increment error counter. */
845 if (atm_vcc)
846 atomic_inc(&atm_vcc->stats->rx_drop);
847 break;
848 default: /* Hmm. Haven't written the code to handle the others yet... -- REW */
849 printk (KERN_WARNING "Don't know what to do with RX status %x: %s.\n",
850 STATUS_CODE(qe), res_strings[STATUS_CODE (qe)]);
851 }
852 write_fs (dev, Q_RP(q->offset), Q_INCWRAP);
853 }
854 }
855
856
857
858 #define DO_DIRECTION(tp) ((tp)->traffic_class != ATM_NONE)
859
860 static int fs_open(struct atm_vcc *atm_vcc)
861 {
862 struct fs_dev *dev;
863 struct fs_vcc *vcc;
864 struct fs_transmit_config *tc;
865 struct atm_trafprm * txtp;
866 struct atm_trafprm * rxtp;
867 /* struct fs_receive_config *rc;*/
868 /* struct FS_QENTRY *qe; */
869 int error;
870 int bfp;
871 int to;
872 unsigned short tmc0;
873 short vpi = atm_vcc->vpi;
874 int vci = atm_vcc->vci;
875
876 func_enter ();
877
878 dev = FS_DEV(atm_vcc->dev);
879 fs_dprintk (FS_DEBUG_OPEN, "fs: open on dev: %p, vcc at %p\n",
880 dev, atm_vcc);
881
882 if (vci != ATM_VPI_UNSPEC && vpi != ATM_VCI_UNSPEC)
883 set_bit(ATM_VF_ADDR, &atm_vcc->flags);
884
885 if ((atm_vcc->qos.aal != ATM_AAL5) &&
886 (atm_vcc->qos.aal != ATM_AAL2))
887 return -EINVAL; /* XXX AAL0 */
888
889 fs_dprintk (FS_DEBUG_OPEN, "fs: (itf %d): open %d.%d\n",
890 atm_vcc->dev->number, atm_vcc->vpi, atm_vcc->vci);
891
892 /* XXX handle qos parameters (rate limiting) ? */
893
894 vcc = kmalloc(sizeof(struct fs_vcc), GFP_KERNEL);
895 fs_dprintk (FS_DEBUG_ALLOC, "Alloc VCC: %p(%Zd)\n", vcc, sizeof(struct fs_vcc));
896 if (!vcc) {
897 clear_bit(ATM_VF_ADDR, &atm_vcc->flags);
898 return -ENOMEM;
899 }
900
901 atm_vcc->dev_data = vcc;
902 vcc->last_skb = NULL;
903
904 init_waitqueue_head (&vcc->close_wait);
905
906 txtp = &atm_vcc->qos.txtp;
907 rxtp = &atm_vcc->qos.rxtp;
908
909 if (!test_bit(ATM_VF_PARTIAL, &atm_vcc->flags)) {
910 if (IS_FS50(dev)) {
911 /* Increment the channel numer: take a free one next time. */
912 for (to=33;to;to--, dev->channo++) {
913 /* We only have 32 channels */
914 if (dev->channo >= 32)
915 dev->channo = 0;
916 /* If we need to do RX, AND the RX is inuse, try the next */
917 if (DO_DIRECTION(rxtp) && dev->atm_vccs[dev->channo])
918 continue;
919 /* If we need to do TX, AND the TX is inuse, try the next */
920 if (DO_DIRECTION(txtp) && test_bit (dev->channo, dev->tx_inuse))
921 continue;
922 /* Ok, both are free! (or not needed) */
923 break;
924 }
925 if (!to) {
926 printk ("No more free channels for FS50..\n");
927 return -EBUSY;
928 }
929 vcc->channo = dev->channo;
930 dev->channo &= dev->channel_mask;
931
932 } else {
933 vcc->channo = (vpi << FS155_VCI_BITS) | (vci);
934 if (((DO_DIRECTION(rxtp) && dev->atm_vccs[vcc->channo])) ||
935 ( DO_DIRECTION(txtp) && test_bit (vcc->channo, dev->tx_inuse))) {
936 printk ("Channel is in use for FS155.\n");
937 return -EBUSY;
938 }
939 }
940 fs_dprintk (FS_DEBUG_OPEN, "OK. Allocated channel %x(%d).\n",
941 vcc->channo, vcc->channo);
942 }
943
944 if (DO_DIRECTION (txtp)) {
945 tc = kmalloc (sizeof (struct fs_transmit_config), GFP_KERNEL);
946 fs_dprintk (FS_DEBUG_ALLOC, "Alloc tc: %p(%Zd)\n",
947 tc, sizeof (struct fs_transmit_config));
948 if (!tc) {
949 fs_dprintk (FS_DEBUG_OPEN, "fs: can't alloc transmit_config.\n");
950 return -ENOMEM;
951 }
952
953 /* Allocate the "open" entry from the high priority txq. This makes
954 it most likely that the chip will notice it. It also prevents us
955 from having to wait for completion. On the other hand, we may
956 need to wait for completion anyway, to see if it completed
957 successfully. */
958
959 switch (atm_vcc->qos.aal) {
960 case ATM_AAL2:
961 case ATM_AAL0:
962 tc->flags = 0
963 | TC_FLAGS_TRANSPARENT_PAYLOAD
964 | TC_FLAGS_PACKET
965 | (1 << 28)
966 | TC_FLAGS_TYPE_UBR /* XXX Change to VBR -- PVDL */
967 | TC_FLAGS_CAL0;
968 break;
969 case ATM_AAL5:
970 tc->flags = 0
971 | TC_FLAGS_AAL5
972 | TC_FLAGS_PACKET /* ??? */
973 | TC_FLAGS_TYPE_CBR
974 | TC_FLAGS_CAL0;
975 break;
976 default:
977 printk ("Unknown aal: %d\n", atm_vcc->qos.aal);
978 tc->flags = 0;
979 }
980 /* Docs are vague about this atm_hdr field. By the way, the FS
981 * chip makes odd errors if lower bits are set.... -- REW */
982 tc->atm_hdr = (vpi << 20) | (vci << 4);
983 tmc0 = 0;
984 {
985 int pcr = atm_pcr_goal (txtp);
986
987 fs_dprintk (FS_DEBUG_OPEN, "pcr = %d.\n", pcr);
988
989 /* XXX Hmm. officially we're only allowed to do this if rounding
990 is round_down -- REW */
991 if (IS_FS50(dev)) {
992 if (pcr > 51840000/53/8) pcr = 51840000/53/8;
993 } else {
994 if (pcr > 155520000/53/8) pcr = 155520000/53/8;
995 }
996 if (!pcr) {
997 /* no rate cap */
998 tmc0 = IS_FS50(dev)?0x61BE:0x64c9; /* Just copied over the bits from Fujitsu -- REW */
999 } else {
1000 int r;
1001 if (pcr < 0) {
1002 r = ROUND_DOWN;
1003 pcr = -pcr;
1004 } else {
1005 r = ROUND_UP;
1006 }
1007 error = make_rate (pcr, r, &tmc0, NULL);
1008 if (error) {
1009 kfree(tc);
1010 return error;
1011 }
1012 }
1013 fs_dprintk (FS_DEBUG_OPEN, "pcr = %d.\n", pcr);
1014 }
1015
1016 tc->TMC[0] = tmc0 | 0x4000;
1017 tc->TMC[1] = 0; /* Unused */
1018 tc->TMC[2] = 0; /* Unused */
1019 tc->TMC[3] = 0; /* Unused */
1020
1021 tc->spec = 0; /* UTOPIA address, UDF, HEC: Unused -> 0 */
1022 tc->rtag[0] = 0; /* What should I do with routing tags???
1023 -- Not used -- AS -- Thanks -- REW*/
1024 tc->rtag[1] = 0;
1025 tc->rtag[2] = 0;
1026
1027 if (fs_debug & FS_DEBUG_OPEN) {
1028 fs_dprintk (FS_DEBUG_OPEN, "TX config record:\n");
1029 my_hd (tc, sizeof (*tc));
1030 }
1031
1032 /* We now use the "submit_command" function to submit commands to
1033 the firestream. There is a define up near the definition of
1034 that routine that switches this routine between immediate write
1035 to the immediate command registers and queuing the commands in
1036 the HPTXQ for execution. This last technique might be more
1037 efficient if we know we're going to submit a whole lot of
1038 commands in one go, but this driver is not setup to be able to
1039 use such a construct. So it probably doen't matter much right
1040 now. -- REW */
1041
1042 /* The command is IMMediate and INQueue. The parameters are out-of-line.. */
1043 submit_command (dev, &dev->hp_txq,
1044 QE_CMD_CONFIG_TX | QE_CMD_IMM_INQ | vcc->channo,
1045 virt_to_bus (tc), 0, 0);
1046
1047 submit_command (dev, &dev->hp_txq,
1048 QE_CMD_TX_EN | QE_CMD_IMM_INQ | vcc->channo,
1049 0, 0, 0);
1050 set_bit (vcc->channo, dev->tx_inuse);
1051 }
1052
1053 if (DO_DIRECTION (rxtp)) {
1054 dev->atm_vccs[vcc->channo] = atm_vcc;
1055
1056 for (bfp = 0;bfp < FS_NR_FREE_POOLS; bfp++)
1057 if (atm_vcc->qos.rxtp.max_sdu <= dev->rx_fp[bfp].bufsize) break;
1058 if (bfp >= FS_NR_FREE_POOLS) {
1059 fs_dprintk (FS_DEBUG_OPEN, "No free pool fits sdu: %d.\n",
1060 atm_vcc->qos.rxtp.max_sdu);
1061 /* XXX Cleanup? -- Would just calling fs_close work??? -- REW */
1062
1063 /* XXX clear tx inuse. Close TX part? */
1064 dev->atm_vccs[vcc->channo] = NULL;
1065 kfree (vcc);
1066 return -EINVAL;
1067 }
1068
1069 switch (atm_vcc->qos.aal) {
1070 case ATM_AAL0:
1071 case ATM_AAL2:
1072 submit_command (dev, &dev->hp_txq,
1073 QE_CMD_CONFIG_RX | QE_CMD_IMM_INQ | vcc->channo,
1074 RC_FLAGS_TRANSP |
1075 RC_FLAGS_BFPS_BFP * bfp |
1076 RC_FLAGS_RXBM_PSB, 0, 0);
1077 break;
1078 case ATM_AAL5:
1079 submit_command (dev, &dev->hp_txq,
1080 QE_CMD_CONFIG_RX | QE_CMD_IMM_INQ | vcc->channo,
1081 RC_FLAGS_AAL5 |
1082 RC_FLAGS_BFPS_BFP * bfp |
1083 RC_FLAGS_RXBM_PSB, 0, 0);
1084 break;
1085 };
1086 if (IS_FS50 (dev)) {
1087 submit_command (dev, &dev->hp_txq,
1088 QE_CMD_REG_WR | QE_CMD_IMM_INQ,
1089 0x80 + vcc->channo,
1090 (vpi << 16) | vci, 0 ); /* XXX -- Use defines. */
1091 }
1092 submit_command (dev, &dev->hp_txq,
1093 QE_CMD_RX_EN | QE_CMD_IMM_INQ | vcc->channo,
1094 0, 0, 0);
1095 }
1096
1097 /* Indicate we're done! */
1098 set_bit(ATM_VF_READY, &atm_vcc->flags);
1099
1100 func_exit ();
1101 return 0;
1102 }
1103
1104
1105 static void fs_close(struct atm_vcc *atm_vcc)
1106 {
1107 struct fs_dev *dev = FS_DEV (atm_vcc->dev);
1108 struct fs_vcc *vcc = FS_VCC (atm_vcc);
1109 struct atm_trafprm * txtp;
1110 struct atm_trafprm * rxtp;
1111
1112 func_enter ();
1113
1114 clear_bit(ATM_VF_READY, &atm_vcc->flags);
1115
1116 fs_dprintk (FS_DEBUG_QSIZE, "--==**[%d]**==--", dev->ntxpckts);
1117 if (vcc->last_skb) {
1118 fs_dprintk (FS_DEBUG_QUEUE, "Waiting for skb %p to be sent.\n",
1119 vcc->last_skb);
1120 /* We're going to wait for the last packet to get sent on this VC. It would
1121 be impolite not to send them don't you think?
1122 XXX
1123 We don't know which packets didn't get sent. So if we get interrupted in
1124 this sleep_on, we'll lose any reference to these packets. Memory leak!
1125 On the other hand, it's awfully convenient that we can abort a "close" that
1126 is taking too long. Maybe just use non-interruptible sleep on? -- REW */
1127 interruptible_sleep_on (& vcc->close_wait);
1128 }
1129
1130 txtp = &atm_vcc->qos.txtp;
1131 rxtp = &atm_vcc->qos.rxtp;
1132
1133
1134 /* See App note XXX (Unpublished as of now) for the reason for the
1135 removal of the "CMD_IMM_INQ" part of the TX_PURGE_INH... -- REW */
1136
1137 if (DO_DIRECTION (txtp)) {
1138 submit_command (dev, &dev->hp_txq,
1139 QE_CMD_TX_PURGE_INH | /*QE_CMD_IMM_INQ|*/ vcc->channo, 0,0,0);
1140 clear_bit (vcc->channo, dev->tx_inuse);
1141 }
1142
1143 if (DO_DIRECTION (rxtp)) {
1144 submit_command (dev, &dev->hp_txq,
1145 QE_CMD_RX_PURGE_INH | QE_CMD_IMM_INQ | vcc->channo, 0,0,0);
1146 dev->atm_vccs [vcc->channo] = NULL;
1147
1148 /* This means that this is configured as a receive channel */
1149 if (IS_FS50 (dev)) {
1150 /* Disable the receive filter. Is 0/0 indeed an invalid receive
1151 channel? -- REW. Yes it is. -- Hang. Ok. I'll use -1
1152 (0xfff...) -- REW */
1153 submit_command (dev, &dev->hp_txq,
1154 QE_CMD_REG_WR | QE_CMD_IMM_INQ,
1155 0x80 + vcc->channo, -1, 0 );
1156 }
1157 }
1158
1159 fs_dprintk (FS_DEBUG_ALLOC, "Free vcc: %p\n", vcc);
1160 kfree (vcc);
1161
1162 func_exit ();
1163 }
1164
1165
1166 static int fs_send (struct atm_vcc *atm_vcc, struct sk_buff *skb)
1167 {
1168 struct fs_dev *dev = FS_DEV (atm_vcc->dev);
1169 struct fs_vcc *vcc = FS_VCC (atm_vcc);
1170 struct FS_BPENTRY *td;
1171
1172 func_enter ();
1173
1174 fs_dprintk (FS_DEBUG_TXMEM, "I");
1175 fs_dprintk (FS_DEBUG_SEND, "Send: atm_vcc %p skb %p vcc %p dev %p\n",
1176 atm_vcc, skb, vcc, dev);
1177
1178 fs_dprintk (FS_DEBUG_ALLOC, "Alloc t-skb: %p (atm_send)\n", skb);
1179
1180 ATM_SKB(skb)->vcc = atm_vcc;
1181
1182 vcc->last_skb = skb;
1183
1184 td = kmalloc (sizeof (struct FS_BPENTRY), GFP_ATOMIC);
1185 fs_dprintk (FS_DEBUG_ALLOC, "Alloc transd: %p(%Zd)\n", td, sizeof (struct FS_BPENTRY));
1186 if (!td) {
1187 /* Oops out of mem */
1188 return -ENOMEM;
1189 }
1190
1191 fs_dprintk (FS_DEBUG_SEND, "first word in buffer: %x\n",
1192 *(int *) skb->data);
1193
1194 td->flags = TD_EPI | TD_DATA | skb->len;
1195 td->next = 0;
1196 td->bsa = virt_to_bus (skb->data);
1197 td->skb = skb;
1198 td->dev = dev;
1199 dev->ntxpckts++;
1200
1201 #ifdef DEBUG_EXTRA
1202 da[qd] = td;
1203 dq[qd].flags = td->flags;
1204 dq[qd].next = td->next;
1205 dq[qd].bsa = td->bsa;
1206 dq[qd].skb = td->skb;
1207 dq[qd].dev = td->dev;
1208 qd++;
1209 if (qd >= 60) qd = 0;
1210 #endif
1211
1212 submit_queue (dev, &dev->hp_txq,
1213 QE_TRANSMIT_DE | vcc->channo,
1214 virt_to_bus (td), 0,
1215 virt_to_bus (td));
1216
1217 fs_dprintk (FS_DEBUG_QUEUE, "in send: txq %d txrq %d\n",
1218 read_fs (dev, Q_EA (dev->hp_txq.offset)) -
1219 read_fs (dev, Q_SA (dev->hp_txq.offset)),
1220 read_fs (dev, Q_EA (dev->tx_relq.offset)) -
1221 read_fs (dev, Q_SA (dev->tx_relq.offset)));
1222
1223 func_exit ();
1224 return 0;
1225 }
1226
1227
1228 /* Some function placeholders for functions we don't yet support. */
1229
1230 #if 0
1231 static int fs_ioctl(struct atm_dev *dev,unsigned int cmd,void __user *arg)
1232 {
1233 func_enter ();
1234 func_exit ();
1235 return -ENOIOCTLCMD;
1236 }
1237
1238
1239 static int fs_getsockopt(struct atm_vcc *vcc,int level,int optname,
1240 void __user *optval,int optlen)
1241 {
1242 func_enter ();
1243 func_exit ();
1244 return 0;
1245 }
1246
1247
1248 static int fs_setsockopt(struct atm_vcc *vcc,int level,int optname,
1249 void __user *optval,unsigned int optlen)
1250 {
1251 func_enter ();
1252 func_exit ();
1253 return 0;
1254 }
1255
1256
1257 static void fs_phy_put(struct atm_dev *dev,unsigned char value,
1258 unsigned long addr)
1259 {
1260 func_enter ();
1261 func_exit ();
1262 }
1263
1264
1265 static unsigned char fs_phy_get(struct atm_dev *dev,unsigned long addr)
1266 {
1267 func_enter ();
1268 func_exit ();
1269 return 0;
1270 }
1271
1272
1273 static int fs_change_qos(struct atm_vcc *vcc,struct atm_qos *qos,int flags)
1274 {
1275 func_enter ();
1276 func_exit ();
1277 return 0;
1278 };
1279
1280 #endif
1281
1282
1283 static const struct atmdev_ops ops = {
1284 .open = fs_open,
1285 .close = fs_close,
1286 .send = fs_send,
1287 .owner = THIS_MODULE,
1288 /* ioctl: fs_ioctl, */
1289 /* getsockopt: fs_getsockopt, */
1290 /* setsockopt: fs_setsockopt, */
1291 /* change_qos: fs_change_qos, */
1292
1293 /* For now implement these internally here... */
1294 /* phy_put: fs_phy_put, */
1295 /* phy_get: fs_phy_get, */
1296 };
1297
1298
1299 static void __devinit undocumented_pci_fix (struct pci_dev *pdev)
1300 {
1301 u32 tint;
1302
1303 /* The Windows driver says: */
1304 /* Switch off FireStream Retry Limit Threshold
1305 */
1306
1307 /* The register at 0x28 is documented as "reserved", no further
1308 comments. */
1309
1310 pci_read_config_dword (pdev, 0x28, &tint);
1311 if (tint != 0x80) {
1312 tint = 0x80;
1313 pci_write_config_dword (pdev, 0x28, tint);
1314 }
1315 }
1316
1317
1318
1319 /**************************************************************************
1320 * PHY routines *
1321 **************************************************************************/
1322
1323 static void __devinit write_phy (struct fs_dev *dev, int regnum, int val)
1324 {
1325 submit_command (dev, &dev->hp_txq, QE_CMD_PRP_WR | QE_CMD_IMM_INQ,
1326 regnum, val, 0);
1327 }
1328
1329 static int __devinit init_phy (struct fs_dev *dev, struct reginit_item *reginit)
1330 {
1331 int i;
1332
1333 func_enter ();
1334 while (reginit->reg != PHY_EOF) {
1335 if (reginit->reg == PHY_CLEARALL) {
1336 /* "PHY_CLEARALL means clear all registers. Numregisters is in "val". */
1337 for (i=0;i<reginit->val;i++) {
1338 write_phy (dev, i, 0);
1339 }
1340 } else {
1341 write_phy (dev, reginit->reg, reginit->val);
1342 }
1343 reginit++;
1344 }
1345 func_exit ();
1346 return 0;
1347 }
1348
1349 static void reset_chip (struct fs_dev *dev)
1350 {
1351 int i;
1352
1353 write_fs (dev, SARMODE0, SARMODE0_SRTS0);
1354
1355 /* Undocumented delay */
1356 udelay (128);
1357
1358 /* The "internal registers are documented to all reset to zero, but
1359 comments & code in the Windows driver indicates that the pools are
1360 NOT reset. */
1361 for (i=0;i < FS_NR_FREE_POOLS;i++) {
1362 write_fs (dev, FP_CNF (RXB_FP(i)), 0);
1363 write_fs (dev, FP_SA (RXB_FP(i)), 0);
1364 write_fs (dev, FP_EA (RXB_FP(i)), 0);
1365 write_fs (dev, FP_CNT (RXB_FP(i)), 0);
1366 write_fs (dev, FP_CTU (RXB_FP(i)), 0);
1367 }
1368
1369 /* The same goes for the match channel registers, although those are
1370 NOT documented that way in the Windows driver. -- REW */
1371 /* The Windows driver DOES write 0 to these registers somewhere in
1372 the init sequence. However, a small hardware-feature, will
1373 prevent reception of data on VPI/VCI = 0/0 (Unless the channel
1374 allocated happens to have no disabled channels that have a lower
1375 number. -- REW */
1376
1377 /* Clear the match channel registers. */
1378 if (IS_FS50 (dev)) {
1379 for (i=0;i<FS50_NR_CHANNELS;i++) {
1380 write_fs (dev, 0x200 + i * 4, -1);
1381 }
1382 }
1383 }
1384
1385 static void __devinit *aligned_kmalloc (int size, gfp_t flags, int alignment)
1386 {
1387 void *t;
1388
1389 if (alignment <= 0x10) {
1390 t = kmalloc (size, flags);
1391 if ((unsigned long)t & (alignment-1)) {
1392 printk ("Kmalloc doesn't align things correctly! %p\n", t);
1393 kfree (t);
1394 return aligned_kmalloc (size, flags, alignment * 4);
1395 }
1396 return t;
1397 }
1398 printk (KERN_ERR "Request for > 0x10 alignment not yet implemented (hard!)\n");
1399 return NULL;
1400 }
1401
1402 static int __devinit init_q (struct fs_dev *dev,
1403 struct queue *txq, int queue, int nentries, int is_rq)
1404 {
1405 int sz = nentries * sizeof (struct FS_QENTRY);
1406 struct FS_QENTRY *p;
1407
1408 func_enter ();
1409
1410 fs_dprintk (FS_DEBUG_INIT, "Inititing queue at %x: %d entries:\n",
1411 queue, nentries);
1412
1413 p = aligned_kmalloc (sz, GFP_KERNEL, 0x10);
1414 fs_dprintk (FS_DEBUG_ALLOC, "Alloc queue: %p(%d)\n", p, sz);
1415
1416 if (!p) return 0;
1417
1418 write_fs (dev, Q_SA(queue), virt_to_bus(p));
1419 write_fs (dev, Q_EA(queue), virt_to_bus(p+nentries-1));
1420 write_fs (dev, Q_WP(queue), virt_to_bus(p));
1421 write_fs (dev, Q_RP(queue), virt_to_bus(p));
1422 if (is_rq) {
1423 /* Configuration for the receive queue: 0: interrupt immediately,
1424 no pre-warning to empty queues: We do our best to keep the
1425 queue filled anyway. */
1426 write_fs (dev, Q_CNF(queue), 0 );
1427 }
1428
1429 txq->sa = p;
1430 txq->ea = p;
1431 txq->offset = queue;
1432
1433 func_exit ();
1434 return 1;
1435 }
1436
1437
1438 static int __devinit init_fp (struct fs_dev *dev,
1439 struct freepool *fp, int queue, int bufsize, int nr_buffers)
1440 {
1441 func_enter ();
1442
1443 fs_dprintk (FS_DEBUG_INIT, "Inititing free pool at %x:\n", queue);
1444
1445 write_fs (dev, FP_CNF(queue), (bufsize * RBFP_RBS) | RBFP_RBSVAL | RBFP_CME);
1446 write_fs (dev, FP_SA(queue), 0);
1447 write_fs (dev, FP_EA(queue), 0);
1448 write_fs (dev, FP_CTU(queue), 0);
1449 write_fs (dev, FP_CNT(queue), 0);
1450
1451 fp->offset = queue;
1452 fp->bufsize = bufsize;
1453 fp->nr_buffers = nr_buffers;
1454
1455 func_exit ();
1456 return 1;
1457 }
1458
1459
1460 static inline int nr_buffers_in_freepool (struct fs_dev *dev, struct freepool *fp)
1461 {
1462 #if 0
1463 /* This seems to be unreliable.... */
1464 return read_fs (dev, FP_CNT (fp->offset));
1465 #else
1466 return fp->n;
1467 #endif
1468 }
1469
1470
1471 /* Check if this gets going again if a pool ever runs out. -- Yes, it
1472 does. I've seen "receive abort: no buffers" and things started
1473 working again after that... -- REW */
1474
1475 static void top_off_fp (struct fs_dev *dev, struct freepool *fp,
1476 gfp_t gfp_flags)
1477 {
1478 struct FS_BPENTRY *qe, *ne;
1479 struct sk_buff *skb;
1480 int n = 0;
1481 u32 qe_tmp;
1482
1483 fs_dprintk (FS_DEBUG_QUEUE, "Topping off queue at %x (%d-%d/%d)\n",
1484 fp->offset, read_fs (dev, FP_CNT (fp->offset)), fp->n,
1485 fp->nr_buffers);
1486 while (nr_buffers_in_freepool(dev, fp) < fp->nr_buffers) {
1487
1488 skb = alloc_skb (fp->bufsize, gfp_flags);
1489 fs_dprintk (FS_DEBUG_ALLOC, "Alloc rec-skb: %p(%d)\n", skb, fp->bufsize);
1490 if (!skb) break;
1491 ne = kmalloc (sizeof (struct FS_BPENTRY), gfp_flags);
1492 fs_dprintk (FS_DEBUG_ALLOC, "Alloc rec-d: %p(%Zd)\n", ne, sizeof (struct FS_BPENTRY));
1493 if (!ne) {
1494 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-skb: %p\n", skb);
1495 dev_kfree_skb_any (skb);
1496 break;
1497 }
1498
1499 fs_dprintk (FS_DEBUG_QUEUE, "Adding skb %p desc %p -> %p(%p) ",
1500 skb, ne, skb->data, skb->head);
1501 n++;
1502 ne->flags = FP_FLAGS_EPI | fp->bufsize;
1503 ne->next = virt_to_bus (NULL);
1504 ne->bsa = virt_to_bus (skb->data);
1505 ne->aal_bufsize = fp->bufsize;
1506 ne->skb = skb;
1507 ne->fp = fp;
1508
1509 /*
1510 * FIXME: following code encodes and decodes
1511 * machine pointers (could be 64-bit) into a
1512 * 32-bit register.
1513 */
1514
1515 qe_tmp = read_fs (dev, FP_EA(fp->offset));
1516 fs_dprintk (FS_DEBUG_QUEUE, "link at %x\n", qe_tmp);
1517 if (qe_tmp) {
1518 qe = bus_to_virt ((long) qe_tmp);
1519 qe->next = virt_to_bus(ne);
1520 qe->flags &= ~FP_FLAGS_EPI;
1521 } else
1522 write_fs (dev, FP_SA(fp->offset), virt_to_bus(ne));
1523
1524 write_fs (dev, FP_EA(fp->offset), virt_to_bus (ne));
1525 fp->n++; /* XXX Atomic_inc? */
1526 write_fs (dev, FP_CTU(fp->offset), 1);
1527 }
1528
1529 fs_dprintk (FS_DEBUG_QUEUE, "Added %d entries. \n", n);
1530 }
1531
1532 static void __devexit free_queue (struct fs_dev *dev, struct queue *txq)
1533 {
1534 func_enter ();
1535
1536 write_fs (dev, Q_SA(txq->offset), 0);
1537 write_fs (dev, Q_EA(txq->offset), 0);
1538 write_fs (dev, Q_RP(txq->offset), 0);
1539 write_fs (dev, Q_WP(txq->offset), 0);
1540 /* Configuration ? */
1541
1542 fs_dprintk (FS_DEBUG_ALLOC, "Free queue: %p\n", txq->sa);
1543 kfree (txq->sa);
1544
1545 func_exit ();
1546 }
1547
1548 static void __devexit free_freepool (struct fs_dev *dev, struct freepool *fp)
1549 {
1550 func_enter ();
1551
1552 write_fs (dev, FP_CNF(fp->offset), 0);
1553 write_fs (dev, FP_SA (fp->offset), 0);
1554 write_fs (dev, FP_EA (fp->offset), 0);
1555 write_fs (dev, FP_CNT(fp->offset), 0);
1556 write_fs (dev, FP_CTU(fp->offset), 0);
1557
1558 func_exit ();
1559 }
1560
1561
1562
1563 static irqreturn_t fs_irq (int irq, void *dev_id)
1564 {
1565 int i;
1566 u32 status;
1567 struct fs_dev *dev = dev_id;
1568
1569 status = read_fs (dev, ISR);
1570 if (!status)
1571 return IRQ_NONE;
1572
1573 func_enter ();
1574
1575 #ifdef IRQ_RATE_LIMIT
1576 /* Aaargh! I'm ashamed. This costs more lines-of-code than the actual
1577 interrupt routine!. (Well, used to when I wrote that comment) -- REW */
1578 {
1579 static int lastjif;
1580 static int nintr=0;
1581
1582 if (lastjif == jiffies) {
1583 if (++nintr > IRQ_RATE_LIMIT) {
1584 free_irq (dev->irq, dev_id);
1585 printk (KERN_ERR "fs: Too many interrupts. Turning off interrupt %d.\n",
1586 dev->irq);
1587 }
1588 } else {
1589 lastjif = jiffies;
1590 nintr = 0;
1591 }
1592 }
1593 #endif
1594 fs_dprintk (FS_DEBUG_QUEUE, "in intr: txq %d txrq %d\n",
1595 read_fs (dev, Q_EA (dev->hp_txq.offset)) -
1596 read_fs (dev, Q_SA (dev->hp_txq.offset)),
1597 read_fs (dev, Q_EA (dev->tx_relq.offset)) -
1598 read_fs (dev, Q_SA (dev->tx_relq.offset)));
1599
1600 /* print the bits in the ISR register. */
1601 if (fs_debug & FS_DEBUG_IRQ) {
1602 /* The FS_DEBUG things are unnecessary here. But this way it is
1603 clear for grep that these are debug prints. */
1604 fs_dprintk (FS_DEBUG_IRQ, "IRQ status:");
1605 for (i=0;i<27;i++)
1606 if (status & (1 << i))
1607 fs_dprintk (FS_DEBUG_IRQ, " %s", irq_bitname[i]);
1608 fs_dprintk (FS_DEBUG_IRQ, "\n");
1609 }
1610
1611 if (status & ISR_RBRQ0_W) {
1612 fs_dprintk (FS_DEBUG_IRQ, "Iiiin-coming (0)!!!!\n");
1613 process_incoming (dev, &dev->rx_rq[0]);
1614 /* items mentioned on RBRQ0 are from FP 0 or 1. */
1615 top_off_fp (dev, &dev->rx_fp[0], GFP_ATOMIC);
1616 top_off_fp (dev, &dev->rx_fp[1], GFP_ATOMIC);
1617 }
1618
1619 if (status & ISR_RBRQ1_W) {
1620 fs_dprintk (FS_DEBUG_IRQ, "Iiiin-coming (1)!!!!\n");
1621 process_incoming (dev, &dev->rx_rq[1]);
1622 top_off_fp (dev, &dev->rx_fp[2], GFP_ATOMIC);
1623 top_off_fp (dev, &dev->rx_fp[3], GFP_ATOMIC);
1624 }
1625
1626 if (status & ISR_RBRQ2_W) {
1627 fs_dprintk (FS_DEBUG_IRQ, "Iiiin-coming (2)!!!!\n");
1628 process_incoming (dev, &dev->rx_rq[2]);
1629 top_off_fp (dev, &dev->rx_fp[4], GFP_ATOMIC);
1630 top_off_fp (dev, &dev->rx_fp[5], GFP_ATOMIC);
1631 }
1632
1633 if (status & ISR_RBRQ3_W) {
1634 fs_dprintk (FS_DEBUG_IRQ, "Iiiin-coming (3)!!!!\n");
1635 process_incoming (dev, &dev->rx_rq[3]);
1636 top_off_fp (dev, &dev->rx_fp[6], GFP_ATOMIC);
1637 top_off_fp (dev, &dev->rx_fp[7], GFP_ATOMIC);
1638 }
1639
1640 if (status & ISR_CSQ_W) {
1641 fs_dprintk (FS_DEBUG_IRQ, "Command executed ok!\n");
1642 process_return_queue (dev, &dev->st_q);
1643 }
1644
1645 if (status & ISR_TBRQ_W) {
1646 fs_dprintk (FS_DEBUG_IRQ, "Data tramsitted!\n");
1647 process_txdone_queue (dev, &dev->tx_relq);
1648 }
1649
1650 func_exit ();
1651 return IRQ_HANDLED;
1652 }
1653
1654
1655 #ifdef FS_POLL_FREQ
1656 static void fs_poll (unsigned long data)
1657 {
1658 struct fs_dev *dev = (struct fs_dev *) data;
1659
1660 fs_irq (0, dev);
1661 dev->timer.expires = jiffies + FS_POLL_FREQ;
1662 add_timer (&dev->timer);
1663 }
1664 #endif
1665
1666 static int __devinit fs_init (struct fs_dev *dev)
1667 {
1668 struct pci_dev *pci_dev;
1669 int isr, to;
1670 int i;
1671
1672 func_enter ();
1673 pci_dev = dev->pci_dev;
1674
1675 printk (KERN_INFO "found a FireStream %d card, base %16llx, irq%d.\n",
1676 IS_FS50(dev)?50:155,
1677 (unsigned long long)pci_resource_start(pci_dev, 0),
1678 dev->pci_dev->irq);
1679
1680 if (fs_debug & FS_DEBUG_INIT)
1681 my_hd ((unsigned char *) dev, sizeof (*dev));
1682
1683 undocumented_pci_fix (pci_dev);
1684
1685 dev->hw_base = pci_resource_start(pci_dev, 0);
1686
1687 dev->base = ioremap(dev->hw_base, 0x1000);
1688
1689 reset_chip (dev);
1690
1691 write_fs (dev, SARMODE0, 0
1692 | (0 * SARMODE0_SHADEN) /* We don't use shadow registers. */
1693 | (1 * SARMODE0_INTMODE_READCLEAR)
1694 | (1 * SARMODE0_CWRE)
1695 | (IS_FS50(dev) ? SARMODE0_PRPWT_FS50_5:
1696 SARMODE0_PRPWT_FS155_3)
1697 | (1 * SARMODE0_CALSUP_1)
1698 | (IS_FS50(dev) ? (0
1699 | SARMODE0_RXVCS_32
1700 | SARMODE0_ABRVCS_32
1701 | SARMODE0_TXVCS_32):
1702 (0
1703 | SARMODE0_RXVCS_1k
1704 | SARMODE0_ABRVCS_1k
1705 | SARMODE0_TXVCS_1k)));
1706
1707 /* 10ms * 100 is 1 second. That should be enough, as AN3:9 says it takes
1708 1ms. */
1709 to = 100;
1710 while (--to) {
1711 isr = read_fs (dev, ISR);
1712
1713 /* This bit is documented as "RESERVED" */
1714 if (isr & ISR_INIT_ERR) {
1715 printk (KERN_ERR "Error initializing the FS... \n");
1716 goto unmap;
1717 }
1718 if (isr & ISR_INIT) {
1719 fs_dprintk (FS_DEBUG_INIT, "Ha! Initialized OK!\n");
1720 break;
1721 }
1722
1723 /* Try again after 10ms. */
1724 msleep(10);
1725 }
1726
1727 if (!to) {
1728 printk (KERN_ERR "timeout initializing the FS... \n");
1729 goto unmap;
1730 }
1731
1732 /* XXX fix for fs155 */
1733 dev->channel_mask = 0x1f;
1734 dev->channo = 0;
1735
1736 /* AN3: 10 */
1737 write_fs (dev, SARMODE1, 0
1738 | (fs_keystream * SARMODE1_DEFHEC) /* XXX PHY */
1739 | ((loopback == 1) * SARMODE1_TSTLP) /* XXX Loopback mode enable... */
1740 | (1 * SARMODE1_DCRM)
1741 | (1 * SARMODE1_DCOAM)
1742 | (0 * SARMODE1_OAMCRC)
1743 | (0 * SARMODE1_DUMPE)
1744 | (0 * SARMODE1_GPLEN)
1745 | (0 * SARMODE1_GNAM)
1746 | (0 * SARMODE1_GVAS)
1747 | (0 * SARMODE1_GPAS)
1748 | (1 * SARMODE1_GPRI)
1749 | (0 * SARMODE1_PMS)
1750 | (0 * SARMODE1_GFCR)
1751 | (1 * SARMODE1_HECM2)
1752 | (1 * SARMODE1_HECM1)
1753 | (1 * SARMODE1_HECM0)
1754 | (1 << 12) /* That's what hang's driver does. Program to 0 */
1755 | (0 * 0xff) /* XXX FS155 */);
1756
1757
1758 /* Cal prescale etc */
1759
1760 /* AN3: 11 */
1761 write_fs (dev, TMCONF, 0x0000000f);
1762 write_fs (dev, CALPRESCALE, 0x01010101 * num);
1763 write_fs (dev, 0x80, 0x000F00E4);
1764
1765 /* AN3: 12 */
1766 write_fs (dev, CELLOSCONF, 0
1767 | ( 0 * CELLOSCONF_CEN)
1768 | ( CELLOSCONF_SC1)
1769 | (0x80 * CELLOSCONF_COBS)
1770 | (num * CELLOSCONF_COPK) /* Changed from 0xff to 0x5a */
1771 | (num * CELLOSCONF_COST));/* after a hint from Hang.
1772 * performance jumped 50->70... */
1773
1774 /* Magic value by Hang */
1775 write_fs (dev, CELLOSCONF_COST, 0x0B809191);
1776
1777 if (IS_FS50 (dev)) {
1778 write_fs (dev, RAS0, RAS0_DCD_XHLT);
1779 dev->atm_dev->ci_range.vpi_bits = 12;
1780 dev->atm_dev->ci_range.vci_bits = 16;
1781 dev->nchannels = FS50_NR_CHANNELS;
1782 } else {
1783 write_fs (dev, RAS0, RAS0_DCD_XHLT
1784 | (((1 << FS155_VPI_BITS) - 1) * RAS0_VPSEL)
1785 | (((1 << FS155_VCI_BITS) - 1) * RAS0_VCSEL));
1786 /* We can chose the split arbitrarily. We might be able to
1787 support more. Whatever. This should do for now. */
1788 dev->atm_dev->ci_range.vpi_bits = FS155_VPI_BITS;
1789 dev->atm_dev->ci_range.vci_bits = FS155_VCI_BITS;
1790
1791 /* Address bits we can't use should be compared to 0. */
1792 write_fs (dev, RAC, 0);
1793
1794 /* Manual (AN9, page 6) says ASF1=0 means compare Utopia address
1795 * too. I can't find ASF1 anywhere. Anyway, we AND with just the
1796 * other bits, then compare with 0, which is exactly what we
1797 * want. */
1798 write_fs (dev, RAM, (1 << (28 - FS155_VPI_BITS - FS155_VCI_BITS)) - 1);
1799 dev->nchannels = FS155_NR_CHANNELS;
1800 }
1801 dev->atm_vccs = kcalloc (dev->nchannels, sizeof (struct atm_vcc *),
1802 GFP_KERNEL);
1803 fs_dprintk (FS_DEBUG_ALLOC, "Alloc atmvccs: %p(%Zd)\n",
1804 dev->atm_vccs, dev->nchannels * sizeof (struct atm_vcc *));
1805
1806 if (!dev->atm_vccs) {
1807 printk (KERN_WARNING "Couldn't allocate memory for VCC buffers. Woops!\n");
1808 /* XXX Clean up..... */
1809 goto unmap;
1810 }
1811
1812 dev->tx_inuse = kzalloc (dev->nchannels / 8 /* bits/byte */ , GFP_KERNEL);
1813 fs_dprintk (FS_DEBUG_ALLOC, "Alloc tx_inuse: %p(%d)\n",
1814 dev->atm_vccs, dev->nchannels / 8);
1815
1816 if (!dev->tx_inuse) {
1817 printk (KERN_WARNING "Couldn't allocate memory for tx_inuse bits!\n");
1818 /* XXX Clean up..... */
1819 goto unmap;
1820 }
1821 /* -- RAS1 : FS155 and 50 differ. Default (0) should be OK for both */
1822 /* -- RAS2 : FS50 only: Default is OK. */
1823
1824 /* DMAMODE, default should be OK. -- REW */
1825 write_fs (dev, DMAMR, DMAMR_TX_MODE_FULL);
1826
1827 init_q (dev, &dev->hp_txq, TX_PQ(TXQ_HP), TXQ_NENTRIES, 0);
1828 init_q (dev, &dev->lp_txq, TX_PQ(TXQ_LP), TXQ_NENTRIES, 0);
1829 init_q (dev, &dev->tx_relq, TXB_RQ, TXQ_NENTRIES, 1);
1830 init_q (dev, &dev->st_q, ST_Q, TXQ_NENTRIES, 1);
1831
1832 for (i=0;i < FS_NR_FREE_POOLS;i++) {
1833 init_fp (dev, &dev->rx_fp[i], RXB_FP(i),
1834 rx_buf_sizes[i], rx_pool_sizes[i]);
1835 top_off_fp (dev, &dev->rx_fp[i], GFP_KERNEL);
1836 }
1837
1838
1839 for (i=0;i < FS_NR_RX_QUEUES;i++)
1840 init_q (dev, &dev->rx_rq[i], RXB_RQ(i), RXRQ_NENTRIES, 1);
1841
1842 dev->irq = pci_dev->irq;
1843 if (request_irq (dev->irq, fs_irq, IRQF_SHARED, "firestream", dev)) {
1844 printk (KERN_WARNING "couldn't get irq %d for firestream.\n", pci_dev->irq);
1845 /* XXX undo all previous stuff... */
1846 goto unmap;
1847 }
1848 fs_dprintk (FS_DEBUG_INIT, "Grabbed irq %d for dev at %p.\n", dev->irq, dev);
1849
1850 /* We want to be notified of most things. Just the statistics count
1851 overflows are not interesting */
1852 write_fs (dev, IMR, 0
1853 | ISR_RBRQ0_W
1854 | ISR_RBRQ1_W
1855 | ISR_RBRQ2_W
1856 | ISR_RBRQ3_W
1857 | ISR_TBRQ_W
1858 | ISR_CSQ_W);
1859
1860 write_fs (dev, SARMODE0, 0
1861 | (0 * SARMODE0_SHADEN) /* We don't use shadow registers. */
1862 | (1 * SARMODE0_GINT)
1863 | (1 * SARMODE0_INTMODE_READCLEAR)
1864 | (0 * SARMODE0_CWRE)
1865 | (IS_FS50(dev)?SARMODE0_PRPWT_FS50_5:
1866 SARMODE0_PRPWT_FS155_3)
1867 | (1 * SARMODE0_CALSUP_1)
1868 | (IS_FS50 (dev)?(0
1869 | SARMODE0_RXVCS_32
1870 | SARMODE0_ABRVCS_32
1871 | SARMODE0_TXVCS_32):
1872 (0
1873 | SARMODE0_RXVCS_1k
1874 | SARMODE0_ABRVCS_1k
1875 | SARMODE0_TXVCS_1k))
1876 | (1 * SARMODE0_RUN));
1877
1878 init_phy (dev, PHY_NTC_INIT);
1879
1880 if (loopback == 2) {
1881 write_phy (dev, 0x39, 0x000e);
1882 }
1883
1884 #ifdef FS_POLL_FREQ
1885 init_timer (&dev->timer);
1886 dev->timer.data = (unsigned long) dev;
1887 dev->timer.function = fs_poll;
1888 dev->timer.expires = jiffies + FS_POLL_FREQ;
1889 add_timer (&dev->timer);
1890 #endif
1891
1892 dev->atm_dev->dev_data = dev;
1893
1894 func_exit ();
1895 return 0;
1896 unmap:
1897 iounmap(dev->base);
1898 return 1;
1899 }
1900
1901 static int __devinit firestream_init_one (struct pci_dev *pci_dev,
1902 const struct pci_device_id *ent)
1903 {
1904 struct atm_dev *atm_dev;
1905 struct fs_dev *fs_dev;
1906
1907 if (pci_enable_device(pci_dev))
1908 goto err_out;
1909
1910 fs_dev = kzalloc (sizeof (struct fs_dev), GFP_KERNEL);
1911 fs_dprintk (FS_DEBUG_ALLOC, "Alloc fs-dev: %p(%Zd)\n",
1912 fs_dev, sizeof (struct fs_dev));
1913 if (!fs_dev)
1914 goto err_out;
1915 atm_dev = atm_dev_register("fs", &pci_dev->dev, &ops, -1, NULL);
1916 if (!atm_dev)
1917 goto err_out_free_fs_dev;
1918
1919 fs_dev->pci_dev = pci_dev;
1920 fs_dev->atm_dev = atm_dev;
1921 fs_dev->flags = ent->driver_data;
1922
1923 if (fs_init(fs_dev))
1924 goto err_out_free_atm_dev;
1925
1926 fs_dev->next = fs_boards;
1927 fs_boards = fs_dev;
1928 return 0;
1929
1930 err_out_free_atm_dev:
1931 atm_dev_deregister(atm_dev);
1932 err_out_free_fs_dev:
1933 kfree(fs_dev);
1934 err_out:
1935 return -ENODEV;
1936 }
1937
1938 static void __devexit firestream_remove_one (struct pci_dev *pdev)
1939 {
1940 int i;
1941 struct fs_dev *dev, *nxtdev;
1942 struct fs_vcc *vcc;
1943 struct FS_BPENTRY *fp, *nxt;
1944
1945 func_enter ();
1946
1947 #if 0
1948 printk ("hptxq:\n");
1949 for (i=0;i<60;i++) {
1950 printk ("%d: %08x %08x %08x %08x \n",
1951 i, pq[qp].cmd, pq[qp].p0, pq[qp].p1, pq[qp].p2);
1952 qp++;
1953 if (qp >= 60) qp = 0;
1954 }
1955
1956 printk ("descriptors:\n");
1957 for (i=0;i<60;i++) {
1958 printk ("%d: %p: %08x %08x %p %p\n",
1959 i, da[qd], dq[qd].flags, dq[qd].bsa, dq[qd].skb, dq[qd].dev);
1960 qd++;
1961 if (qd >= 60) qd = 0;
1962 }
1963 #endif
1964
1965 for (dev = fs_boards;dev != NULL;dev=nxtdev) {
1966 fs_dprintk (FS_DEBUG_CLEANUP, "Releasing resources for dev at %p.\n", dev);
1967
1968 /* XXX Hit all the tx channels too! */
1969
1970 for (i=0;i < dev->nchannels;i++) {
1971 if (dev->atm_vccs[i]) {
1972 vcc = FS_VCC (dev->atm_vccs[i]);
1973 submit_command (dev, &dev->hp_txq,
1974 QE_CMD_TX_PURGE_INH | QE_CMD_IMM_INQ | vcc->channo, 0,0,0);
1975 submit_command (dev, &dev->hp_txq,
1976 QE_CMD_RX_PURGE_INH | QE_CMD_IMM_INQ | vcc->channo, 0,0,0);
1977
1978 }
1979 }
1980
1981 /* XXX Wait a while for the chip to release all buffers. */
1982
1983 for (i=0;i < FS_NR_FREE_POOLS;i++) {
1984 for (fp=bus_to_virt (read_fs (dev, FP_SA(dev->rx_fp[i].offset)));
1985 !(fp->flags & FP_FLAGS_EPI);fp = nxt) {
1986 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-skb: %p\n", fp->skb);
1987 dev_kfree_skb_any (fp->skb);
1988 nxt = bus_to_virt (fp->next);
1989 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-d: %p\n", fp);
1990 kfree (fp);
1991 }
1992 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-skb: %p\n", fp->skb);
1993 dev_kfree_skb_any (fp->skb);
1994 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-d: %p\n", fp);
1995 kfree (fp);
1996 }
1997
1998 /* Hang the chip in "reset", prevent it clobbering memory that is
1999 no longer ours. */
2000 reset_chip (dev);
2001
2002 fs_dprintk (FS_DEBUG_CLEANUP, "Freeing irq%d.\n", dev->irq);
2003 free_irq (dev->irq, dev);
2004 del_timer (&dev->timer);
2005
2006 atm_dev_deregister(dev->atm_dev);
2007 free_queue (dev, &dev->hp_txq);
2008 free_queue (dev, &dev->lp_txq);
2009 free_queue (dev, &dev->tx_relq);
2010 free_queue (dev, &dev->st_q);
2011
2012 fs_dprintk (FS_DEBUG_ALLOC, "Free atmvccs: %p\n", dev->atm_vccs);
2013 kfree (dev->atm_vccs);
2014
2015 for (i=0;i< FS_NR_FREE_POOLS;i++)
2016 free_freepool (dev, &dev->rx_fp[i]);
2017
2018 for (i=0;i < FS_NR_RX_QUEUES;i++)
2019 free_queue (dev, &dev->rx_rq[i]);
2020
2021 iounmap(dev->base);
2022 fs_dprintk (FS_DEBUG_ALLOC, "Free fs-dev: %p\n", dev);
2023 nxtdev = dev->next;
2024 kfree (dev);
2025 }
2026
2027 func_exit ();
2028 }
2029
2030 static struct pci_device_id firestream_pci_tbl[] = {
2031 { PCI_VDEVICE(FUJITSU_ME, PCI_DEVICE_ID_FUJITSU_FS50), FS_IS50},
2032 { PCI_VDEVICE(FUJITSU_ME, PCI_DEVICE_ID_FUJITSU_FS155), FS_IS155},
2033 { 0, }
2034 };
2035
2036 MODULE_DEVICE_TABLE(pci, firestream_pci_tbl);
2037
2038 static struct pci_driver firestream_driver = {
2039 .name = "firestream",
2040 .id_table = firestream_pci_tbl,
2041 .probe = firestream_init_one,
2042 .remove = __devexit_p(firestream_remove_one),
2043 };
2044
2045 static int __init firestream_init_module (void)
2046 {
2047 int error;
2048
2049 func_enter ();
2050 error = pci_register_driver(&firestream_driver);
2051 func_exit ();
2052 return error;
2053 }
2054
2055 static void __exit firestream_cleanup_module(void)
2056 {
2057 pci_unregister_driver(&firestream_driver);
2058 }
2059
2060 module_init(firestream_init_module);
2061 module_exit(firestream_cleanup_module);
2062
2063 MODULE_LICENSE("GPL");
2064
2065
2066
linux-next