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ALSA: hda - Add static_hdmi_pcm option to HDMI codec parser
[linux-2.6/next.git] / drivers / spi / dw_spi.c
blob90439314cf673ce19c33747ab4f283f0f3f0bc01
1 /*
2 * dw_spi.c - Designware SPI core controller driver (refer pxa2xx_spi.c)
3 *
4 * Copyright (c) 2009, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 */
19
20 #include <linux/dma-mapping.h>
21 #include <linux/interrupt.h>
22 #include <linux/highmem.h>
23 #include <linux/delay.h>
24 #include <linux/slab.h>
25
26 #include <linux/spi/dw_spi.h>
27 #include <linux/spi/spi.h>
28
29 #ifdef CONFIG_DEBUG_FS
30 #include <linux/debugfs.h>
31 #endif
32
33 #define START_STATE ((void *)0)
34 #define RUNNING_STATE ((void *)1)
35 #define DONE_STATE ((void *)2)
36 #define ERROR_STATE ((void *)-1)
37
38 #define QUEUE_RUNNING 0
39 #define QUEUE_STOPPED 1
40
41 #define MRST_SPI_DEASSERT 0
42 #define MRST_SPI_ASSERT 1
43
44 /* Slave spi_dev related */
45 struct chip_data {
46 u16 cr0;
47 u8 cs; /* chip select pin */
48 u8 n_bytes; /* current is a 1/2/4 byte op */
49 u8 tmode; /* TR/TO/RO/EEPROM */
50 u8 type; /* SPI/SSP/MicroWire */
51
52 u8 poll_mode; /* 1 means use poll mode */
53
54 u32 dma_width;
55 u32 rx_threshold;
56 u32 tx_threshold;
57 u8 enable_dma;
58 u8 bits_per_word;
59 u16 clk_div; /* baud rate divider */
60 u32 speed_hz; /* baud rate */
61 int (*write)(struct dw_spi *dws);
62 int (*read)(struct dw_spi *dws);
63 void (*cs_control)(u32 command);
64 };
65
66 #ifdef CONFIG_DEBUG_FS
67 static int spi_show_regs_open(struct inode *inode, struct file *file)
68 {
69 file->private_data = inode->i_private;
70 return 0;
71 }
72
73 #define SPI_REGS_BUFSIZE 1024
74 static ssize_t spi_show_regs(struct file *file, char __user *user_buf,
75 size_t count, loff_t *ppos)
76 {
77 struct dw_spi *dws;
78 char *buf;
79 u32 len = 0;
80 ssize_t ret;
81
82 dws = file->private_data;
83
84 buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
85 if (!buf)
86 return 0;
87
88 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
89 "MRST SPI0 registers:\n");
90 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
91 "=================================\n");
92 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
93 "CTRL0: \t\t0x%08x\n", dw_readl(dws, ctrl0));
94 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
95 "CTRL1: \t\t0x%08x\n", dw_readl(dws, ctrl1));
96 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
97 "SSIENR: \t0x%08x\n", dw_readl(dws, ssienr));
98 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
99 "SER: \t\t0x%08x\n", dw_readl(dws, ser));
100 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
101 "BAUDR: \t\t0x%08x\n", dw_readl(dws, baudr));
102 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
103 "TXFTLR: \t0x%08x\n", dw_readl(dws, txfltr));
104 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
105 "RXFTLR: \t0x%08x\n", dw_readl(dws, rxfltr));
106 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
107 "TXFLR: \t\t0x%08x\n", dw_readl(dws, txflr));
108 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
109 "RXFLR: \t\t0x%08x\n", dw_readl(dws, rxflr));
110 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
111 "SR: \t\t0x%08x\n", dw_readl(dws, sr));
112 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
113 "IMR: \t\t0x%08x\n", dw_readl(dws, imr));
114 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
115 "ISR: \t\t0x%08x\n", dw_readl(dws, isr));
116 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
117 "DMACR: \t\t0x%08x\n", dw_readl(dws, dmacr));
118 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
119 "DMATDLR: \t0x%08x\n", dw_readl(dws, dmatdlr));
120 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
121 "DMARDLR: \t0x%08x\n", dw_readl(dws, dmardlr));
122 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
123 "=================================\n");
124
125 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
126 kfree(buf);
127 return ret;
128 }
129
130 static const struct file_operations mrst_spi_regs_ops = {
131 .owner = THIS_MODULE,
132 .open = spi_show_regs_open,
133 .read = spi_show_regs,
134 .llseek = default_llseek,
135 };
136
137 static int mrst_spi_debugfs_init(struct dw_spi *dws)
138 {
139 dws->debugfs = debugfs_create_dir("mrst_spi", NULL);
140 if (!dws->debugfs)
141 return -ENOMEM;
142
143 debugfs_create_file("registers", S_IFREG | S_IRUGO,
144 dws->debugfs, (void *)dws, &mrst_spi_regs_ops);
145 return 0;
146 }
147
148 static void mrst_spi_debugfs_remove(struct dw_spi *dws)
149 {
150 if (dws->debugfs)
151 debugfs_remove_recursive(dws->debugfs);
152 }
153
154 #else
155 static inline int mrst_spi_debugfs_init(struct dw_spi *dws)
156 {
157 return 0;
158 }
159
160 static inline void mrst_spi_debugfs_remove(struct dw_spi *dws)
161 {
162 }
163 #endif /* CONFIG_DEBUG_FS */
164
165 static void wait_till_not_busy(struct dw_spi *dws)
166 {
167 unsigned long end = jiffies + 1 + usecs_to_jiffies(1000);
168
169 while (time_before(jiffies, end)) {
170 if (!(dw_readw(dws, sr) & SR_BUSY))
171 return;
172 }
173 dev_err(&dws->master->dev,
174 "DW SPI: Status keeps busy for 1000us after a read/write!\n");
175 }
176
177 static void flush(struct dw_spi *dws)
178 {
179 while (dw_readw(dws, sr) & SR_RF_NOT_EMPT)
180 dw_readw(dws, dr);
181
182 wait_till_not_busy(dws);
183 }
184
185 static int null_writer(struct dw_spi *dws)
186 {
187 u8 n_bytes = dws->n_bytes;
188
189 if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
190 || (dws->tx == dws->tx_end))
191 return 0;
192 dw_writew(dws, dr, 0);
193 dws->tx += n_bytes;
194
195 wait_till_not_busy(dws);
196 return 1;
197 }
198
199 static int null_reader(struct dw_spi *dws)
200 {
201 u8 n_bytes = dws->n_bytes;
202
203 while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
204 && (dws->rx < dws->rx_end)) {
205 dw_readw(dws, dr);
206 dws->rx += n_bytes;
207 }
208 wait_till_not_busy(dws);
209 return dws->rx == dws->rx_end;
210 }
211
212 static int u8_writer(struct dw_spi *dws)
213 {
214 if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
215 || (dws->tx == dws->tx_end))
216 return 0;
217
218 dw_writew(dws, dr, *(u8 *)(dws->tx));
219 ++dws->tx;
220
221 wait_till_not_busy(dws);
222 return 1;
223 }
224
225 static int u8_reader(struct dw_spi *dws)
226 {
227 while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
228 && (dws->rx < dws->rx_end)) {
229 *(u8 *)(dws->rx) = dw_readw(dws, dr);
230 ++dws->rx;
231 }
232
233 wait_till_not_busy(dws);
234 return dws->rx == dws->rx_end;
235 }
236
237 static int u16_writer(struct dw_spi *dws)
238 {
239 if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
240 || (dws->tx == dws->tx_end))
241 return 0;
242
243 dw_writew(dws, dr, *(u16 *)(dws->tx));
244 dws->tx += 2;
245
246 wait_till_not_busy(dws);
247 return 1;
248 }
249
250 static int u16_reader(struct dw_spi *dws)
251 {
252 u16 temp;
253
254 while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
255 && (dws->rx < dws->rx_end)) {
256 temp = dw_readw(dws, dr);
257 *(u16 *)(dws->rx) = temp;
258 dws->rx += 2;
259 }
260
261 wait_till_not_busy(dws);
262 return dws->rx == dws->rx_end;
263 }
264
265 static void *next_transfer(struct dw_spi *dws)
266 {
267 struct spi_message *msg = dws->cur_msg;
268 struct spi_transfer *trans = dws->cur_transfer;
269
270 /* Move to next transfer */
271 if (trans->transfer_list.next != &msg->transfers) {
272 dws->cur_transfer =
273 list_entry(trans->transfer_list.next,
274 struct spi_transfer,
275 transfer_list);
276 return RUNNING_STATE;
277 } else
278 return DONE_STATE;
279 }
280
281 /*
282 * Note: first step is the protocol driver prepares
283 * a dma-capable memory, and this func just need translate
284 * the virt addr to physical
285 */
286 static int map_dma_buffers(struct dw_spi *dws)
287 {
288 if (!dws->cur_msg->is_dma_mapped || !dws->dma_inited
289 || !dws->cur_chip->enable_dma)
290 return 0;
291
292 if (dws->cur_transfer->tx_dma)
293 dws->tx_dma = dws->cur_transfer->tx_dma;
294
295 if (dws->cur_transfer->rx_dma)
296 dws->rx_dma = dws->cur_transfer->rx_dma;
297
298 return 1;
299 }
300
301 /* Caller already set message->status; dma and pio irqs are blocked */
302 static void giveback(struct dw_spi *dws)
303 {
304 struct spi_transfer *last_transfer;
305 unsigned long flags;
306 struct spi_message *msg;
307
308 spin_lock_irqsave(&dws->lock, flags);
309 msg = dws->cur_msg;
310 dws->cur_msg = NULL;
311 dws->cur_transfer = NULL;
312 dws->prev_chip = dws->cur_chip;
313 dws->cur_chip = NULL;
314 dws->dma_mapped = 0;
315 queue_work(dws->workqueue, &dws->pump_messages);
316 spin_unlock_irqrestore(&dws->lock, flags);
317
318 last_transfer = list_entry(msg->transfers.prev,
319 struct spi_transfer,
320 transfer_list);
321
322 if (!last_transfer->cs_change && dws->cs_control)
323 dws->cs_control(MRST_SPI_DEASSERT);
324
325 msg->state = NULL;
326 if (msg->complete)
327 msg->complete(msg->context);
328 }
329
330 static void int_error_stop(struct dw_spi *dws, const char *msg)
331 {
332 /* Stop and reset hw */
333 flush(dws);
334 spi_enable_chip(dws, 0);
335
336 dev_err(&dws->master->dev, "%s\n", msg);
337 dws->cur_msg->state = ERROR_STATE;
338 tasklet_schedule(&dws->pump_transfers);
339 }
340
341 static void transfer_complete(struct dw_spi *dws)
342 {
343 /* Update total byte transfered return count actual bytes read */
344 dws->cur_msg->actual_length += dws->len;
345
346 /* Move to next transfer */
347 dws->cur_msg->state = next_transfer(dws);
348
349 /* Handle end of message */
350 if (dws->cur_msg->state == DONE_STATE) {
351 dws->cur_msg->status = 0;
352 giveback(dws);
353 } else
354 tasklet_schedule(&dws->pump_transfers);
355 }
356
357 static irqreturn_t interrupt_transfer(struct dw_spi *dws)
358 {
359 u16 irq_status, irq_mask = 0x3f;
360 u32 int_level = dws->fifo_len / 2;
361 u32 left;
362
363 irq_status = dw_readw(dws, isr) & irq_mask;
364 /* Error handling */
365 if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
366 dw_readw(dws, txoicr);
367 dw_readw(dws, rxoicr);
368 dw_readw(dws, rxuicr);
369 int_error_stop(dws, "interrupt_transfer: fifo overrun");
370 return IRQ_HANDLED;
371 }
372
373 if (irq_status & SPI_INT_TXEI) {
374 spi_mask_intr(dws, SPI_INT_TXEI);
375
376 left = (dws->tx_end - dws->tx) / dws->n_bytes;
377 left = (left > int_level) ? int_level : left;
378
379 while (left--)
380 dws->write(dws);
381 dws->read(dws);
382
383 /* Re-enable the IRQ if there is still data left to tx */
384 if (dws->tx_end > dws->tx)
385 spi_umask_intr(dws, SPI_INT_TXEI);
386 else
387 transfer_complete(dws);
388 }
389
390 return IRQ_HANDLED;
391 }
392
393 static irqreturn_t dw_spi_irq(int irq, void *dev_id)
394 {
395 struct dw_spi *dws = dev_id;
396 u16 irq_status, irq_mask = 0x3f;
397
398 irq_status = dw_readw(dws, isr) & irq_mask;
399 if (!irq_status)
400 return IRQ_NONE;
401
402 if (!dws->cur_msg) {
403 spi_mask_intr(dws, SPI_INT_TXEI);
404 /* Never fail */
405 return IRQ_HANDLED;
406 }
407
408 return dws->transfer_handler(dws);
409 }
410
411 /* Must be called inside pump_transfers() */
412 static void poll_transfer(struct dw_spi *dws)
413 {
414 while (dws->write(dws))
415 dws->read(dws);
416
417 transfer_complete(dws);
418 }
419
420 static void dma_transfer(struct dw_spi *dws, int cs_change)
421 {
422 }
423
424 static void pump_transfers(unsigned long data)
425 {
426 struct dw_spi *dws = (struct dw_spi *)data;
427 struct spi_message *message = NULL;
428 struct spi_transfer *transfer = NULL;
429 struct spi_transfer *previous = NULL;
430 struct spi_device *spi = NULL;
431 struct chip_data *chip = NULL;
432 u8 bits = 0;
433 u8 imask = 0;
434 u8 cs_change = 0;
435 u16 txint_level = 0;
436 u16 clk_div = 0;
437 u32 speed = 0;
438 u32 cr0 = 0;
439
440 /* Get current state information */
441 message = dws->cur_msg;
442 transfer = dws->cur_transfer;
443 chip = dws->cur_chip;
444 spi = message->spi;
445
446 if (unlikely(!chip->clk_div))
447 chip->clk_div = dws->max_freq / chip->speed_hz;
448
449 if (message->state == ERROR_STATE) {
450 message->status = -EIO;
451 goto early_exit;
452 }
453
454 /* Handle end of message */
455 if (message->state == DONE_STATE) {
456 message->status = 0;
457 goto early_exit;
458 }
459
460 /* Delay if requested at end of transfer*/
461 if (message->state == RUNNING_STATE) {
462 previous = list_entry(transfer->transfer_list.prev,
463 struct spi_transfer,
464 transfer_list);
465 if (previous->delay_usecs)
466 udelay(previous->delay_usecs);
467 }
468
469 dws->n_bytes = chip->n_bytes;
470 dws->dma_width = chip->dma_width;
471 dws->cs_control = chip->cs_control;
472
473 dws->rx_dma = transfer->rx_dma;
474 dws->tx_dma = transfer->tx_dma;
475 dws->tx = (void *)transfer->tx_buf;
476 dws->tx_end = dws->tx + transfer->len;
477 dws->rx = transfer->rx_buf;
478 dws->rx_end = dws->rx + transfer->len;
479 dws->write = dws->tx ? chip->write : null_writer;
480 dws->read = dws->rx ? chip->read : null_reader;
481 dws->cs_change = transfer->cs_change;
482 dws->len = dws->cur_transfer->len;
483 if (chip != dws->prev_chip)
484 cs_change = 1;
485
486 cr0 = chip->cr0;
487
488 /* Handle per transfer options for bpw and speed */
489 if (transfer->speed_hz) {
490 speed = chip->speed_hz;
491
492 if (transfer->speed_hz != speed) {
493 speed = transfer->speed_hz;
494 if (speed > dws->max_freq) {
495 printk(KERN_ERR "MRST SPI0: unsupported"
496 "freq: %dHz\n", speed);
497 message->status = -EIO;
498 goto early_exit;
499 }
500
501 /* clk_div doesn't support odd number */
502 clk_div = dws->max_freq / speed;
503 clk_div = (clk_div + 1) & 0xfffe;
504
505 chip->speed_hz = speed;
506 chip->clk_div = clk_div;
507 }
508 }
509 if (transfer->bits_per_word) {
510 bits = transfer->bits_per_word;
511
512 switch (bits) {
513 case 8:
514 dws->n_bytes = 1;
515 dws->dma_width = 1;
516 dws->read = (dws->read != null_reader) ?
517 u8_reader : null_reader;
518 dws->write = (dws->write != null_writer) ?
519 u8_writer : null_writer;
520 break;
521 case 16:
522 dws->n_bytes = 2;
523 dws->dma_width = 2;
524 dws->read = (dws->read != null_reader) ?
525 u16_reader : null_reader;
526 dws->write = (dws->write != null_writer) ?
527 u16_writer : null_writer;
528 break;
529 default:
530 printk(KERN_ERR "MRST SPI0: unsupported bits:"
531 "%db\n", bits);
532 message->status = -EIO;
533 goto early_exit;
534 }
535
536 cr0 = (bits - 1)
537 | (chip->type << SPI_FRF_OFFSET)
538 | (spi->mode << SPI_MODE_OFFSET)
539 | (chip->tmode << SPI_TMOD_OFFSET);
540 }
541 message->state = RUNNING_STATE;
542
543 /*
544 * Adjust transfer mode if necessary. Requires platform dependent
545 * chipselect mechanism.
546 */
547 if (dws->cs_control) {
548 if (dws->rx && dws->tx)
549 chip->tmode = SPI_TMOD_TR;
550 else if (dws->rx)
551 chip->tmode = SPI_TMOD_RO;
552 else
553 chip->tmode = SPI_TMOD_TO;
554
555 cr0 &= ~SPI_TMOD_MASK;
556 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
557 }
558
559 /* Check if current transfer is a DMA transaction */
560 dws->dma_mapped = map_dma_buffers(dws);
561
562 /*
563 * Interrupt mode
564 * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
565 */
566 if (!dws->dma_mapped && !chip->poll_mode) {
567 int templen = dws->len / dws->n_bytes;
568 txint_level = dws->fifo_len / 2;
569 txint_level = (templen > txint_level) ? txint_level : templen;
570
571 imask |= SPI_INT_TXEI;
572 dws->transfer_handler = interrupt_transfer;
573 }
574
575 /*
576 * Reprogram registers only if
577 * 1. chip select changes
578 * 2. clk_div is changed
579 * 3. control value changes
580 */
581 if (dw_readw(dws, ctrl0) != cr0 || cs_change || clk_div || imask) {
582 spi_enable_chip(dws, 0);
583
584 if (dw_readw(dws, ctrl0) != cr0)
585 dw_writew(dws, ctrl0, cr0);
586
587 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
588 spi_chip_sel(dws, spi->chip_select);
589
590 /* Set the interrupt mask, for poll mode just diable all int */
591 spi_mask_intr(dws, 0xff);
592 if (imask)
593 spi_umask_intr(dws, imask);
594 if (txint_level)
595 dw_writew(dws, txfltr, txint_level);
596
597 spi_enable_chip(dws, 1);
598 if (cs_change)
599 dws->prev_chip = chip;
600 }
601
602 if (dws->dma_mapped)
603 dma_transfer(dws, cs_change);
604
605 if (chip->poll_mode)
606 poll_transfer(dws);
607
608 return;
609
610 early_exit:
611 giveback(dws);
612 return;
613 }
614
615 static void pump_messages(struct work_struct *work)
616 {
617 struct dw_spi *dws =
618 container_of(work, struct dw_spi, pump_messages);
619 unsigned long flags;
620
621 /* Lock queue and check for queue work */
622 spin_lock_irqsave(&dws->lock, flags);
623 if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {
624 dws->busy = 0;
625 spin_unlock_irqrestore(&dws->lock, flags);
626 return;
627 }
628
629 /* Make sure we are not already running a message */
630 if (dws->cur_msg) {
631 spin_unlock_irqrestore(&dws->lock, flags);
632 return;
633 }
634
635 /* Extract head of queue */
636 dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);
637 list_del_init(&dws->cur_msg->queue);
638
639 /* Initial message state*/
640 dws->cur_msg->state = START_STATE;
641 dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
642 struct spi_transfer,
643 transfer_list);
644 dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
645
646 /* Mark as busy and launch transfers */
647 tasklet_schedule(&dws->pump_transfers);
648
649 dws->busy = 1;
650 spin_unlock_irqrestore(&dws->lock, flags);
651 }
652
653 /* spi_device use this to queue in their spi_msg */
654 static int dw_spi_transfer(struct spi_device *spi, struct spi_message *msg)
655 {
656 struct dw_spi *dws = spi_master_get_devdata(spi->master);
657 unsigned long flags;
658
659 spin_lock_irqsave(&dws->lock, flags);
660
661 if (dws->run == QUEUE_STOPPED) {
662 spin_unlock_irqrestore(&dws->lock, flags);
663 return -ESHUTDOWN;
664 }
665
666 msg->actual_length = 0;
667 msg->status = -EINPROGRESS;
668 msg->state = START_STATE;
669
670 list_add_tail(&msg->queue, &dws->queue);
671
672 if (dws->run == QUEUE_RUNNING && !dws->busy) {
673
674 if (dws->cur_transfer || dws->cur_msg)
675 queue_work(dws->workqueue,
676 &dws->pump_messages);
677 else {
678 /* If no other data transaction in air, just go */
679 spin_unlock_irqrestore(&dws->lock, flags);
680 pump_messages(&dws->pump_messages);
681 return 0;
682 }
683 }
684
685 spin_unlock_irqrestore(&dws->lock, flags);
686 return 0;
687 }
688
689 /* This may be called twice for each spi dev */
690 static int dw_spi_setup(struct spi_device *spi)
691 {
692 struct dw_spi_chip *chip_info = NULL;
693 struct chip_data *chip;
694
695 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
696 return -EINVAL;
697
698 /* Only alloc on first setup */
699 chip = spi_get_ctldata(spi);
700 if (!chip) {
701 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
702 if (!chip)
703 return -ENOMEM;
704 }
705
706 /*
707 * Protocol drivers may change the chip settings, so...
708 * if chip_info exists, use it
709 */
710 chip_info = spi->controller_data;
711
712 /* chip_info doesn't always exist */
713 if (chip_info) {
714 if (chip_info->cs_control)
715 chip->cs_control = chip_info->cs_control;
716
717 chip->poll_mode = chip_info->poll_mode;
718 chip->type = chip_info->type;
719
720 chip->rx_threshold = 0;
721 chip->tx_threshold = 0;
722
723 chip->enable_dma = chip_info->enable_dma;
724 }
725
726 if (spi->bits_per_word <= 8) {
727 chip->n_bytes = 1;
728 chip->dma_width = 1;
729 chip->read = u8_reader;
730 chip->write = u8_writer;
731 } else if (spi->bits_per_word <= 16) {
732 chip->n_bytes = 2;
733 chip->dma_width = 2;
734 chip->read = u16_reader;
735 chip->write = u16_writer;
736 } else {
737 /* Never take >16b case for MRST SPIC */
738 dev_err(&spi->dev, "invalid wordsize\n");
739 return -EINVAL;
740 }
741 chip->bits_per_word = spi->bits_per_word;
742
743 if (!spi->max_speed_hz) {
744 dev_err(&spi->dev, "No max speed HZ parameter\n");
745 return -EINVAL;
746 }
747 chip->speed_hz = spi->max_speed_hz;
748
749 chip->tmode = 0; /* Tx & Rx */
750 /* Default SPI mode is SCPOL = 0, SCPH = 0 */
751 chip->cr0 = (chip->bits_per_word - 1)
752 | (chip->type << SPI_FRF_OFFSET)
753 | (spi->mode << SPI_MODE_OFFSET)
754 | (chip->tmode << SPI_TMOD_OFFSET);
755
756 spi_set_ctldata(spi, chip);
757 return 0;
758 }
759
760 static void dw_spi_cleanup(struct spi_device *spi)
761 {
762 struct chip_data *chip = spi_get_ctldata(spi);
763 kfree(chip);
764 }
765
766 static int __devinit init_queue(struct dw_spi *dws)
767 {
768 INIT_LIST_HEAD(&dws->queue);
769 spin_lock_init(&dws->lock);
770
771 dws->run = QUEUE_STOPPED;
772 dws->busy = 0;
773
774 tasklet_init(&dws->pump_transfers,
775 pump_transfers, (unsigned long)dws);
776
777 INIT_WORK(&dws->pump_messages, pump_messages);
778 dws->workqueue = create_singlethread_workqueue(
779 dev_name(dws->master->dev.parent));
780 if (dws->workqueue == NULL)
781 return -EBUSY;
782
783 return 0;
784 }
785
786 static int start_queue(struct dw_spi *dws)
787 {
788 unsigned long flags;
789
790 spin_lock_irqsave(&dws->lock, flags);
791
792 if (dws->run == QUEUE_RUNNING || dws->busy) {
793 spin_unlock_irqrestore(&dws->lock, flags);
794 return -EBUSY;
795 }
796
797 dws->run = QUEUE_RUNNING;
798 dws->cur_msg = NULL;
799 dws->cur_transfer = NULL;
800 dws->cur_chip = NULL;
801 dws->prev_chip = NULL;
802 spin_unlock_irqrestore(&dws->lock, flags);
803
804 queue_work(dws->workqueue, &dws->pump_messages);
805
806 return 0;
807 }
808
809 static int stop_queue(struct dw_spi *dws)
810 {
811 unsigned long flags;
812 unsigned limit = 50;
813 int status = 0;
814
815 spin_lock_irqsave(&dws->lock, flags);
816 dws->run = QUEUE_STOPPED;
817 while (!list_empty(&dws->queue) && dws->busy && limit--) {
818 spin_unlock_irqrestore(&dws->lock, flags);
819 msleep(10);
820 spin_lock_irqsave(&dws->lock, flags);
821 }
822
823 if (!list_empty(&dws->queue) || dws->busy)
824 status = -EBUSY;
825 spin_unlock_irqrestore(&dws->lock, flags);
826
827 return status;
828 }
829
830 static int destroy_queue(struct dw_spi *dws)
831 {
832 int status;
833
834 status = stop_queue(dws);
835 if (status != 0)
836 return status;
837 destroy_workqueue(dws->workqueue);
838 return 0;
839 }
840
841 /* Restart the controller, disable all interrupts, clean rx fifo */
842 static void spi_hw_init(struct dw_spi *dws)
843 {
844 spi_enable_chip(dws, 0);
845 spi_mask_intr(dws, 0xff);
846 spi_enable_chip(dws, 1);
847 flush(dws);
848
849 /*
850 * Try to detect the FIFO depth if not set by interface driver,
851 * the depth could be from 2 to 256 from HW spec
852 */
853 if (!dws->fifo_len) {
854 u32 fifo;
855 for (fifo = 2; fifo <= 257; fifo++) {
856 dw_writew(dws, txfltr, fifo);
857 if (fifo != dw_readw(dws, txfltr))
858 break;
859 }
860
861 dws->fifo_len = (fifo == 257) ? 0 : fifo;
862 dw_writew(dws, txfltr, 0);
863 }
864 }
865
866 int __devinit dw_spi_add_host(struct dw_spi *dws)
867 {
868 struct spi_master *master;
869 int ret;
870
871 BUG_ON(dws == NULL);
872
873 master = spi_alloc_master(dws->parent_dev, 0);
874 if (!master) {
875 ret = -ENOMEM;
876 goto exit;
877 }
878
879 dws->master = master;
880 dws->type = SSI_MOTO_SPI;
881 dws->prev_chip = NULL;
882 dws->dma_inited = 0;
883 dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
884
885 ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED,
886 "dw_spi", dws);
887 if (ret < 0) {
888 dev_err(&master->dev, "can not get IRQ\n");
889 goto err_free_master;
890 }
891
892 master->mode_bits = SPI_CPOL | SPI_CPHA;
893 master->bus_num = dws->bus_num;
894 master->num_chipselect = dws->num_cs;
895 master->cleanup = dw_spi_cleanup;
896 master->setup = dw_spi_setup;
897 master->transfer = dw_spi_transfer;
898
899 dws->dma_inited = 0;
900
901 /* Basic HW init */
902 spi_hw_init(dws);
903
904 /* Initial and start queue */
905 ret = init_queue(dws);
906 if (ret) {
907 dev_err(&master->dev, "problem initializing queue\n");
908 goto err_diable_hw;
909 }
910 ret = start_queue(dws);
911 if (ret) {
912 dev_err(&master->dev, "problem starting queue\n");
913 goto err_diable_hw;
914 }
915
916 spi_master_set_devdata(master, dws);
917 ret = spi_register_master(master);
918 if (ret) {
919 dev_err(&master->dev, "problem registering spi master\n");
920 goto err_queue_alloc;
921 }
922
923 mrst_spi_debugfs_init(dws);
924 return 0;
925
926 err_queue_alloc:
927 destroy_queue(dws);
928 err_diable_hw:
929 spi_enable_chip(dws, 0);
930 free_irq(dws->irq, dws);
931 err_free_master:
932 spi_master_put(master);
933 exit:
934 return ret;
935 }
936 EXPORT_SYMBOL(dw_spi_add_host);
937
938 void __devexit dw_spi_remove_host(struct dw_spi *dws)
939 {
940 int status = 0;
941
942 if (!dws)
943 return;
944 mrst_spi_debugfs_remove(dws);
945
946 /* Remove the queue */
947 status = destroy_queue(dws);
948 if (status != 0)
949 dev_err(&dws->master->dev, "dw_spi_remove: workqueue will not "
950 "complete, message memory not freed\n");
951
952 spi_enable_chip(dws, 0);
953 /* Disable clk */
954 spi_set_clk(dws, 0);
955 free_irq(dws->irq, dws);
956
957 /* Disconnect from the SPI framework */
958 spi_unregister_master(dws->master);
959 }
960 EXPORT_SYMBOL(dw_spi_remove_host);
961
962 int dw_spi_suspend_host(struct dw_spi *dws)
963 {
964 int ret = 0;
965
966 ret = stop_queue(dws);
967 if (ret)
968 return ret;
969 spi_enable_chip(dws, 0);
970 spi_set_clk(dws, 0);
971 return ret;
972 }
973 EXPORT_SYMBOL(dw_spi_suspend_host);
974
975 int dw_spi_resume_host(struct dw_spi *dws)
976 {
977 int ret;
978
979 spi_hw_init(dws);
980 ret = start_queue(dws);
981 if (ret)
982 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
983 return ret;
984 }
985 EXPORT_SYMBOL(dw_spi_resume_host);
986
987 MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
988 MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
989 MODULE_LICENSE("GPL v2");
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