include/linux/mfd/mc13783-private.h

   1 /*
   2  * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
   3  *
   4  * Initial development of this code was funded by
   5  * Phytec Messtechnik GmbH, http://www.phytec.de
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20  */
  21
  22 #ifndef __LINUX_MFD_MC13783_PRIV_H
  23 #define __LINUX_MFD_MC13783_PRIV_H
  24
  25 #include <linux/platform_device.h>
  26 #include <linux/mfd/mc13783.h>
  27 #include <linux/workqueue.h>
  28 #include <linux/mutex.h>
  29
  30 struct mc13783_irq {
  31         void (*handler)(int, void *);
  32         void *data;
  33 };
  34
  35 #define MC13783_NUM_IRQ         2
  36 #define MC13783_IRQ_TS          0
  37 #define MC13783_IRQ_REGULATOR   1
  38
  39 #define MC13783_ADC_MODE_TS             1
  40 #define MC13783_ADC_MODE_SINGLE_CHAN    2
  41 #define MC13783_ADC_MODE_MULT_CHAN      3
  42
  43 struct mc13783 {
  44         int revision;
  45         struct device *dev;
  46         struct spi_device *spi_device;
  47
  48         int (*read_dev)(void *data, char reg, int count, u32 *dst);
  49         int (*write_dev)(void *data, char reg, int count, const u32 *src);
  50
  51         struct mutex io_lock;
  52         void *io_data;
  53         int irq;
  54         unsigned int flags;
  55
  56         struct mc13783_irq irq_handler[MC13783_NUM_IRQ];
  57         struct work_struct work;
  58         struct completion adc_done;
  59         unsigned int ts_active;
  60         struct mutex adc_conv_lock;
  61
  62         struct mc13783_regulator_init_data *regulators;
  63         int num_regulators;
  64 };
  65
  66 int mc13783_reg_read(struct mc13783 *, int reg_num, u32 *);
  67 int mc13783_reg_write(struct mc13783 *, int, u32);
  68 int mc13783_set_bits(struct mc13783 *, int, u32, u32);
  69 int mc13783_free_irq(struct mc13783 *mc13783, int irq);
  70 int mc13783_register_irq(struct mc13783 *mc13783, int irq,
  71                 void (*handler) (int, void *), void *data);
  72
  73 #define MC13783_REG_INTERRUPT_STATUS_0           0
  74 #define MC13783_REG_INTERRUPT_MASK_0             1
  75 #define MC13783_REG_INTERRUPT_SENSE_0            2
  76 #define MC13783_REG_INTERRUPT_STATUS_1           3
  77 #define MC13783_REG_INTERRUPT_MASK_1             4
  78 #define MC13783_REG_INTERRUPT_SENSE_1            5
  79 #define MC13783_REG_POWER_UP_MODE_SENSE          6
  80 #define MC13783_REG_REVISION                     7
  81 #define MC13783_REG_SEMAPHORE                    8
  82 #define MC13783_REG_ARBITRATION_PERIPHERAL_AUDIO 9
  83 #define MC13783_REG_ARBITRATION_SWITCHERS       10
  84 #define MC13783_REG_ARBITRATION_REGULATORS_0    11
  85 #define MC13783_REG_ARBITRATION_REGULATORS_1    12
  86 #define MC13783_REG_POWER_CONTROL_0             13
  87 #define MC13783_REG_POWER_CONTROL_1             14
  88 #define MC13783_REG_POWER_CONTROL_2             15
  89 #define MC13783_REG_REGEN_ASSIGNMENT            16
  90 #define MC13783_REG_CONTROL_SPARE               17
  91 #define MC13783_REG_MEMORY_A                    18
  92 #define MC13783_REG_MEMORY_B                    19
  93 #define MC13783_REG_RTC_TIME                    20
  94 #define MC13783_REG_RTC_ALARM                   21
  95 #define MC13783_REG_RTC_DAY                     22
  96 #define MC13783_REG_RTC_DAY_ALARM               23
  97 #define MC13783_REG_SWITCHERS_0                 24
  98 #define MC13783_REG_SWITCHERS_1                 25
  99 #define MC13783_REG_SWITCHERS_2                 26
 100 #define MC13783_REG_SWITCHERS_3                 27
 101 #define MC13783_REG_SWITCHERS_4                 28
 102 #define MC13783_REG_SWITCHERS_5                 29
 103 #define MC13783_REG_REGULATOR_SETTING_0         30
 104 #define MC13783_REG_REGULATOR_SETTING_1         31
 105 #define MC13783_REG_REGULATOR_MODE_0            32
 106 #define MC13783_REG_REGULATOR_MODE_1            33
 107 #define MC13783_REG_POWER_MISCELLANEOUS         34
 108 #define MC13783_REG_POWER_SPARE                 35
 109 #define MC13783_REG_AUDIO_RX_0                  36
 110 #define MC13783_REG_AUDIO_RX_1                  37
 111 #define MC13783_REG_AUDIO_TX                    38
 112 #define MC13783_REG_AUDIO_SSI_NETWORK           39
 113 #define MC13783_REG_AUDIO_CODEC                 40
 114 #define MC13783_REG_AUDIO_STEREO_DAC            41
 115 #define MC13783_REG_AUDIO_SPARE                 42
 116 #define MC13783_REG_ADC_0                       43
 117 #define MC13783_REG_ADC_1                       44
 118 #define MC13783_REG_ADC_2                       45
 119 #define MC13783_REG_ADC_3                       46
 120 #define MC13783_REG_ADC_4                       47
 121 #define MC13783_REG_CHARGER                     48
 122 #define MC13783_REG_USB                         49
 123 #define MC13783_REG_CHARGE_USB_SPARE            50
 124 #define MC13783_REG_LED_CONTROL_0               51
 125 #define MC13783_REG_LED_CONTROL_1               52
 126 #define MC13783_REG_LED_CONTROL_2               53
 127 #define MC13783_REG_LED_CONTROL_3               54
 128 #define MC13783_REG_LED_CONTROL_4               55
 129 #define MC13783_REG_LED_CONTROL_5               56
 130 #define MC13783_REG_SPARE                       57
 131 #define MC13783_REG_TRIM_0                      58
 132 #define MC13783_REG_TRIM_1                      59
 133 #define MC13783_REG_TEST_0                      60
 134 #define MC13783_REG_TEST_1                      61
 135 #define MC13783_REG_TEST_2                      62
 136 #define MC13783_REG_TEST_3                      63
 137 #define MC13783_REG_NB                          64
 138
 139
 140 /*
 141  * Interrupt Status
 142  */
 143 #define MC13783_INT_STAT_ADCDONEI       (1 << 0)
 144 #define MC13783_INT_STAT_ADCBISDONEI    (1 << 1)
 145 #define MC13783_INT_STAT_TSI            (1 << 2)
 146 #define MC13783_INT_STAT_WHIGHI         (1 << 3)
 147 #define MC13783_INT_STAT_WLOWI          (1 << 4)
 148 #define MC13783_INT_STAT_CHGDETI        (1 << 6)
 149 #define MC13783_INT_STAT_CHGOVI         (1 << 7)
 150 #define MC13783_INT_STAT_CHGREVI        (1 << 8)
 151 #define MC13783_INT_STAT_CHGSHORTI      (1 << 9)
 152 #define MC13783_INT_STAT_CCCVI          (1 << 10)
 153 #define MC13783_INT_STAT_CHGCURRI       (1 << 11)
 154 #define MC13783_INT_STAT_BPONI          (1 << 12)
 155 #define MC13783_INT_STAT_LOBATLI        (1 << 13)
 156 #define MC13783_INT_STAT_LOBATHI        (1 << 14)
 157 #define MC13783_INT_STAT_UDPI           (1 << 15)
 158 #define MC13783_INT_STAT_USBI           (1 << 16)
 159 #define MC13783_INT_STAT_IDI            (1 << 19)
 160 #define MC13783_INT_STAT_Unused         (1 << 20)
 161 #define MC13783_INT_STAT_SE1I           (1 << 21)
 162 #define MC13783_INT_STAT_CKDETI         (1 << 22)
 163 #define MC13783_INT_STAT_UDMI           (1 << 23)
 164
 165 /*
 166  * Interrupt Mask
 167  */
 168 #define MC13783_INT_MASK_ADCDONEM       (1 << 0)
 169 #define MC13783_INT_MASK_ADCBISDONEM    (1 << 1)
 170 #define MC13783_INT_MASK_TSM            (1 << 2)
 171 #define MC13783_INT_MASK_WHIGHM         (1 << 3)
 172 #define MC13783_INT_MASK_WLOWM          (1 << 4)
 173 #define MC13783_INT_MASK_CHGDETM        (1 << 6)
 174 #define MC13783_INT_MASK_CHGOVM         (1 << 7)
 175 #define MC13783_INT_MASK_CHGREVM        (1 << 8)
 176 #define MC13783_INT_MASK_CHGSHORTM      (1 << 9)
 177 #define MC13783_INT_MASK_CCCVM          (1 << 10)
 178 #define MC13783_INT_MASK_CHGCURRM       (1 << 11)
 179 #define MC13783_INT_MASK_BPONM          (1 << 12)
 180 #define MC13783_INT_MASK_LOBATLM        (1 << 13)
 181 #define MC13783_INT_MASK_LOBATHM        (1 << 14)
 182 #define MC13783_INT_MASK_UDPM           (1 << 15)
 183 #define MC13783_INT_MASK_USBM           (1 << 16)
 184 #define MC13783_INT_MASK_IDM            (1 << 19)
 185 #define MC13783_INT_MASK_SE1M           (1 << 21)
 186 #define MC13783_INT_MASK_CKDETM         (1 << 22)
 187
 188 /*
 189  * Reg Regulator Mode 0
 190  */
 191 #define MC13783_REGCTRL_VAUDIO_EN       (1 << 0)
 192 #define MC13783_REGCTRL_VAUDIO_STBY     (1 << 1)
 193 #define MC13783_REGCTRL_VAUDIO_MODE     (1 << 2)
 194 #define MC13783_REGCTRL_VIOHI_EN        (1 << 3)
 195 #define MC13783_REGCTRL_VIOHI_STBY      (1 << 4)
 196 #define MC13783_REGCTRL_VIOHI_MODE      (1 << 5)
 197 #define MC13783_REGCTRL_VIOLO_EN        (1 << 6)
 198 #define MC13783_REGCTRL_VIOLO_STBY      (1 << 7)
 199 #define MC13783_REGCTRL_VIOLO_MODE      (1 << 8)
 200 #define MC13783_REGCTRL_VDIG_EN         (1 << 9)
 201 #define MC13783_REGCTRL_VDIG_STBY       (1 << 10)
 202 #define MC13783_REGCTRL_VDIG_MODE       (1 << 11)
 203 #define MC13783_REGCTRL_VGEN_EN         (1 << 12)
 204 #define MC13783_REGCTRL_VGEN_STBY       (1 << 13)
 205 #define MC13783_REGCTRL_VGEN_MODE       (1 << 14)
 206 #define MC13783_REGCTRL_VRFDIG_EN       (1 << 15)
 207 #define MC13783_REGCTRL_VRFDIG_STBY     (1 << 16)
 208 #define MC13783_REGCTRL_VRFDIG_MODE     (1 << 17)
 209 #define MC13783_REGCTRL_VRFREF_EN       (1 << 18)
 210 #define MC13783_REGCTRL_VRFREF_STBY     (1 << 19)
 211 #define MC13783_REGCTRL_VRFREF_MODE     (1 << 20)
 212 #define MC13783_REGCTRL_VRFCP_EN        (1 << 21)
 213 #define MC13783_REGCTRL_VRFCP_STBY      (1 << 22)
 214 #define MC13783_REGCTRL_VRFCP_MODE      (1 << 23)
 215
 216 /*
 217  * Reg Regulator Mode 1
 218  */
 219 #define MC13783_REGCTRL_VSIM_EN         (1 << 0)
 220 #define MC13783_REGCTRL_VSIM_STBY       (1 << 1)
 221 #define MC13783_REGCTRL_VSIM_MODE       (1 << 2)
 222 #define MC13783_REGCTRL_VESIM_EN        (1 << 3)
 223 #define MC13783_REGCTRL_VESIM_STBY      (1 << 4)
 224 #define MC13783_REGCTRL_VESIM_MODE      (1 << 5)
 225 #define MC13783_REGCTRL_VCAM_EN         (1 << 6)
 226 #define MC13783_REGCTRL_VCAM_STBY       (1 << 7)
 227 #define MC13783_REGCTRL_VCAM_MODE       (1 << 8)
 228 #define MC13783_REGCTRL_VRFBG_EN        (1 << 9)
 229 #define MC13783_REGCTRL_VRFBG_STBY      (1 << 10)
 230 #define MC13783_REGCTRL_VVIB_EN         (1 << 11)
 231 #define MC13783_REGCTRL_VRF1_EN         (1 << 12)
 232 #define MC13783_REGCTRL_VRF1_STBY       (1 << 13)
 233 #define MC13783_REGCTRL_VRF1_MODE       (1 << 14)
 234 #define MC13783_REGCTRL_VRF2_EN         (1 << 15)
 235 #define MC13783_REGCTRL_VRF2_STBY       (1 << 16)
 236 #define MC13783_REGCTRL_VRF2_MODE       (1 << 17)
 237 #define MC13783_REGCTRL_VMMC1_EN        (1 << 18)
 238 #define MC13783_REGCTRL_VMMC1_STBY      (1 << 19)
 239 #define MC13783_REGCTRL_VMMC1_MODE      (1 << 20)
 240 #define MC13783_REGCTRL_VMMC2_EN        (1 << 21)
 241 #define MC13783_REGCTRL_VMMC2_STBY      (1 << 22)
 242 #define MC13783_REGCTRL_VMMC2_MODE      (1 << 23)
 243
 244 /*
 245  * Reg Regulator Misc.
 246  */
 247 #define MC13783_REGCTRL_GPO1_EN         (1 << 6)
 248 #define MC13783_REGCTRL_GPO2_EN         (1 << 8)
 249 #define MC13783_REGCTRL_GPO3_EN         (1 << 10)
 250 #define MC13783_REGCTRL_GPO4_EN         (1 << 12)
 251 #define MC13783_REGCTRL_VIBPINCTRL      (1 << 14)
 252
 253 /*
 254  * Reg Switcher 4
 255  */
 256 #define MC13783_SWCTRL_SW1A_MODE        (1 << 0)
 257 #define MC13783_SWCTRL_SW1A_STBY_MODE   (1 << 2)
 258 #define MC13783_SWCTRL_SW1A_DVS_SPEED   (1 << 6)
 259 #define MC13783_SWCTRL_SW1A_PANIC_MODE  (1 << 8)
 260 #define MC13783_SWCTRL_SW1A_SOFTSTART   (1 << 9)
 261 #define MC13783_SWCTRL_SW1B_MODE        (1 << 10)
 262 #define MC13783_SWCTRL_SW1B_STBY_MODE   (1 << 12)
 263 #define MC13783_SWCTRL_SW1B_DVS_SPEED   (1 << 14)
 264 #define MC13783_SWCTRL_SW1B_PANIC_MODE  (1 << 16)
 265 #define MC13783_SWCTRL_SW1B_SOFTSTART   (1 << 17)
 266 #define MC13783_SWCTRL_PLL_EN           (1 << 18)
 267 #define MC13783_SWCTRL_PLL_FACTOR       (1 << 19)
 268
 269 /*
 270  * Reg Switcher 5
 271  */
 272 #define MC13783_SWCTRL_SW2A_MODE        (1 << 0)
 273 #define MC13783_SWCTRL_SW2A_STBY_MODE   (1 << 2)
 274 #define MC13783_SWCTRL_SW2A_DVS_SPEED   (1 << 6)
 275 #define MC13783_SWCTRL_SW2A_PANIC_MODE  (1 << 8)
 276 #define MC13783_SWCTRL_SW2A_SOFTSTART   (1 << 9)
 277 #define MC13783_SWCTRL_SW2B_MODE        (1 << 10)
 278 #define MC13783_SWCTRL_SW2B_STBY_MODE   (1 << 12)
 279 #define MC13783_SWCTRL_SW2B_DVS_SPEED   (1 << 14)
 280 #define MC13783_SWCTRL_SW2B_PANIC_MODE  (1 << 16)
 281 #define MC13783_SWCTRL_SW2B_SOFTSTART   (1 << 17)
 282 #define MC13783_SWSET_SW3               (1 << 18)
 283 #define MC13783_SWCTRL_SW3_EN           (1 << 20)
 284 #define MC13783_SWCTRL_SW3_STBY         (1 << 21)
 285 #define MC13783_SWCTRL_SW3_MODE         (1 << 22)
 286
 287 /*
 288  * ADC/Touch
 289  */
 290 #define MC13783_ADC0_LICELLCON          (1 << 0)
 291 #define MC13783_ADC0_CHRGICON           (1 << 1)
 292 #define MC13783_ADC0_BATICON            (1 << 2)
 293 #define MC13783_ADC0_RTHEN              (1 << 3)
 294 #define MC13783_ADC0_DTHEN              (1 << 4)
 295 #define MC13783_ADC0_UIDEN              (1 << 5)
 296 #define MC13783_ADC0_ADOUTEN            (1 << 6)
 297 #define MC13783_ADC0_ADOUTPER           (1 << 7)
 298 #define MC13783_ADC0_ADREFEN            (1 << 10)
 299 #define MC13783_ADC0_ADREFMODE          (1 << 11)
 300 #define MC13783_ADC0_TSMOD0             (1 << 12)
 301 #define MC13783_ADC0_TSMOD1             (1 << 13)
 302 #define MC13783_ADC0_TSMOD2             (1 << 14)
 303 #define MC13783_ADC0_CHRGRAWDIV         (1 << 15)
 304 #define MC13783_ADC0_ADINC1             (1 << 16)
 305 #define MC13783_ADC0_ADINC2             (1 << 17)
 306 #define MC13783_ADC0_WCOMP              (1 << 18)
 307 #define MC13783_ADC0_ADCBIS0            (1 << 23)
 308
 309 #define MC13783_ADC1_ADEN               (1 << 0)
 310 #define MC13783_ADC1_RAND               (1 << 1)
 311 #define MC13783_ADC1_ADSEL              (1 << 3)
 312 #define MC13783_ADC1_TRIGMASK           (1 << 4)
 313 #define MC13783_ADC1_ADA10              (1 << 5)
 314 #define MC13783_ADC1_ADA11              (1 << 6)
 315 #define MC13783_ADC1_ADA12              (1 << 7)
 316 #define MC13783_ADC1_ADA20              (1 << 8)
 317 #define MC13783_ADC1_ADA21              (1 << 9)
 318 #define MC13783_ADC1_ADA22              (1 << 10)
 319 #define MC13783_ADC1_ATO0               (1 << 11)
 320 #define MC13783_ADC1_ATO1               (1 << 12)
 321 #define MC13783_ADC1_ATO2               (1 << 13)
 322 #define MC13783_ADC1_ATO3               (1 << 14)
 323 #define MC13783_ADC1_ATO4               (1 << 15)
 324 #define MC13783_ADC1_ATO5               (1 << 16)
 325 #define MC13783_ADC1_ATO6               (1 << 17)
 326 #define MC13783_ADC1_ATO7               (1 << 18)
 327 #define MC13783_ADC1_ATOX               (1 << 19)
 328 #define MC13783_ADC1_ASC                (1 << 20)
 329 #define MC13783_ADC1_ADTRIGIGN          (1 << 21)
 330 #define MC13783_ADC1_ADONESHOT          (1 << 22)
 331 #define MC13783_ADC1_ADCBIS1            (1 << 23)
 332
 333 #define MC13783_ADC1_CHAN0_SHIFT        5
 334 #define MC13783_ADC1_CHAN1_SHIFT        8
 335
 336 #define MC13783_ADC2_ADD10              (1 << 2)
 337 #define MC13783_ADC2_ADD11              (1 << 3)
 338 #define MC13783_ADC2_ADD12              (1 << 4)
 339 #define MC13783_ADC2_ADD13              (1 << 5)
 340 #define MC13783_ADC2_ADD14              (1 << 6)
 341 #define MC13783_ADC2_ADD15              (1 << 7)
 342 #define MC13783_ADC2_ADD16              (1 << 8)
 343 #define MC13783_ADC2_ADD17              (1 << 9)
 344 #define MC13783_ADC2_ADD18              (1 << 10)
 345 #define MC13783_ADC2_ADD19              (1 << 11)
 346 #define MC13783_ADC2_ADD20              (1 << 14)
 347 #define MC13783_ADC2_ADD21              (1 << 15)
 348 #define MC13783_ADC2_ADD22              (1 << 16)
 349 #define MC13783_ADC2_ADD23              (1 << 17)
 350 #define MC13783_ADC2_ADD24              (1 << 18)
 351 #define MC13783_ADC2_ADD25              (1 << 19)
 352 #define MC13783_ADC2_ADD26              (1 << 20)
 353 #define MC13783_ADC2_ADD27              (1 << 21)
 354 #define MC13783_ADC2_ADD28              (1 << 22)
 355 #define MC13783_ADC2_ADD29              (1 << 23)
 356
 357 #define MC13783_ADC3_WHIGH0             (1 << 0)
 358 #define MC13783_ADC3_WHIGH1             (1 << 1)
 359 #define MC13783_ADC3_WHIGH2             (1 << 2)
 360 #define MC13783_ADC3_WHIGH3             (1 << 3)
 361 #define MC13783_ADC3_WHIGH4             (1 << 4)
 362 #define MC13783_ADC3_WHIGH5             (1 << 5)
 363 #define MC13783_ADC3_ICID0              (1 << 6)
 364 #define MC13783_ADC3_ICID1              (1 << 7)
 365 #define MC13783_ADC3_ICID2              (1 << 8)
 366 #define MC13783_ADC3_WLOW0              (1 << 9)
 367 #define MC13783_ADC3_WLOW1              (1 << 10)
 368 #define MC13783_ADC3_WLOW2              (1 << 11)
 369 #define MC13783_ADC3_WLOW3              (1 << 12)
 370 #define MC13783_ADC3_WLOW4              (1 << 13)
 371 #define MC13783_ADC3_WLOW5              (1 << 14)
 372 #define MC13783_ADC3_ADCBIS2            (1 << 23)
 373
 374 #define MC13783_ADC4_ADDBIS10           (1 << 2)
 375 #define MC13783_ADC4_ADDBIS11           (1 << 3)
 376 #define MC13783_ADC4_ADDBIS12           (1 << 4)
 377 #define MC13783_ADC4_ADDBIS13           (1 << 5)
 378 #define MC13783_ADC4_ADDBIS14           (1 << 6)
 379 #define MC13783_ADC4_ADDBIS15           (1 << 7)
 380 #define MC13783_ADC4_ADDBIS16           (1 << 8)
 381 #define MC13783_ADC4_ADDBIS17           (1 << 9)
 382 #define MC13783_ADC4_ADDBIS18           (1 << 10)
 383 #define MC13783_ADC4_ADDBIS19           (1 << 11)
 384 #define MC13783_ADC4_ADDBIS20           (1 << 14)
 385 #define MC13783_ADC4_ADDBIS21           (1 << 15)
 386 #define MC13783_ADC4_ADDBIS22           (1 << 16)
 387 #define MC13783_ADC4_ADDBIS23           (1 << 17)
 388 #define MC13783_ADC4_ADDBIS24           (1 << 18)
 389 #define MC13783_ADC4_ADDBIS25           (1 << 19)
 390 #define MC13783_ADC4_ADDBIS26           (1 << 20)
 391 #define MC13783_ADC4_ADDBIS27           (1 << 21)
 392 #define MC13783_ADC4_ADDBIS28           (1 << 22)
 393 #define MC13783_ADC4_ADDBIS29           (1 << 23)
 394
 395 #endif /* __LINUX_MFD_MC13783_PRIV_H */
 396