The x86 timer interrupt handler is the only handler not traced in the
[linux-2.6/next.git] / arch / mips / include / asm / mach-loongson / cpu-feature-overrides.h
blob675bd8641d5a1efc0df38c258d7343c5eddcdb1e
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
6 * Copyright (C) 2009 Wu Zhangjin <wuzhangjin@gmail.com>
7 * Copyright (C) 2009 Philippe Vachon <philippe@cowpig.ca>
8 * Copyright (C) 2009 Zhang Le <r0bertz@gentoo.org>
10 * reference: /proc/cpuinfo,
11 * arch/mips/kernel/cpu-probe.c(cpu_probe_legacy),
12 * arch/mips/kernel/proc.c(show_cpuinfo),
13 * loongson2f user manual.
16 #ifndef __ASM_MACH_LOONGSON_CPU_FEATURE_OVERRIDES_H
17 #define __ASM_MACH_LOONGSON_CPU_FEATURE_OVERRIDES_H
19 #define cpu_dcache_line_size() 32
20 #define cpu_icache_line_size() 32
21 #define cpu_scache_line_size() 32
24 #define cpu_has_32fpr 1
25 #define cpu_has_3k_cache 0
26 #define cpu_has_4k_cache 1
27 #define cpu_has_4kex 1
28 #define cpu_has_64bits 1
29 #define cpu_has_cache_cdex_p 0
30 #define cpu_has_cache_cdex_s 0
31 #define cpu_has_counter 1
32 #define cpu_has_dc_aliases (PAGE_SIZE < 0x4000)
33 #define cpu_has_divec 0
34 #define cpu_has_dsp 0
35 #define cpu_has_ejtag 0
36 #define cpu_has_fpu 1
37 #define cpu_has_ic_fills_f_dc 0
38 #define cpu_has_inclusive_pcaches 1
39 #define cpu_has_llsc 1
40 #define cpu_has_mcheck 0
41 #define cpu_has_mdmx 0
42 #define cpu_has_mips16 0
43 #define cpu_has_mips32r1 0
44 #define cpu_has_mips32r2 0
45 #define cpu_has_mips3d 0
46 #define cpu_has_mips64r1 0
47 #define cpu_has_mips64r2 0
48 #define cpu_has_mipsmt 0
49 #define cpu_has_prefetch 0
50 #define cpu_has_smartmips 0
51 #define cpu_has_tlb 1
52 #define cpu_has_tx39_cache 0
53 #define cpu_has_userlocal 0
54 #define cpu_has_vce 0
55 #define cpu_has_veic 0
56 #define cpu_has_vint 0
57 #define cpu_has_vtag_icache 0
58 #define cpu_has_watch 1
60 #endif /* __ASM_MACH_LOONGSON_CPU_FEATURE_OVERRIDES_H */