arch/ppc/platforms/cpci690.h

   1 /*
   2  * arch/ppc/platforms/cpci690.h
   3  *
   4  * Definitions for Force CPCI690
   5  *
   6  * Author: Mark A. Greer <mgreer@mvista.com>
   7  *
   8  * 2003 (c) MontaVista, Software, Inc.  This file is licensed under
   9  * the terms of the GNU General Public License version 2.  This program
  10  * is licensed "as is" without any warranty of any kind, whether express
  11  * or implied.
  12  */
  13
  14 /*
  15  * The GT64260 has 2 PCI buses each with 1 window from the CPU bus to
  16  * PCI I/O space and 4 windows from the CPU bus to PCI MEM space.
  17  */
  18
  19 #ifndef __PPC_PLATFORMS_CPCI690_H
  20 #define __PPC_PLATFORMS_CPCI690_H
  21
  22 /*
  23  * Define bd_t to pass in the MAC addresses used by the GT64260's enet ctlrs.
  24  */
  25 #define CPCI690_BI_MAGIC                0xFE8765DC
  26
  27 typedef struct board_info {
  28         u32     bi_magic;
  29         u8      bi_enetaddr[3][6];
  30 } bd_t;
  31
  32 /* PCI bus Resource setup */
  33 #define CPCI690_PCI0_MEM_START_PROC_ADDR        0x80000000
  34 #define CPCI690_PCI0_MEM_START_PCI_HI_ADDR      0x00000000
  35 #define CPCI690_PCI0_MEM_START_PCI_LO_ADDR      0x80000000
  36 #define CPCI690_PCI0_MEM_SIZE                   0x10000000
  37 #define CPCI690_PCI0_IO_START_PROC_ADDR         0xa0000000
  38 #define CPCI690_PCI0_IO_START_PCI_ADDR          0x00000000
  39 #define CPCI690_PCI0_IO_SIZE                    0x01000000
  40
  41 #define CPCI690_PCI1_MEM_START_PROC_ADDR        0x90000000
  42 #define CPCI690_PCI1_MEM_START_PCI_HI_ADDR      0x00000000
  43 #define CPCI690_PCI1_MEM_START_PCI_LO_ADDR      0x90000000
  44 #define CPCI690_PCI1_MEM_SIZE                   0x10000000
  45 #define CPCI690_PCI1_IO_START_PROC_ADDR         0xa1000000
  46 #define CPCI690_PCI1_IO_START_PCI_ADDR          0x01000000
  47 #define CPCI690_PCI1_IO_SIZE                    0x01000000
  48
  49 /* Board Registers */
  50 #define CPCI690_BR_BASE                         0xf0000000
  51 #define CPCI690_BR_SIZE_ACTUAL                  0x8
  52 #define CPCI690_BR_SIZE                 max(GT64260_WINDOW_SIZE_MIN,    \
  53                                                 CPCI690_BR_SIZE_ACTUAL)
  54 #define CPCI690_BR_LED_CNTL                     0x00
  55 #define CPCI690_BR_SW_RESET                     0x01
  56 #define CPCI690_BR_MISC_STATUS                  0x02
  57 #define CPCI690_BR_SWITCH_STATUS                0x03
  58 #define CPCI690_BR_MEM_CTLR                     0x04
  59 #define CPCI690_BR_LAST_RESET_1                 0x05
  60 #define CPCI690_BR_LAST_RESET_2                 0x06
  61
  62 #define CPCI690_TODC_BASE                       0xf0100000
  63 #define CPCI690_TODC_SIZE_ACTUAL                0x8000 /* Size or NVRAM + RTC */
  64 #define CPCI690_TODC_SIZE               max(GT64260_WINDOW_SIZE_MIN,    \
  65                                                 CPCI690_TODC_SIZE_ACTUAL)
  66 #define CPCI690_MAC_OFFSET                      0x7c10 /* MAC in RTC NVRAM */
  67
  68 #define CPCI690_IPMI_BASE                       0xf0200000
  69 #define CPCI690_IPMI_SIZE_ACTUAL                0x10 /* 16 bytes of IPMI */
  70 #define CPCI690_IPMI_SIZE               max(GT64260_WINDOW_SIZE_MIN,    \
  71                                                 CPCI690_IPMI_SIZE_ACTUAL)
  72
  73 #define CPCI690_MPSC_BAUD                       9600
  74 #define CPCI690_MPSC_CLK_SRC                    8 /* TCLK */
  75
  76 #define CPCI690_BUS_FREQ                        133333333
  77
  78 #endif /* __PPC_PLATFORMS_CPCI690_H */