include/asm-i386/processor.h

   1 /*
   2  * include/asm-i386/processor.h
   3  *
   4  * Copyright (C) 1994 Linus Torvalds
   5  */
   6
   7 #ifndef __ASM_I386_PROCESSOR_H
   8 #define __ASM_I386_PROCESSOR_H
   9
  10 #include <asm/vm86.h>
  11 #include <asm/math_emu.h>
  12 #include <asm/segment.h>
  13 #include <asm/page.h>
  14 #include <asm/types.h>
  15 #include <asm/sigcontext.h>
  16 #include <asm/cpufeature.h>
  17 #include <asm/msr.h>
  18 #include <asm/system.h>
  19 #include <linux/cache.h>
  20 #include <linux/config.h>
  21 #include <linux/threads.h>
  22 #include <asm/percpu.h>
  23
  24 /* flag for disabling the tsc */
  25 extern int tsc_disable;
  26
  27 struct desc_struct {
  28         unsigned long a,b;
  29 };
  30
  31 #define desc_empty(desc) \
  32                 (!((desc)->a + (desc)->b))
  33
  34 #define desc_equal(desc1, desc2) \
  35                 (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
  36 /*
  37  * Default implementation of macro that returns current
  38  * instruction pointer ("program counter").
  39  */
  40 #define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
  41
  42 /*
  43  *  CPU type and hardware bug flags. Kept separately for each CPU.
  44  *  Members of this structure are referenced in head.S, so think twice
  45  *  before touching them. [mj]
  46  */
  47
  48 struct cpuinfo_x86 {
  49         __u8    x86;            /* CPU family */
  50         __u8    x86_vendor;     /* CPU vendor */
  51         __u8    x86_model;
  52         __u8    x86_mask;
  53         char    wp_works_ok;    /* It doesn't on 386's */
  54         char    hlt_works_ok;   /* Problems on some 486Dx4's and old 386's */
  55         char    hard_math;
  56         char    rfu;
  57         int     cpuid_level;    /* Maximum supported CPUID level, -1=no CPUID */
  58         unsigned long   x86_capability[NCAPINTS];
  59         char    x86_vendor_id[16];
  60         char    x86_model_id[64];
  61         int     x86_cache_size;  /* in KB - valid for CPUS which support this
  62                                     call  */
  63         int     x86_cache_alignment;    /* In bytes */
  64         int     fdiv_bug;
  65         int     f00f_bug;
  66         int     coma_bug;
  67         unsigned long loops_per_jiffy;
  68         unsigned char x86_num_cores;
  69 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
  70
  71 #define X86_VENDOR_INTEL 0
  72 #define X86_VENDOR_CYRIX 1
  73 #define X86_VENDOR_AMD 2
  74 #define X86_VENDOR_UMC 3
  75 #define X86_VENDOR_NEXGEN 4
  76 #define X86_VENDOR_CENTAUR 5
  77 #define X86_VENDOR_RISE 6
  78 #define X86_VENDOR_TRANSMETA 7
  79 #define X86_VENDOR_NSC 8
  80 #define X86_VENDOR_NUM 9
  81 #define X86_VENDOR_UNKNOWN 0xff
  82
  83 /*
  84  * capabilities of CPUs
  85  */
  86
  87 extern struct cpuinfo_x86 boot_cpu_data;
  88 extern struct cpuinfo_x86 new_cpu_data;
  89 extern struct tss_struct doublefault_tss;
  90 DECLARE_PER_CPU(struct tss_struct, init_tss);
  91
  92 #ifdef CONFIG_SMP
  93 extern struct cpuinfo_x86 cpu_data[];
  94 #define current_cpu_data cpu_data[smp_processor_id()]
  95 #else
  96 #define cpu_data (&boot_cpu_data)
  97 #define current_cpu_data boot_cpu_data
  98 #endif
  99
 100 extern  int phys_proc_id[NR_CPUS];
 101 extern char ignore_fpu_irq;
 102
 103 extern void identify_cpu(struct cpuinfo_x86 *);
 104 extern void print_cpu_info(struct cpuinfo_x86 *);
 105 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
 106
 107 #ifdef CONFIG_X86_HT
 108 extern void detect_ht(struct cpuinfo_x86 *c);
 109 #else
 110 static inline void detect_ht(struct cpuinfo_x86 *c) {}
 111 #endif
 112
 113 /*
 114  * EFLAGS bits
 115  */
 116 #define X86_EFLAGS_CF   0x00000001 /* Carry Flag */
 117 #define X86_EFLAGS_PF   0x00000004 /* Parity Flag */
 118 #define X86_EFLAGS_AF   0x00000010 /* Auxillary carry Flag */
 119 #define X86_EFLAGS_ZF   0x00000040 /* Zero Flag */
 120 #define X86_EFLAGS_SF   0x00000080 /* Sign Flag */
 121 #define X86_EFLAGS_TF   0x00000100 /* Trap Flag */
 122 #define X86_EFLAGS_IF   0x00000200 /* Interrupt Flag */
 123 #define X86_EFLAGS_DF   0x00000400 /* Direction Flag */
 124 #define X86_EFLAGS_OF   0x00000800 /* Overflow Flag */
 125 #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
 126 #define X86_EFLAGS_NT   0x00004000 /* Nested Task */
 127 #define X86_EFLAGS_RF   0x00010000 /* Resume Flag */
 128 #define X86_EFLAGS_VM   0x00020000 /* Virtual Mode */
 129 #define X86_EFLAGS_AC   0x00040000 /* Alignment Check */
 130 #define X86_EFLAGS_VIF  0x00080000 /* Virtual Interrupt Flag */
 131 #define X86_EFLAGS_VIP  0x00100000 /* Virtual Interrupt Pending */
 132 #define X86_EFLAGS_ID   0x00200000 /* CPUID detection flag */
 133
 134 /*
 135  * Generic CPUID function
 136  * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
 137  * resulting in stale register contents being returned.
 138  */
 139 static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx)
 140 {
 141         __asm__("cpuid"
 142                 : "=a" (*eax),
 143                   "=b" (*ebx),
 144                   "=c" (*ecx),
 145                   "=d" (*edx)
 146                 : "0" (op), "c"(0));
 147 }
 148
 149 /* Some CPUID calls want 'count' to be placed in ecx */
 150 static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
 151                 int *edx)
 152 {
 153         __asm__("cpuid"
 154                 : "=a" (*eax),
 155                   "=b" (*ebx),
 156                   "=c" (*ecx),
 157                   "=d" (*edx)
 158                 : "0" (op), "c" (count));
 159 }
 160
 161 /*
 162  * CPUID functions returning a single datum
 163  */
 164 static inline unsigned int cpuid_eax(unsigned int op)
 165 {
 166         unsigned int eax;
 167
 168         __asm__("cpuid"
 169                 : "=a" (eax)
 170                 : "0" (op)
 171                 : "bx", "cx", "dx");
 172         return eax;
 173 }
 174 static inline unsigned int cpuid_ebx(unsigned int op)
 175 {
 176         unsigned int eax, ebx;
 177
 178         __asm__("cpuid"
 179                 : "=a" (eax), "=b" (ebx)
 180                 : "0" (op)
 181                 : "cx", "dx" );
 182         return ebx;
 183 }
 184 static inline unsigned int cpuid_ecx(unsigned int op)
 185 {
 186         unsigned int eax, ecx;
 187
 188         __asm__("cpuid"
 189                 : "=a" (eax), "=c" (ecx)
 190                 : "0" (op)
 191                 : "bx", "dx" );
 192         return ecx;
 193 }
 194 static inline unsigned int cpuid_edx(unsigned int op)
 195 {
 196         unsigned int eax, edx;
 197
 198         __asm__("cpuid"
 199                 : "=a" (eax), "=d" (edx)
 200                 : "0" (op)
 201                 : "bx", "cx");
 202         return edx;
 203 }
 204
 205 #define load_cr3(pgdir) \
 206         asm volatile("movl %0,%%cr3": :"r" (__pa(pgdir)))
 207
 208
 209 /*
 210  * Intel CPU features in CR4
 211  */
 212 #define X86_CR4_VME             0x0001  /* enable vm86 extensions */
 213 #define X86_CR4_PVI             0x0002  /* virtual interrupts flag enable */
 214 #define X86_CR4_TSD             0x0004  /* disable time stamp at ipl 3 */
 215 #define X86_CR4_DE              0x0008  /* enable debugging extensions */
 216 #define X86_CR4_PSE             0x0010  /* enable page size extensions */
 217 #define X86_CR4_PAE             0x0020  /* enable physical address extensions */
 218 #define X86_CR4_MCE             0x0040  /* Machine check enable */
 219 #define X86_CR4_PGE             0x0080  /* enable global pages */
 220 #define X86_CR4_PCE             0x0100  /* enable performance counters at ipl 3 */
 221 #define X86_CR4_OSFXSR          0x0200  /* enable fast FPU save and restore */
 222 #define X86_CR4_OSXMMEXCPT      0x0400  /* enable unmasked SSE exceptions */
 223
 224 /*
 225  * Save the cr4 feature set we're using (ie
 226  * Pentium 4MB enable and PPro Global page
 227  * enable), so that any CPU's that boot up
 228  * after us can get the correct flags.
 229  */
 230 extern unsigned long mmu_cr4_features;
 231
 232 static inline void set_in_cr4 (unsigned long mask)
 233 {
 234         mmu_cr4_features |= mask;
 235         __asm__("movl %%cr4,%%eax\n\t"
 236                 "orl %0,%%eax\n\t"
 237                 "movl %%eax,%%cr4\n"
 238                 : : "irg" (mask)
 239                 :"ax");
 240 }
 241
 242 static inline void clear_in_cr4 (unsigned long mask)
 243 {
 244         mmu_cr4_features &= ~mask;
 245         __asm__("movl %%cr4,%%eax\n\t"
 246                 "andl %0,%%eax\n\t"
 247                 "movl %%eax,%%cr4\n"
 248                 : : "irg" (~mask)
 249                 :"ax");
 250 }
 251
 252 /*
 253  *      NSC/Cyrix CPU configuration register indexes
 254  */
 255
 256 #define CX86_PCR0 0x20
 257 #define CX86_GCR  0xb8
 258 #define CX86_CCR0 0xc0
 259 #define CX86_CCR1 0xc1
 260 #define CX86_CCR2 0xc2
 261 #define CX86_CCR3 0xc3
 262 #define CX86_CCR4 0xe8
 263 #define CX86_CCR5 0xe9
 264 #define CX86_CCR6 0xea
 265 #define CX86_CCR7 0xeb
 266 #define CX86_PCR1 0xf0
 267 #define CX86_DIR0 0xfe
 268 #define CX86_DIR1 0xff
 269 #define CX86_ARR_BASE 0xc4
 270 #define CX86_RCR_BASE 0xdc
 271
 272 /*
 273  *      NSC/Cyrix CPU indexed register access macros
 274  */
 275
 276 #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
 277
 278 #define setCx86(reg, data) do { \
 279         outb((reg), 0x22); \
 280         outb((data), 0x23); \
 281 } while (0)
 282
 283 static inline void __monitor(const void *eax, unsigned long ecx,
 284                 unsigned long edx)
 285 {
 286         /* "monitor %eax,%ecx,%edx;" */
 287         asm volatile(
 288                 ".byte 0x0f,0x01,0xc8;"
 289                 : :"a" (eax), "c" (ecx), "d"(edx));
 290 }
 291
 292 static inline void __mwait(unsigned long eax, unsigned long ecx)
 293 {
 294         /* "mwait %eax,%ecx;" */
 295         asm volatile(
 296                 ".byte 0x0f,0x01,0xc9;"
 297                 : :"a" (eax), "c" (ecx));
 298 }
 299
 300 /* from system description table in BIOS.  Mostly for MCA use, but
 301 others may find it useful. */
 302 extern unsigned int machine_id;
 303 extern unsigned int machine_submodel_id;
 304 extern unsigned int BIOS_revision;
 305 extern unsigned int mca_pentium_flag;
 306
 307 /* Boot loader type from the setup header */
 308 extern int bootloader_type;
 309
 310 /*
 311  * User space process size: 3GB (default).
 312  */
 313 #define TASK_SIZE       (PAGE_OFFSET)
 314
 315 /* This decides where the kernel will search for a free chunk of vm
 316  * space during mmap's.
 317  */
 318 #define TASK_UNMAPPED_BASE      (PAGE_ALIGN(TASK_SIZE / 3))
 319
 320 #define HAVE_ARCH_PICK_MMAP_LAYOUT
 321
 322 /*
 323  * Size of io_bitmap.
 324  */
 325 #define IO_BITMAP_BITS  65536
 326 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
 327 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
 328 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
 329 #define INVALID_IO_BITMAP_OFFSET 0x8000
 330 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
 331
 332 struct i387_fsave_struct {
 333         long    cwd;
 334         long    swd;
 335         long    twd;
 336         long    fip;
 337         long    fcs;
 338         long    foo;
 339         long    fos;
 340         long    st_space[20];   /* 8*10 bytes for each FP-reg = 80 bytes */
 341         long    status;         /* software status information */
 342 };
 343
 344 struct i387_fxsave_struct {
 345         unsigned short  cwd;
 346         unsigned short  swd;
 347         unsigned short  twd;
 348         unsigned short  fop;
 349         long    fip;
 350         long    fcs;
 351         long    foo;
 352         long    fos;
 353         long    mxcsr;
 354         long    mxcsr_mask;
 355         long    st_space[32];   /* 8*16 bytes for each FP-reg = 128 bytes */
 356         long    xmm_space[32];  /* 8*16 bytes for each XMM-reg = 128 bytes */
 357         long    padding[56];
 358 } __attribute__ ((aligned (16)));
 359
 360 struct i387_soft_struct {
 361         long    cwd;
 362         long    swd;
 363         long    twd;
 364         long    fip;
 365         long    fcs;
 366         long    foo;
 367         long    fos;
 368         long    st_space[20];   /* 8*10 bytes for each FP-reg = 80 bytes */
 369         unsigned char   ftop, changed, lookahead, no_update, rm, alimit;
 370         struct info     *info;
 371         unsigned long   entry_eip;
 372 };
 373
 374 union i387_union {
 375         struct i387_fsave_struct        fsave;
 376         struct i387_fxsave_struct       fxsave;
 377         struct i387_soft_struct soft;
 378 };
 379
 380 typedef struct {
 381         unsigned long seg;
 382 } mm_segment_t;
 383
 384 struct thread_struct;
 385
 386 struct tss_struct {
 387         unsigned short  back_link,__blh;
 388         unsigned long   esp0;
 389         unsigned short  ss0,__ss0h;
 390         unsigned long   esp1;
 391         unsigned short  ss1,__ss1h;     /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
 392         unsigned long   esp2;
 393         unsigned short  ss2,__ss2h;
 394         unsigned long   __cr3;
 395         unsigned long   eip;
 396         unsigned long   eflags;
 397         unsigned long   eax,ecx,edx,ebx;
 398         unsigned long   esp;
 399         unsigned long   ebp;
 400         unsigned long   esi;
 401         unsigned long   edi;
 402         unsigned short  es, __esh;
 403         unsigned short  cs, __csh;
 404         unsigned short  ss, __ssh;
 405         unsigned short  ds, __dsh;
 406         unsigned short  fs, __fsh;
 407         unsigned short  gs, __gsh;
 408         unsigned short  ldt, __ldth;
 409         unsigned short  trace, io_bitmap_base;
 410         /*
 411          * The extra 1 is there because the CPU will access an
 412          * additional byte beyond the end of the IO permission
 413          * bitmap. The extra byte must be all 1 bits, and must
 414          * be within the limit.
 415          */
 416         unsigned long   io_bitmap[IO_BITMAP_LONGS + 1];
 417         /*
 418          * Cache the current maximum and the last task that used the bitmap:
 419          */
 420         unsigned long io_bitmap_max;
 421         struct thread_struct *io_bitmap_owner;
 422         /*
 423          * pads the TSS to be cacheline-aligned (size is 0x100)
 424          */
 425         unsigned long __cacheline_filler[35];
 426         /*
 427          * .. and then another 0x100 bytes for emergency kernel stack
 428          */
 429         unsigned long stack[64];
 430 } __attribute__((packed));
 431
 432 #define ARCH_MIN_TASKALIGN      16
 433
 434 struct thread_struct {
 435 /* cached TLS descriptors. */
 436         struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
 437         unsigned long   esp0;
 438         unsigned long   sysenter_cs;
 439         unsigned long   eip;
 440         unsigned long   esp;
 441         unsigned long   fs;
 442         unsigned long   gs;
 443 /* Hardware debugging registers */
 444         unsigned long   debugreg[8];  /* %%db0-7 debug registers */
 445 /* fault info */
 446         unsigned long   cr2, trap_no, error_code;
 447 /* floating point info */
 448         union i387_union        i387;
 449 /* virtual 86 mode info */
 450         struct vm86_struct __user * vm86_info;
 451         unsigned long           screen_bitmap;
 452         unsigned long           v86flags, v86mask, saved_esp0;
 453         unsigned int            saved_fs, saved_gs;
 454 /* IO permissions */
 455         unsigned long   *io_bitmap_ptr;
 456 /* max allowed port in the bitmap, in bytes: */
 457         unsigned long   io_bitmap_max;
 458 };
 459
 460 #define INIT_THREAD  {                                                  \
 461         .vm86_info = NULL,                                              \
 462         .sysenter_cs = __KERNEL_CS,                                     \
 463         .io_bitmap_ptr = NULL,                                          \
 464 }
 465
 466 /*
 467  * Note that the .io_bitmap member must be extra-big. This is because
 468  * the CPU will access an additional byte beyond the end of the IO
 469  * permission bitmap. The extra byte must be all 1 bits, and must
 470  * be within the limit.
 471  */
 472 #define INIT_TSS  {                                                     \
 473         .esp0           = sizeof(init_stack) + (long)&init_stack,       \
 474         .ss0            = __KERNEL_DS,                                  \
 475         .ss1            = __KERNEL_CS,                                  \
 476         .ldt            = GDT_ENTRY_LDT,                                \
 477         .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,                     \
 478         .io_bitmap      = { [ 0 ... IO_BITMAP_LONGS] = ~0 },            \
 479 }
 480
 481 static inline void load_esp0(struct tss_struct *tss, struct thread_struct *thread)
 482 {
 483         tss->esp0 = thread->esp0;
 484         /* This can only happen when SEP is enabled, no need to test "SEP"arately */
 485         if (unlikely(tss->ss1 != thread->sysenter_cs)) {
 486                 tss->ss1 = thread->sysenter_cs;
 487                 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
 488         }
 489 }
 490
 491 #define start_thread(regs, new_eip, new_esp) do {               \
 492         __asm__("movl %0,%%fs ; movl %0,%%gs": :"r" (0));       \
 493         set_fs(USER_DS);                                        \
 494         regs->xds = __USER_DS;                                  \
 495         regs->xes = __USER_DS;                                  \
 496         regs->xss = __USER_DS;                                  \
 497         regs->xcs = __USER_CS;                                  \
 498         regs->eip = new_eip;                                    \
 499         regs->esp = new_esp;                                    \
 500 } while (0)
 501
 502 /* Forward declaration, a strange C thing */
 503 struct task_struct;
 504 struct mm_struct;
 505
 506 /* Free all resources held by a thread. */
 507 extern void release_thread(struct task_struct *);
 508
 509 /* Prepare to copy thread state - unlazy all lazy status */
 510 extern void prepare_to_copy(struct task_struct *tsk);
 511
 512 /*
 513  * create a kernel thread without removing it from tasklists
 514  */
 515 extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
 516
 517 extern unsigned long thread_saved_pc(struct task_struct *tsk);
 518 void show_trace(struct task_struct *task, unsigned long *stack);
 519
 520 unsigned long get_wchan(struct task_struct *p);
 521
 522 #define THREAD_SIZE_LONGS      (THREAD_SIZE/sizeof(unsigned long))
 523 #define KSTK_TOP(info)                                                 \
 524 ({                                                                     \
 525        unsigned long *__ptr = (unsigned long *)(info);                 \
 526        (unsigned long)(&__ptr[THREAD_SIZE_LONGS]);                     \
 527 })
 528
 529 #define task_pt_regs(task)                                             \
 530 ({                                                                     \
 531        struct pt_regs *__regs__;                                       \
 532        __regs__ = (struct pt_regs *)KSTK_TOP((task)->thread_info);     \
 533        __regs__ - 1;                                                   \
 534 })
 535
 536 #define KSTK_EIP(task) (task_pt_regs(task)->eip)
 537 #define KSTK_ESP(task) (task_pt_regs(task)->esp)
 538
 539
 540 struct microcode_header {
 541         unsigned int hdrver;
 542         unsigned int rev;
 543         unsigned int date;
 544         unsigned int sig;
 545         unsigned int cksum;
 546         unsigned int ldrver;
 547         unsigned int pf;
 548         unsigned int datasize;
 549         unsigned int totalsize;
 550         unsigned int reserved[3];
 551 };
 552
 553 struct microcode {
 554         struct microcode_header hdr;
 555         unsigned int bits[0];
 556 };
 557
 558 typedef struct microcode microcode_t;
 559 typedef struct microcode_header microcode_header_t;
 560
 561 /* microcode format is extended from prescott processors */
 562 struct extended_signature {
 563         unsigned int sig;
 564         unsigned int pf;
 565         unsigned int cksum;
 566 };
 567
 568 struct extended_sigtable {
 569         unsigned int count;
 570         unsigned int cksum;
 571         unsigned int reserved[3];
 572         struct extended_signature sigs[0];
 573 };
 574 /* '6' because it used to be for P6 only (but now covers Pentium 4 as well) */
 575 #define MICROCODE_IOCFREE       _IO('6',0)
 576
 577 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
 578 static inline void rep_nop(void)
 579 {
 580         __asm__ __volatile__("rep;nop": : :"memory");
 581 }
 582
 583 #define cpu_relax()     rep_nop()
 584
 585 /* generic versions from gas */
 586 #define GENERIC_NOP1    ".byte 0x90\n"
 587 #define GENERIC_NOP2            ".byte 0x89,0xf6\n"
 588 #define GENERIC_NOP3        ".byte 0x8d,0x76,0x00\n"
 589 #define GENERIC_NOP4        ".byte 0x8d,0x74,0x26,0x00\n"
 590 #define GENERIC_NOP5        GENERIC_NOP1 GENERIC_NOP4
 591 #define GENERIC_NOP6    ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
 592 #define GENERIC_NOP7    ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
 593 #define GENERIC_NOP8    GENERIC_NOP1 GENERIC_NOP7
 594
 595 /* Opteron nops */
 596 #define K8_NOP1 GENERIC_NOP1
 597 #define K8_NOP2 ".byte 0x66,0x90\n"
 598 #define K8_NOP3 ".byte 0x66,0x66,0x90\n"
 599 #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
 600 #define K8_NOP5 K8_NOP3 K8_NOP2
 601 #define K8_NOP6 K8_NOP3 K8_NOP3
 602 #define K8_NOP7 K8_NOP4 K8_NOP3
 603 #define K8_NOP8 K8_NOP4 K8_NOP4
 604
 605 /* K7 nops */
 606 /* uses eax dependencies (arbitary choice) */
 607 #define K7_NOP1  GENERIC_NOP1
 608 #define K7_NOP2 ".byte 0x8b,0xc0\n"
 609 #define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
 610 #define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
 611 #define K7_NOP5 K7_NOP4 ASM_NOP1
 612 #define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
 613 #define K7_NOP7        ".byte 0x8D,0x04,0x05,0,0,0,0\n"
 614 #define K7_NOP8        K7_NOP7 ASM_NOP1
 615
 616 #ifdef CONFIG_MK8
 617 #define ASM_NOP1 K8_NOP1
 618 #define ASM_NOP2 K8_NOP2
 619 #define ASM_NOP3 K8_NOP3
 620 #define ASM_NOP4 K8_NOP4
 621 #define ASM_NOP5 K8_NOP5
 622 #define ASM_NOP6 K8_NOP6
 623 #define ASM_NOP7 K8_NOP7
 624 #define ASM_NOP8 K8_NOP8
 625 #elif defined(CONFIG_MK7)
 626 #define ASM_NOP1 K7_NOP1
 627 #define ASM_NOP2 K7_NOP2
 628 #define ASM_NOP3 K7_NOP3
 629 #define ASM_NOP4 K7_NOP4
 630 #define ASM_NOP5 K7_NOP5
 631 #define ASM_NOP6 K7_NOP6
 632 #define ASM_NOP7 K7_NOP7
 633 #define ASM_NOP8 K7_NOP8
 634 #else
 635 #define ASM_NOP1 GENERIC_NOP1
 636 #define ASM_NOP2 GENERIC_NOP2
 637 #define ASM_NOP3 GENERIC_NOP3
 638 #define ASM_NOP4 GENERIC_NOP4
 639 #define ASM_NOP5 GENERIC_NOP5
 640 #define ASM_NOP6 GENERIC_NOP6
 641 #define ASM_NOP7 GENERIC_NOP7
 642 #define ASM_NOP8 GENERIC_NOP8
 643 #endif
 644
 645 #define ASM_NOP_MAX 8
 646
 647 /* Prefetch instructions for Pentium III and AMD Athlon */
 648 /* It's not worth to care about 3dnow! prefetches for the K6
 649    because they are microcoded there and very slow.
 650    However we don't do prefetches for pre XP Athlons currently
 651    That should be fixed. */
 652 #define ARCH_HAS_PREFETCH
 653 extern inline void prefetch(const void *x)
 654 {
 655         alternative_input(ASM_NOP4,
 656                           "prefetchnta (%1)",
 657                           X86_FEATURE_XMM,
 658                           "r" (x));
 659 }
 660
 661 #define ARCH_HAS_PREFETCH
 662 #define ARCH_HAS_PREFETCHW
 663 #define ARCH_HAS_SPINLOCK_PREFETCH
 664
 665 /* 3dnow! prefetch to get an exclusive cache line. Useful for
 666    spinlocks to avoid one state transition in the cache coherency protocol. */
 667 extern inline void prefetchw(const void *x)
 668 {
 669         alternative_input(ASM_NOP4,
 670                           "prefetchw (%1)",
 671                           X86_FEATURE_3DNOW,
 672                           "r" (x));
 673 }
 674 #define spin_lock_prefetch(x)   prefetchw(x)
 675
 676 extern void select_idle_routine(const struct cpuinfo_x86 *c);
 677
 678 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
 679
 680 extern unsigned long boot_option_idle_override;
 681
 682 #endif /* __ASM_I386_PROCESSOR_H */