include/asm-ppc/pgtable.h

   1 #ifdef __KERNEL__
   2 #ifndef _PPC_PGTABLE_H
   3 #define _PPC_PGTABLE_H
   4
   5 #include <asm-generic/4level-fixup.h>
   6
   7 #include <linux/config.h>
   8
   9 #ifndef __ASSEMBLY__
  10 #include <linux/sched.h>
  11 #include <linux/threads.h>
  12 #include <asm/processor.h>              /* For TASK_SIZE */
  13 #include <asm/mmu.h>
  14 #include <asm/page.h>
  15
  16 extern unsigned long va_to_phys(unsigned long address);
  17 extern pte_t *va_to_pte(unsigned long address);
  18 extern unsigned long ioremap_bot, ioremap_base;
  19 #endif /* __ASSEMBLY__ */
  20
  21 /*
  22  * The PowerPC MMU uses a hash table containing PTEs, together with
  23  * a set of 16 segment registers (on 32-bit implementations), to define
  24  * the virtual to physical address mapping.
  25  *
  26  * We use the hash table as an extended TLB, i.e. a cache of currently
  27  * active mappings.  We maintain a two-level page table tree, much
  28  * like that used by the i386, for the sake of the Linux memory
  29  * management code.  Low-level assembler code in hashtable.S
  30  * (procedure hash_page) is responsible for extracting ptes from the
  31  * tree and putting them into the hash table when necessary, and
  32  * updating the accessed and modified bits in the page table tree.
  33  */
  34
  35 /*
  36  * The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk.
  37  * We also use the two level tables, but we can put the real bits in them
  38  * needed for the TLB and tablewalk.  These definitions require Mx_CTR.PPM = 0,
  39  * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1.  The level 2 descriptor has
  40  * additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit
  41  * based upon user/super access.  The TLB does not have accessed nor write
  42  * protect.  We assume that if the TLB get loaded with an entry it is
  43  * accessed, and overload the changed bit for write protect.  We use
  44  * two bits in the software pte that are supposed to be set to zero in
  45  * the TLB entry (24 and 25) for these indicators.  Although the level 1
  46  * descriptor contains the guarded and writethrough/copyback bits, we can
  47  * set these at the page level since they get copied from the Mx_TWC
  48  * register when the TLB entry is loaded.  We will use bit 27 for guard, since
  49  * that is where it exists in the MD_TWC, and bit 26 for writethrough.
  50  * These will get masked from the level 2 descriptor at TLB load time, and
  51  * copied to the MD_TWC before it gets loaded.
  52  * Large page sizes added.  We currently support two sizes, 4K and 8M.
  53  * This also allows a TLB hander optimization because we can directly
  54  * load the PMD into MD_TWC.  The 8M pages are only used for kernel
  55  * mapping of well known areas.  The PMD (PGD) entries contain control
  56  * flags in addition to the address, so care must be taken that the
  57  * software no longer assumes these are only pointers.
  58  */
  59
  60 /*
  61  * At present, all PowerPC 400-class processors share a similar TLB
  62  * architecture. The instruction and data sides share a unified,
  63  * 64-entry, fully-associative TLB which is maintained totally under
  64  * software control. In addition, the instruction side has a
  65  * hardware-managed, 4-entry, fully-associative TLB which serves as a
  66  * first level to the shared TLB. These two TLBs are known as the UTLB
  67  * and ITLB, respectively (see "mmu.h" for definitions).
  68  */
  69
  70 /*
  71  * The normal case is that PTEs are 32-bits and we have a 1-page
  72  * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages.  -- paulus
  73  *
  74  * For any >32-bit physical address platform, we can use the following
  75  * two level page table layout where the pgdir is 8KB and the MS 13 bits
  76  * are an index to the second level table.  The combined pgdir/pmd first
  77  * level has 2048 entries and the second level has 512 64-bit PTE entries.
  78  * -Matt
  79  */
  80 /* PMD_SHIFT determines the size of the area mapped by the PTE pages */
  81 #define PMD_SHIFT       (PAGE_SHIFT + PTE_SHIFT)
  82 #define PMD_SIZE        (1UL << PMD_SHIFT)
  83 #define PMD_MASK        (~(PMD_SIZE-1))
  84
  85 /* PGDIR_SHIFT determines what a top-level page table entry can map */
  86 #define PGDIR_SHIFT     PMD_SHIFT
  87 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
  88 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
  89
  90 /*
  91  * entries per page directory level: our page-table tree is two-level, so
  92  * we don't really have any PMD directory.
  93  */
  94 #define PTRS_PER_PTE    (1 << PTE_SHIFT)
  95 #define PTRS_PER_PMD    1
  96 #define PTRS_PER_PGD    (1 << (32 - PGDIR_SHIFT))
  97
  98 #define USER_PTRS_PER_PGD       (TASK_SIZE / PGDIR_SIZE)
  99 #define FIRST_USER_PGD_NR       0
 100
 101 #define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
 102 #define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS)
 103
 104 #define pte_ERROR(e) \
 105         printk("%s:%d: bad pte "PTE_FMT".\n", __FILE__, __LINE__, pte_val(e))
 106 #define pmd_ERROR(e) \
 107         printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
 108 #define pgd_ERROR(e) \
 109         printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
 110
 111 /*
 112  * Just any arbitrary offset to the start of the vmalloc VM area: the
 113  * current 64MB value just means that there will be a 64MB "hole" after the
 114  * physical memory until the kernel virtual memory starts.  That means that
 115  * any out-of-bounds memory accesses will hopefully be caught.
 116  * The vmalloc() routines leaves a hole of 4kB between each vmalloced
 117  * area for the same reason. ;)
 118  *
 119  * We no longer map larger than phys RAM with the BATs so we don't have
 120  * to worry about the VMALLOC_OFFSET causing problems.  We do have to worry
 121  * about clashes between our early calls to ioremap() that start growing down
 122  * from ioremap_base being run into the VM area allocations (growing upwards
 123  * from VMALLOC_START).  For this reason we have ioremap_bot to check when
 124  * we actually run into our mappings setup in the early boot with the VM
 125  * system.  This really does become a problem for machines with good amounts
 126  * of RAM.  -- Cort
 127  */
 128 #define VMALLOC_OFFSET (0x1000000) /* 16M */
 129 #ifdef CONFIG_44x
 130 #include <asm/ibm44x.h>
 131 #define VMALLOC_START (((_ALIGN((long)high_memory, PPC44x_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
 132 #else
 133 #define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
 134 #endif
 135 #define VMALLOC_END     ioremap_bot
 136
 137 /*
 138  * Bits in a linux-style PTE.  These match the bits in the
 139  * (hardware-defined) PowerPC PTE as closely as possible.
 140  */
 141
 142 #if defined(CONFIG_40x)
 143
 144 /* There are several potential gotchas here.  The 40x hardware TLBLO
 145    field looks like this:
 146
 147    0  1  2  3  4  ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31
 148    RPN.....................  0  0 EX WR ZSEL.......  W  I  M  G
 149
 150    Where possible we make the Linux PTE bits match up with this
 151
 152    - bits 20 and 21 must be cleared, because we use 4k pages (40x can
 153      support down to 1k pages), this is done in the TLBMiss exception
 154      handler.
 155    - We use only zones 0 (for kernel pages) and 1 (for user pages)
 156      of the 16 available.  Bit 24-26 of the TLB are cleared in the TLB
 157      miss handler.  Bit 27 is PAGE_USER, thus selecting the correct
 158      zone.
 159    - PRESENT *must* be in the bottom two bits because swap cache
 160      entries use the top 30 bits.  Because 40x doesn't support SMP
 161      anyway, M is irrelevant so we borrow it for PAGE_PRESENT.  Bit 30
 162      is cleared in the TLB miss handler before the TLB entry is loaded.
 163    - All other bits of the PTE are loaded into TLBLO without
 164      modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
 165      software PTE bits.  We actually use use bits 21, 24, 25, and
 166      30 respectively for the software bits: ACCESSED, DIRTY, RW, and
 167      PRESENT.
 168 */
 169
 170 /* Definitions for 40x embedded chips. */
 171 #define _PAGE_GUARDED   0x001   /* G: page is guarded from prefetch */
 172 #define _PAGE_FILE      0x001   /* when !present: nonlinear file mapping */
 173 #define _PAGE_PRESENT   0x002   /* software: PTE contains a translation */
 174 #define _PAGE_NO_CACHE  0x004   /* I: caching is inhibited */
 175 #define _PAGE_WRITETHRU 0x008   /* W: caching is write-through */
 176 #define _PAGE_USER      0x010   /* matches one of the zone permission bits */
 177 #define _PAGE_RW        0x040   /* software: Writes permitted */
 178 #define _PAGE_DIRTY     0x080   /* software: dirty page */
 179 #define _PAGE_HWWRITE   0x100   /* hardware: Dirty & RW, set in exception */
 180 #define _PAGE_HWEXEC    0x200   /* hardware: EX permission */
 181 #define _PAGE_ACCESSED  0x400   /* software: R: page referenced */
 182
 183 #define _PMD_PRESENT    0x400   /* PMD points to page of PTEs */
 184 #define _PMD_BAD        0x802
 185 #define _PMD_SIZE       0x0e0   /* size field, != 0 for large-page PMD entry */
 186 #define _PMD_SIZE_4M    0x0c0
 187 #define _PMD_SIZE_16M   0x0e0
 188 #define PMD_PAGE_SIZE(pmdval)   (1024 << (((pmdval) & _PMD_SIZE) >> 4))
 189
 190 #elif defined(CONFIG_44x)
 191 /*
 192  * Definitions for PPC440
 193  *
 194  * Because of the 3 word TLB entries to support 36-bit addressing,
 195  * the attribute are difficult to map in such a fashion that they
 196  * are easily loaded during exception processing.  I decided to
 197  * organize the entry so the ERPN is the only portion in the
 198  * upper word of the PTE and the attribute bits below are packed
 199  * in as sensibly as they can be in the area below a 4KB page size
 200  * oriented RPN.  This at least makes it easy to load the RPN and
 201  * ERPN fields in the TLB. -Matt
 202  *
 203  * Note that these bits preclude future use of a page size
 204  * less than 4KB.
 205  */
 206 #define _PAGE_PRESENT   0x00000001              /* S: PTE valid */
 207 #define _PAGE_RW        0x00000002              /* S: Write permission */
 208 #define _PAGE_DIRTY     0x00000004              /* S: Page dirty */
 209 #define _PAGE_ACCESSED  0x00000008              /* S: Page referenced */
 210 #define _PAGE_HWWRITE   0x00000010              /* H: Dirty & RW */
 211 #define _PAGE_HWEXEC    0x00000020              /* H: Execute permission */
 212 #define _PAGE_USER      0x00000040              /* S: User page */
 213 #define _PAGE_ENDIAN    0x00000080              /* H: E bit */
 214 #define _PAGE_GUARDED   0x00000100              /* H: G bit */
 215 #define _PAGE_COHERENT  0x00000200              /* H: M bit */
 216 #define _PAGE_FILE      0x00000400              /* S: nonlinear file mapping */
 217 #define _PAGE_NO_CACHE  0x00000400              /* H: I bit */
 218 #define _PAGE_WRITETHRU 0x00000800              /* H: W bit */
 219
 220 /* TODO: Add large page lowmem mapping support */
 221 #define _PMD_PRESENT    0
 222 #define _PMD_PRESENT_MASK (PAGE_MASK)
 223 #define _PMD_BAD        (~PAGE_MASK)
 224
 225 /* ERPN in a PTE never gets cleared, ignore it */
 226 #define _PTE_NONE_MASK  0xffffffff00000000ULL
 227
 228 #elif defined(CONFIG_E500)
 229
 230 /*
 231    MMU Assist Register 3:
 232
 233    32 33 34 35 36  ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63
 234    RPN......................  0  0 U0 U1 U2 U3 UX SX UW SW UR SR
 235
 236    - PRESENT *must* be in the bottom three bits because swap cache
 237      entries use the top 29 bits.
 238
 239    - FILE *must* be in the bottom three bits because swap cache
 240      entries use the top 29 bits.
 241 */
 242
 243 /* Definitions for e500 core */
 244 #define _PAGE_PRESENT   0x001   /* S: PTE contains a translation */
 245 #define _PAGE_USER      0x002   /* S: User page (maps to UR) */
 246 #define _PAGE_FILE      0x002   /* S: when !present: nonlinear file mapping */
 247 #define _PAGE_ACCESSED  0x004   /* S: Page referenced */
 248 #define _PAGE_HWWRITE   0x008   /* H: Dirty & RW, set in exception */
 249 #define _PAGE_RW        0x010   /* S: Write permission */
 250 #define _PAGE_HWEXEC    0x020   /* H: UX permission */
 251
 252 #define _PAGE_ENDIAN    0x040   /* H: E bit */
 253 #define _PAGE_GUARDED   0x080   /* H: G bit */
 254 #define _PAGE_COHERENT  0x100   /* H: M bit */
 255 #define _PAGE_NO_CACHE  0x200   /* H: I bit */
 256 #define _PAGE_WRITETHRU 0x400   /* H: W bit */
 257 #define _PAGE_DIRTY     0x800   /* S: Page dirty */
 258
 259 #define _PMD_PRESENT    0
 260 #define _PMD_PRESENT_MASK (PAGE_MASK)
 261 #define _PMD_BAD        (~PAGE_MASK)
 262
 263 #define NUM_TLBCAMS     (16)
 264
 265 #elif defined(CONFIG_8xx)
 266 /* Definitions for 8xx embedded chips. */
 267 #define _PAGE_PRESENT   0x0001  /* Page is valid */
 268 #define _PAGE_FILE      0x0002  /* when !present: nonlinear file mapping */
 269 #define _PAGE_NO_CACHE  0x0002  /* I: cache inhibit */
 270 #define _PAGE_SHARED    0x0004  /* No ASID (context) compare */
 271
 272 /* These five software bits must be masked out when the entry is loaded
 273  * into the TLB.
 274  */
 275 #define _PAGE_EXEC      0x0008  /* software: i-cache coherency required */
 276 #define _PAGE_GUARDED   0x0010  /* software: guarded access */
 277 #define _PAGE_DIRTY     0x0020  /* software: page changed */
 278 #define _PAGE_RW        0x0040  /* software: user write access allowed */
 279 #define _PAGE_ACCESSED  0x0080  /* software: page referenced */
 280
 281 /* Setting any bits in the nibble with the follow two controls will
 282  * require a TLB exception handler change.  It is assumed unused bits
 283  * are always zero.
 284  */
 285 #define _PAGE_HWWRITE   0x0100  /* h/w write enable: never set in Linux PTE */
 286 #define _PAGE_USER      0x0800  /* One of the PP bits, the other is USER&~RW */
 287
 288 #define _PMD_PRESENT    0x0001
 289 #define _PMD_BAD        0x0ff0
 290 #define _PMD_PAGE_MASK  0x000c
 291 #define _PMD_PAGE_8M    0x000c
 292
 293 /*
 294  * The 8xx TLB miss handler allegedly sets _PAGE_ACCESSED in the PTE
 295  * for an address even if _PAGE_PRESENT is not set, as a performance
 296  * optimization.  This is a bug if you ever want to use swap unless
 297  * _PAGE_ACCESSED is 2, which it isn't, or unless you have 8xx-specific
 298  * definitions for __swp_entry etc. below, which would be gross.
 299  *  -- paulus
 300  */
 301 #define _PTE_NONE_MASK _PAGE_ACCESSED
 302
 303 #else /* CONFIG_6xx */
 304 /* Definitions for 60x, 740/750, etc. */
 305 #define _PAGE_PRESENT   0x001   /* software: pte contains a translation */
 306 #define _PAGE_HASHPTE   0x002   /* hash_page has made an HPTE for this pte */
 307 #define _PAGE_FILE      0x004   /* when !present: nonlinear file mapping */
 308 #define _PAGE_USER      0x004   /* usermode access allowed */
 309 #define _PAGE_GUARDED   0x008   /* G: prohibit speculative access */
 310 #define _PAGE_COHERENT  0x010   /* M: enforce memory coherence (SMP systems) */
 311 #define _PAGE_NO_CACHE  0x020   /* I: cache inhibit */
 312 #define _PAGE_WRITETHRU 0x040   /* W: cache write-through */
 313 #define _PAGE_DIRTY     0x080   /* C: page changed */
 314 #define _PAGE_ACCESSED  0x100   /* R: page referenced */
 315 #define _PAGE_EXEC      0x200   /* software: i-cache coherency required */
 316 #define _PAGE_RW        0x400   /* software: user write access allowed */
 317
 318 #define _PTE_NONE_MASK  _PAGE_HASHPTE
 319
 320 #define _PMD_PRESENT    0
 321 #define _PMD_PRESENT_MASK (PAGE_MASK)
 322 #define _PMD_BAD        (~PAGE_MASK)
 323 #endif
 324
 325 /*
 326  * Some bits are only used on some cpu families...
 327  */
 328 #ifndef _PAGE_HASHPTE
 329 #define _PAGE_HASHPTE   0
 330 #endif
 331 #ifndef _PTE_NONE_MASK
 332 #define _PTE_NONE_MASK 0
 333 #endif
 334 #ifndef _PAGE_SHARED
 335 #define _PAGE_SHARED    0
 336 #endif
 337 #ifndef _PAGE_HWWRITE
 338 #define _PAGE_HWWRITE   0
 339 #endif
 340 #ifndef _PAGE_HWEXEC
 341 #define _PAGE_HWEXEC    0
 342 #endif
 343 #ifndef _PAGE_EXEC
 344 #define _PAGE_EXEC      0
 345 #endif
 346 #ifndef _PMD_PRESENT_MASK
 347 #define _PMD_PRESENT_MASK       _PMD_PRESENT
 348 #endif
 349 #ifndef _PMD_SIZE
 350 #define _PMD_SIZE       0
 351 #define PMD_PAGE_SIZE(pmd)      bad_call_to_PMD_PAGE_SIZE()
 352 #endif
 353
 354 #define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
 355
 356 /*
 357  * Note: the _PAGE_COHERENT bit automatically gets set in the hardware
 358  * PTE if CONFIG_SMP is defined (hash_page does this); there is no need
 359  * to have it in the Linux PTE, and in fact the bit could be reused for
 360  * another purpose.  -- paulus.
 361  */
 362
 363 #ifdef CONFIG_44x
 364 #define _PAGE_BASE      (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_GUARDED)
 365 #else
 366 #define _PAGE_BASE      (_PAGE_PRESENT | _PAGE_ACCESSED)
 367 #endif
 368 #define _PAGE_WRENABLE  (_PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE)
 369 #define _PAGE_KERNEL    (_PAGE_BASE | _PAGE_SHARED | _PAGE_WRENABLE)
 370
 371 #ifdef CONFIG_PPC_STD_MMU
 372 /* On standard PPC MMU, no user access implies kernel read/write access,
 373  * so to write-protect kernel memory we must turn on user access */
 374 #define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED | _PAGE_USER)
 375 #else
 376 #define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED)
 377 #endif
 378
 379 #define _PAGE_IO        (_PAGE_KERNEL | _PAGE_NO_CACHE | _PAGE_GUARDED)
 380 #define _PAGE_RAM       (_PAGE_KERNEL | _PAGE_HWEXEC)
 381
 382 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH)
 383 /* We want the debuggers to be able to set breakpoints anywhere, so
 384  * don't write protect the kernel text */
 385 #define _PAGE_RAM_TEXT  _PAGE_RAM
 386 #else
 387 #define _PAGE_RAM_TEXT  (_PAGE_KERNEL_RO | _PAGE_HWEXEC)
 388 #endif
 389
 390 #define PAGE_NONE       __pgprot(_PAGE_BASE)
 391 #define PAGE_READONLY   __pgprot(_PAGE_BASE | _PAGE_USER)
 392 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
 393 #define PAGE_SHARED     __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
 394 #define PAGE_SHARED_X   __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
 395 #define PAGE_COPY       __pgprot(_PAGE_BASE | _PAGE_USER)
 396 #define PAGE_COPY_X     __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
 397
 398 #define PAGE_KERNEL             __pgprot(_PAGE_RAM)
 399 #define PAGE_KERNEL_NOCACHE     __pgprot(_PAGE_IO)
 400
 401 /*
 402  * The PowerPC can only do execute protection on a segment (256MB) basis,
 403  * not on a page basis.  So we consider execute permission the same as read.
 404  * Also, write permissions imply read permissions.
 405  * This is the closest we can get..
 406  */
 407 #define __P000  PAGE_NONE
 408 #define __P001  PAGE_READONLY_X
 409 #define __P010  PAGE_COPY
 410 #define __P011  PAGE_COPY_X
 411 #define __P100  PAGE_READONLY
 412 #define __P101  PAGE_READONLY_X
 413 #define __P110  PAGE_COPY
 414 #define __P111  PAGE_COPY_X
 415
 416 #define __S000  PAGE_NONE
 417 #define __S001  PAGE_READONLY_X
 418 #define __S010  PAGE_SHARED
 419 #define __S011  PAGE_SHARED_X
 420 #define __S100  PAGE_READONLY
 421 #define __S101  PAGE_READONLY_X
 422 #define __S110  PAGE_SHARED
 423 #define __S111  PAGE_SHARED_X
 424
 425 #ifndef __ASSEMBLY__
 426 /* Make sure we get a link error if PMD_PAGE_SIZE is ever called on a
 427  * kernel without large page PMD support */
 428 extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
 429
 430 /*
 431  * Conversions between PTE values and page frame numbers.
 432  */
 433
 434 #define pte_pfn(x)              (pte_val(x) >> PAGE_SHIFT)
 435 #define pte_page(x)             pfn_to_page(pte_pfn(x))
 436
 437 #define pfn_pte(pfn, prot)      __pte(((pte_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
 438 #define mk_pte(page, prot)      pfn_pte(page_to_pfn(page), prot)
 439
 440 /*
 441  * ZERO_PAGE is a global shared page that is always zero: used
 442  * for zero-mapped memory areas etc..
 443  */
 444 extern unsigned long empty_zero_page[1024];
 445 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
 446
 447 #endif /* __ASSEMBLY__ */
 448
 449 #define pte_none(pte)           ((pte_val(pte) & ~_PTE_NONE_MASK) == 0)
 450 #define pte_present(pte)        (pte_val(pte) & _PAGE_PRESENT)
 451 #define pte_clear(mm,addr,ptep) do { set_pte_at((mm), (addr), (ptep), __pte(0)); } while (0)
 452
 453 #define pmd_none(pmd)           (!pmd_val(pmd))
 454 #define pmd_bad(pmd)            (pmd_val(pmd) & _PMD_BAD)
 455 #define pmd_present(pmd)        (pmd_val(pmd) & _PMD_PRESENT_MASK)
 456 #define pmd_clear(pmdp)         do { pmd_val(*(pmdp)) = 0; } while (0)
 457
 458 #ifndef __ASSEMBLY__
 459 /*
 460  * The "pgd_xxx()" functions here are trivial for a folded two-level
 461  * setup: the pgd is never bad, and a pmd always exists (as it's folded
 462  * into the pgd entry)
 463  */
 464 static inline int pgd_none(pgd_t pgd)           { return 0; }
 465 static inline int pgd_bad(pgd_t pgd)            { return 0; }
 466 static inline int pgd_present(pgd_t pgd)        { return 1; }
 467 #define pgd_clear(xp)                           do { } while (0)
 468
 469 #define pgd_page(pgd) \
 470         ((unsigned long) __va(pgd_val(pgd) & PAGE_MASK))
 471
 472 /*
 473  * The following only work if pte_present() is true.
 474  * Undefined behaviour if not..
 475  */
 476 static inline int pte_read(pte_t pte)           { return pte_val(pte) & _PAGE_USER; }
 477 static inline int pte_write(pte_t pte)          { return pte_val(pte) & _PAGE_RW; }
 478 static inline int pte_exec(pte_t pte)           { return pte_val(pte) & _PAGE_EXEC; }
 479 static inline int pte_dirty(pte_t pte)          { return pte_val(pte) & _PAGE_DIRTY; }
 480 static inline int pte_young(pte_t pte)          { return pte_val(pte) & _PAGE_ACCESSED; }
 481 static inline int pte_file(pte_t pte)           { return pte_val(pte) & _PAGE_FILE; }
 482
 483 static inline void pte_uncache(pte_t pte)       { pte_val(pte) |= _PAGE_NO_CACHE; }
 484 static inline void pte_cache(pte_t pte)         { pte_val(pte) &= ~_PAGE_NO_CACHE; }
 485
 486 static inline pte_t pte_rdprotect(pte_t pte) {
 487         pte_val(pte) &= ~_PAGE_USER; return pte; }
 488 static inline pte_t pte_wrprotect(pte_t pte) {
 489         pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; }
 490 static inline pte_t pte_exprotect(pte_t pte) {
 491         pte_val(pte) &= ~_PAGE_EXEC; return pte; }
 492 static inline pte_t pte_mkclean(pte_t pte) {
 493         pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; }
 494 static inline pte_t pte_mkold(pte_t pte) {
 495         pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
 496
 497 static inline pte_t pte_mkread(pte_t pte) {
 498         pte_val(pte) |= _PAGE_USER; return pte; }
 499 static inline pte_t pte_mkexec(pte_t pte) {
 500         pte_val(pte) |= _PAGE_USER | _PAGE_EXEC; return pte; }
 501 static inline pte_t pte_mkwrite(pte_t pte) {
 502         pte_val(pte) |= _PAGE_RW; return pte; }
 503 static inline pte_t pte_mkdirty(pte_t pte) {
 504         pte_val(pte) |= _PAGE_DIRTY; return pte; }
 505 static inline pte_t pte_mkyoung(pte_t pte) {
 506         pte_val(pte) |= _PAGE_ACCESSED; return pte; }
 507
 508 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 509 {
 510         pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
 511         return pte;
 512 }
 513
 514 /*
 515  * When flushing the tlb entry for a page, we also need to flush the hash
 516  * table entry.  flush_hash_pages is assembler (for speed) in hashtable.S.
 517  */
 518 extern int flush_hash_pages(unsigned context, unsigned long va,
 519                             unsigned long pmdval, int count);
 520
 521 /* Add an HPTE to the hash table */
 522 extern void add_hash_page(unsigned context, unsigned long va,
 523                           unsigned long pmdval);
 524
 525 /*
 526  * Atomic PTE updates.
 527  *
 528  * pte_update clears and sets bit atomically, and returns
 529  * the old pte value.
 530  * The ((unsigned long)(p+1) - 4) hack is to get to the least-significant
 531  * 32 bits of the PTE regardless of whether PTEs are 32 or 64 bits.
 532  */
 533 static inline unsigned long pte_update(pte_t *p, unsigned long clr,
 534                                        unsigned long set)
 535 {
 536         unsigned long old, tmp;
 537
 538         __asm__ __volatile__("\
 539 1:      lwarx   %0,0,%3\n\
 540         andc    %1,%0,%4\n\
 541         or      %1,%1,%5\n"
 542         PPC405_ERR77(0,%3)
 543 "       stwcx.  %1,0,%3\n\
 544         bne-    1b"
 545         : "=&r" (old), "=&r" (tmp), "=m" (*p)
 546         : "r" ((unsigned long)(p+1) - 4), "r" (clr), "r" (set), "m" (*p)
 547         : "cc" );
 548         return old;
 549 }
 550
 551 /*
 552  * set_pte stores a linux PTE into the linux page table.
 553  * On machines which use an MMU hash table we avoid changing the
 554  * _PAGE_HASHPTE bit.
 555  */
 556 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
 557                               pte_t *ptep, pte_t pte)
 558 {
 559 #if _PAGE_HASHPTE != 0
 560         pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte) & ~_PAGE_HASHPTE);
 561 #else
 562         *ptep = pte;
 563 #endif
 564 }
 565
 566 /*
 567  * 2.6 calles this without flushing the TLB entry, this is wrong
 568  * for our hash-based implementation, we fix that up here
 569  */
 570 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
 571 static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep)
 572 {
 573         unsigned long old;
 574         old = pte_update(ptep, _PAGE_ACCESSED, 0);
 575 #if _PAGE_HASHPTE != 0
 576         if (old & _PAGE_HASHPTE) {
 577                 unsigned long ptephys = __pa(ptep) & PAGE_MASK;
 578                 flush_hash_pages(context, addr, ptephys, 1);
 579         }
 580 #endif
 581         return (old & _PAGE_ACCESSED) != 0;
 582 }
 583 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \
 584         __ptep_test_and_clear_young((__vma)->vm_mm->context, __addr, __ptep)
 585
 586 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
 587 static inline int ptep_test_and_clear_dirty(struct vm_area_struct *vma,
 588                                             unsigned long addr, pte_t *ptep)
 589 {
 590         return (pte_update(ptep, (_PAGE_DIRTY | _PAGE_HWWRITE), 0) & _PAGE_DIRTY) != 0;
 591 }
 592
 593 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
 594 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
 595                                        pte_t *ptep)
 596 {
 597         return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0));
 598 }
 599
 600 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
 601 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
 602                                       pte_t *ptep)
 603 {
 604         pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0);
 605 }
 606
 607 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
 608 static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
 609 {
 610         unsigned long bits = pte_val(entry) &
 611                 (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW);
 612         pte_update(ptep, 0, bits);
 613 }
 614
 615 #define  ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
 616         do {                                                               \
 617                 __ptep_set_access_flags(__ptep, __entry, __dirty);         \
 618                 flush_tlb_page_nohash(__vma, __address);                   \
 619         } while(0)
 620
 621 /*
 622  * Macro to mark a page protection value as "uncacheable".
 623  */
 624 #define pgprot_noncached(prot)  (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED))
 625
 626 struct file;
 627 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long addr,
 628                                      unsigned long size, pgprot_t vma_prot);
 629 #define __HAVE_PHYS_MEM_ACCESS_PROT
 630
 631 #define __HAVE_ARCH_PTE_SAME
 632 #define pte_same(A,B)   (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)
 633
 634 /*
 635  * Note that on Book E processors, the pmd contains the kernel virtual
 636  * (lowmem) address of the pte page.  The physical address is less useful
 637  * because everything runs with translation enabled (even the TLB miss
 638  * handler).  On everything else the pmd contains the physical address
 639  * of the pte page.  -- paulus
 640  */
 641 #ifndef CONFIG_BOOKE
 642 #define pmd_page_kernel(pmd)    \
 643         ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
 644 #define pmd_page(pmd)           \
 645         (mem_map + (pmd_val(pmd) >> PAGE_SHIFT))
 646 #else
 647 #define pmd_page_kernel(pmd)    \
 648         ((unsigned long) (pmd_val(pmd) & PAGE_MASK))
 649 #define pmd_page(pmd)           \
 650         (mem_map + (__pa(pmd_val(pmd)) >> PAGE_SHIFT))
 651 #endif
 652
 653 /* to find an entry in a kernel page-table-directory */
 654 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
 655
 656 /* to find an entry in a page-table-directory */
 657 #define pgd_index(address)       ((address) >> PGDIR_SHIFT)
 658 #define pgd_offset(mm, address)  ((mm)->pgd + pgd_index(address))
 659
 660 /* Find an entry in the second-level page table.. */
 661 static inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
 662 {
 663         return (pmd_t *) dir;
 664 }
 665
 666 /* Find an entry in the third-level page table.. */
 667 #define pte_index(address)              \
 668         (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
 669 #define pte_offset_kernel(dir, addr)    \
 670         ((pte_t *) pmd_page_kernel(*(dir)) + pte_index(addr))
 671 #define pte_offset_map(dir, addr)               \
 672         ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE0) + pte_index(addr))
 673 #define pte_offset_map_nested(dir, addr)        \
 674         ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE1) + pte_index(addr))
 675
 676 #define pte_unmap(pte)          kunmap_atomic(pte, KM_PTE0)
 677 #define pte_unmap_nested(pte)   kunmap_atomic(pte, KM_PTE1)
 678
 679 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
 680
 681 extern void paging_init(void);
 682
 683 /*
 684  * Encode and decode a swap entry.
 685  * Note that the bits we use in a PTE for representing a swap entry
 686  * must not include the _PAGE_PRESENT bit, the _PAGE_FILE bit, or the
 687  *_PAGE_HASHPTE bit (if used).  -- paulus
 688  */
 689 #define __swp_type(entry)               ((entry).val & 0x1f)
 690 #define __swp_offset(entry)             ((entry).val >> 5)
 691 #define __swp_entry(type, offset)       ((swp_entry_t) { (type) | ((offset) << 5) })
 692 #define __pte_to_swp_entry(pte)         ((swp_entry_t) { pte_val(pte) >> 3 })
 693 #define __swp_entry_to_pte(x)           ((pte_t) { (x).val << 3 })
 694
 695 /* Encode and decode a nonlinear file mapping entry */
 696 #define PTE_FILE_MAX_BITS       29
 697 #define pte_to_pgoff(pte)       (pte_val(pte) >> 3)
 698 #define pgoff_to_pte(off)       ((pte_t) { ((off) << 3) | _PAGE_FILE })
 699
 700 /* CONFIG_APUS */
 701 /* For virtual address to physical address conversion */
 702 extern void cache_clear(__u32 addr, int length);
 703 extern void cache_push(__u32 addr, int length);
 704 extern int mm_end_of_chunk (unsigned long addr, int len);
 705 extern unsigned long iopa(unsigned long addr);
 706 extern unsigned long mm_ptov(unsigned long addr) __attribute_const__;
 707
 708 /* Values for nocacheflag and cmode */
 709 /* These are not used by the APUS kernel_map, but prevents
 710    compilation errors. */
 711 #define KERNELMAP_FULL_CACHING          0
 712 #define KERNELMAP_NOCACHE_SER           1
 713 #define KERNELMAP_NOCACHE_NONSER        2
 714 #define KERNELMAP_NO_COPYBACK           3
 715
 716 /*
 717  * Map some physical address range into the kernel address space.
 718  */
 719 extern unsigned long kernel_map(unsigned long paddr, unsigned long size,
 720                                 int nocacheflag, unsigned long *memavailp );
 721
 722 /*
 723  * Set cache mode of (kernel space) address range.
 724  */
 725 extern void kernel_set_cachemode (unsigned long address, unsigned long size,
 726                                  unsigned int cmode);
 727
 728 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
 729 #define kern_addr_valid(addr)   (1)
 730
 731 #ifdef CONFIG_PHYS_64BIT
 732 extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from,
 733                         unsigned long paddr, unsigned long size, pgprot_t prot);
 734 static inline int io_remap_page_range(struct vm_area_struct *vma,
 735                                         unsigned long vaddr,
 736                                         unsigned long paddr,
 737                                         unsigned long size,
 738                                         pgprot_t prot)
 739 {
 740         phys_addr_t paddr64 = fixup_bigphys_addr(paddr, size);
 741         return remap_pfn_range(vma, vaddr, paddr64 >> PAGE_SHIFT, size, prot);
 742 }
 743
 744 static inline int io_remap_pfn_range(struct vm_area_struct *vma,
 745                                         unsigned long vaddr,
 746                                         unsigned long pfn,
 747                                         unsigned long size,
 748                                         pgprot_t prot)
 749 {
 750         phys_addr_t paddr64 = fixup_bigphys_addr(pfn << PAGE_SHIFT, size);
 751         return remap_pfn_range(vma, vaddr, paddr64 >> PAGE_SHIFT, size, prot);
 752 }
 753 #else
 754 #define io_remap_page_range(vma, vaddr, paddr, size, prot)              \
 755                 remap_pfn_range(vma, vaddr, (paddr) >> PAGE_SHIFT, size, prot)
 756 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
 757                 remap_pfn_range(vma, vaddr, pfn, size, prot)
 758 #endif
 759
 760 #define MK_IOSPACE_PFN(space, pfn)      (pfn)
 761 #define GET_IOSPACE(pfn)                0
 762 #define GET_PFN(pfn)                    (pfn)
 763
 764 /*
 765  * No page table caches to initialise
 766  */
 767 #define pgtable_cache_init()    do { } while (0)
 768
 769 extern int get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep);
 770
 771 #include <asm-generic/pgtable.h>
 772
 773 #endif /* !__ASSEMBLY__ */
 774
 775 #endif /* _PPC_PGTABLE_H */
 776 #endif /* __KERNEL__ */