Linux 2.6.25-rc4
[linux-2.6/next.git] / arch / arm / mach-at91 / at91sam9261.c
blob90b87e1877d9006e7555f735c34876a401d5e3ee
1 /*
2 * arch/arm/mach-at91/at91sam9261.c
4 * Copyright (C) 2005 SAN People
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
13 #include <linux/module.h>
15 #include <asm/mach/arch.h>
16 #include <asm/mach/map.h>
17 #include <asm/arch/at91sam9261.h>
18 #include <asm/arch/at91_pmc.h>
19 #include <asm/arch/at91_rstc.h>
21 #include "generic.h"
22 #include "clock.h"
24 static struct map_desc at91sam9261_io_desc[] __initdata = {
26 .virtual = AT91_VA_BASE_SYS,
27 .pfn = __phys_to_pfn(AT91_BASE_SYS),
28 .length = SZ_16K,
29 .type = MT_DEVICE,
30 }, {
31 .virtual = AT91_IO_VIRT_BASE - AT91SAM9261_SRAM_SIZE,
32 .pfn = __phys_to_pfn(AT91SAM9261_SRAM_BASE),
33 .length = AT91SAM9261_SRAM_SIZE,
34 .type = MT_DEVICE,
38 /* --------------------------------------------------------------------
39 * Clocks
40 * -------------------------------------------------------------------- */
43 * The peripheral clocks.
45 static struct clk pioA_clk = {
46 .name = "pioA_clk",
47 .pmc_mask = 1 << AT91SAM9261_ID_PIOA,
48 .type = CLK_TYPE_PERIPHERAL,
50 static struct clk pioB_clk = {
51 .name = "pioB_clk",
52 .pmc_mask = 1 << AT91SAM9261_ID_PIOB,
53 .type = CLK_TYPE_PERIPHERAL,
55 static struct clk pioC_clk = {
56 .name = "pioC_clk",
57 .pmc_mask = 1 << AT91SAM9261_ID_PIOC,
58 .type = CLK_TYPE_PERIPHERAL,
60 static struct clk usart0_clk = {
61 .name = "usart0_clk",
62 .pmc_mask = 1 << AT91SAM9261_ID_US0,
63 .type = CLK_TYPE_PERIPHERAL,
65 static struct clk usart1_clk = {
66 .name = "usart1_clk",
67 .pmc_mask = 1 << AT91SAM9261_ID_US1,
68 .type = CLK_TYPE_PERIPHERAL,
70 static struct clk usart2_clk = {
71 .name = "usart2_clk",
72 .pmc_mask = 1 << AT91SAM9261_ID_US2,
73 .type = CLK_TYPE_PERIPHERAL,
75 static struct clk mmc_clk = {
76 .name = "mci_clk",
77 .pmc_mask = 1 << AT91SAM9261_ID_MCI,
78 .type = CLK_TYPE_PERIPHERAL,
80 static struct clk udc_clk = {
81 .name = "udc_clk",
82 .pmc_mask = 1 << AT91SAM9261_ID_UDP,
83 .type = CLK_TYPE_PERIPHERAL,
85 static struct clk twi_clk = {
86 .name = "twi_clk",
87 .pmc_mask = 1 << AT91SAM9261_ID_TWI,
88 .type = CLK_TYPE_PERIPHERAL,
90 static struct clk spi0_clk = {
91 .name = "spi0_clk",
92 .pmc_mask = 1 << AT91SAM9261_ID_SPI0,
93 .type = CLK_TYPE_PERIPHERAL,
95 static struct clk spi1_clk = {
96 .name = "spi1_clk",
97 .pmc_mask = 1 << AT91SAM9261_ID_SPI1,
98 .type = CLK_TYPE_PERIPHERAL,
100 static struct clk ssc0_clk = {
101 .name = "ssc0_clk",
102 .pmc_mask = 1 << AT91SAM9261_ID_SSC0,
103 .type = CLK_TYPE_PERIPHERAL,
105 static struct clk ssc1_clk = {
106 .name = "ssc1_clk",
107 .pmc_mask = 1 << AT91SAM9261_ID_SSC1,
108 .type = CLK_TYPE_PERIPHERAL,
110 static struct clk ssc2_clk = {
111 .name = "ssc2_clk",
112 .pmc_mask = 1 << AT91SAM9261_ID_SSC2,
113 .type = CLK_TYPE_PERIPHERAL,
115 static struct clk tc0_clk = {
116 .name = "tc0_clk",
117 .pmc_mask = 1 << AT91SAM9261_ID_TC0,
118 .type = CLK_TYPE_PERIPHERAL,
120 static struct clk tc1_clk = {
121 .name = "tc1_clk",
122 .pmc_mask = 1 << AT91SAM9261_ID_TC1,
123 .type = CLK_TYPE_PERIPHERAL,
125 static struct clk tc2_clk = {
126 .name = "tc2_clk",
127 .pmc_mask = 1 << AT91SAM9261_ID_TC2,
128 .type = CLK_TYPE_PERIPHERAL,
130 static struct clk ohci_clk = {
131 .name = "ohci_clk",
132 .pmc_mask = 1 << AT91SAM9261_ID_UHP,
133 .type = CLK_TYPE_PERIPHERAL,
135 static struct clk lcdc_clk = {
136 .name = "lcdc_clk",
137 .pmc_mask = 1 << AT91SAM9261_ID_LCDC,
138 .type = CLK_TYPE_PERIPHERAL,
141 static struct clk *periph_clocks[] __initdata = {
142 &pioA_clk,
143 &pioB_clk,
144 &pioC_clk,
145 &usart0_clk,
146 &usart1_clk,
147 &usart2_clk,
148 &mmc_clk,
149 &udc_clk,
150 &twi_clk,
151 &spi0_clk,
152 &spi1_clk,
153 &ssc0_clk,
154 &ssc1_clk,
155 &ssc2_clk,
156 &tc0_clk,
157 &tc1_clk,
158 &tc2_clk,
159 &ohci_clk,
160 &lcdc_clk,
161 // irq0 .. irq2
165 * The four programmable clocks.
166 * You must configure pin multiplexing to bring these signals out.
168 static struct clk pck0 = {
169 .name = "pck0",
170 .pmc_mask = AT91_PMC_PCK0,
171 .type = CLK_TYPE_PROGRAMMABLE,
172 .id = 0,
174 static struct clk pck1 = {
175 .name = "pck1",
176 .pmc_mask = AT91_PMC_PCK1,
177 .type = CLK_TYPE_PROGRAMMABLE,
178 .id = 1,
180 static struct clk pck2 = {
181 .name = "pck2",
182 .pmc_mask = AT91_PMC_PCK2,
183 .type = CLK_TYPE_PROGRAMMABLE,
184 .id = 2,
186 static struct clk pck3 = {
187 .name = "pck3",
188 .pmc_mask = AT91_PMC_PCK3,
189 .type = CLK_TYPE_PROGRAMMABLE,
190 .id = 3,
193 /* HClocks */
194 static struct clk hck0 = {
195 .name = "hck0",
196 .pmc_mask = AT91_PMC_HCK0,
197 .type = CLK_TYPE_SYSTEM,
198 .id = 0,
200 static struct clk hck1 = {
201 .name = "hck1",
202 .pmc_mask = AT91_PMC_HCK1,
203 .type = CLK_TYPE_SYSTEM,
204 .id = 1,
207 static void __init at91sam9261_register_clocks(void)
209 int i;
211 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
212 clk_register(periph_clocks[i]);
214 clk_register(&pck0);
215 clk_register(&pck1);
216 clk_register(&pck2);
217 clk_register(&pck3);
219 clk_register(&hck0);
220 clk_register(&hck1);
223 /* --------------------------------------------------------------------
224 * GPIO
225 * -------------------------------------------------------------------- */
227 static struct at91_gpio_bank at91sam9261_gpio[] = {
229 .id = AT91SAM9261_ID_PIOA,
230 .offset = AT91_PIOA,
231 .clock = &pioA_clk,
232 }, {
233 .id = AT91SAM9261_ID_PIOB,
234 .offset = AT91_PIOB,
235 .clock = &pioB_clk,
236 }, {
237 .id = AT91SAM9261_ID_PIOC,
238 .offset = AT91_PIOC,
239 .clock = &pioC_clk,
243 static void at91sam9261_reset(void)
245 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
249 /* --------------------------------------------------------------------
250 * AT91SAM9261 processor initialization
251 * -------------------------------------------------------------------- */
253 void __init at91sam9261_initialize(unsigned long main_clock)
255 /* Map peripherals */
256 iotable_init(at91sam9261_io_desc, ARRAY_SIZE(at91sam9261_io_desc));
258 at91_arch_reset = at91sam9261_reset;
259 at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
260 | (1 << AT91SAM9261_ID_IRQ2);
262 /* Init clock subsystem */
263 at91_clock_init(main_clock);
265 /* Register the processor-specific clocks */
266 at91sam9261_register_clocks();
268 /* Register GPIO subsystem */
269 at91_gpio_init(at91sam9261_gpio, 3);
272 /* --------------------------------------------------------------------
273 * Interrupt initialization
274 * -------------------------------------------------------------------- */
277 * The default interrupt priority levels (0 = lowest, 7 = highest).
279 static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
280 7, /* Advanced Interrupt Controller */
281 7, /* System Peripherals */
282 1, /* Parallel IO Controller A */
283 1, /* Parallel IO Controller B */
284 1, /* Parallel IO Controller C */
286 5, /* USART 0 */
287 5, /* USART 1 */
288 5, /* USART 2 */
289 0, /* Multimedia Card Interface */
290 2, /* USB Device Port */
291 6, /* Two-Wire Interface */
292 5, /* Serial Peripheral Interface 0 */
293 5, /* Serial Peripheral Interface 1 */
294 4, /* Serial Synchronous Controller 0 */
295 4, /* Serial Synchronous Controller 1 */
296 4, /* Serial Synchronous Controller 2 */
297 0, /* Timer Counter 0 */
298 0, /* Timer Counter 1 */
299 0, /* Timer Counter 2 */
300 2, /* USB Host port */
301 3, /* LCD Controller */
309 0, /* Advanced Interrupt Controller */
310 0, /* Advanced Interrupt Controller */
311 0, /* Advanced Interrupt Controller */
314 void __init at91sam9261_init_interrupts(unsigned int priority[NR_AIC_IRQS])
316 if (!priority)
317 priority = at91sam9261_default_irq_priority;
319 /* Initialize the AIC interrupt controller */
320 at91_aic_init(priority);
322 /* Enable GPIO interrupts */
323 at91_gpio_irq_setup();