arch/arm/mach-ixp23xx/core.c

   1 /*
   2  * arch/arm/mach-ixp23xx/core.c
   3  *
   4  * Core routines for IXP23xx chips
   5  *
   6  * Author: Deepak Saxena <dsaxena@plexity.net>
   7  *
   8  * Copyright 2005 (c) MontaVista Software, Inc.
   9  *
  10  * Based on 2.4 code Copyright 2004 (c) Intel Corporation
  11  *
  12  * This file is licensed under the terms of the GNU General Public
  13  * License version 2. This program is licensed "as is" without any
  14  * warranty of any kind, whether express or implied.
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/sched.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/serial.h>
  23 #include <linux/tty.h>
  24 #include <linux/bitops.h>
  25 #include <linux/serial_8250.h>
  26 #include <linux/serial_core.h>
  27 #include <linux/device.h>
  28 #include <linux/mm.h>
  29 #include <linux/time.h>
  30 #include <linux/timex.h>
  31
  32 #include <asm/types.h>
  33 #include <asm/setup.h>
  34 #include <asm/memory.h>
  35 #include <asm/hardware.h>
  36 #include <asm/mach-types.h>
  37 #include <asm/irq.h>
  38 #include <asm/system.h>
  39 #include <asm/tlbflush.h>
  40 #include <asm/pgtable.h>
  41
  42 #include <asm/mach/map.h>
  43 #include <asm/mach/time.h>
  44 #include <asm/mach/irq.h>
  45 #include <asm/mach/arch.h>
  46
  47
  48 /*************************************************************************
  49  * Chip specific mappings shared by all IXP23xx systems
  50  *************************************************************************/
  51 static struct map_desc ixp23xx_io_desc[] __initdata = {
  52         { /* XSI-CPP CSRs */
  53                 .virtual        = IXP23XX_XSI2CPP_CSR_VIRT,
  54                 .pfn            = __phys_to_pfn(IXP23XX_XSI2CPP_CSR_PHYS),
  55                 .length         = IXP23XX_XSI2CPP_CSR_SIZE,
  56                 .type           = MT_DEVICE,
  57         }, { /* Expansion Bus Config */
  58                 .virtual        = IXP23XX_EXP_CFG_VIRT,
  59                 .pfn            = __phys_to_pfn(IXP23XX_EXP_CFG_PHYS),
  60                 .length         = IXP23XX_EXP_CFG_SIZE,
  61                 .type           = MT_DEVICE,
  62         }, { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACS,.... */
  63                 .virtual        = IXP23XX_PERIPHERAL_VIRT,
  64                 .pfn            = __phys_to_pfn(IXP23XX_PERIPHERAL_PHYS),
  65                 .length         = IXP23XX_PERIPHERAL_SIZE,
  66                 .type           = MT_DEVICE,
  67         }, { /* CAP CSRs */
  68                 .virtual        = IXP23XX_CAP_CSR_VIRT,
  69                 .pfn            = __phys_to_pfn(IXP23XX_CAP_CSR_PHYS),
  70                 .length         = IXP23XX_CAP_CSR_SIZE,
  71                 .type           = MT_DEVICE,
  72         }, { /* MSF CSRs */
  73                 .virtual        = IXP23XX_MSF_CSR_VIRT,
  74                 .pfn            = __phys_to_pfn(IXP23XX_MSF_CSR_PHYS),
  75                 .length         = IXP23XX_MSF_CSR_SIZE,
  76                 .type           = MT_DEVICE,
  77         }, { /* PCI I/O Space */
  78                 .virtual        = IXP23XX_PCI_IO_VIRT,
  79                 .pfn            = __phys_to_pfn(IXP23XX_PCI_IO_PHYS),
  80                 .length         = IXP23XX_PCI_IO_SIZE,
  81                 .type           = MT_DEVICE,
  82         }, { /* PCI Config Space */
  83                 .virtual        = IXP23XX_PCI_CFG_VIRT,
  84                 .pfn            = __phys_to_pfn(IXP23XX_PCI_CFG_PHYS),
  85                 .length         = IXP23XX_PCI_CFG_SIZE,
  86                 .type           = MT_DEVICE,
  87         }, { /* PCI local CFG CSRs */
  88                 .virtual        = IXP23XX_PCI_CREG_VIRT,
  89                 .pfn            = __phys_to_pfn(IXP23XX_PCI_CREG_PHYS),
  90                 .length         = IXP23XX_PCI_CREG_SIZE,
  91                 .type           = MT_DEVICE,
  92         }, { /* PCI MEM Space */
  93                 .virtual        = IXP23XX_PCI_MEM_VIRT,
  94                 .pfn            = __phys_to_pfn(IXP23XX_PCI_MEM_PHYS),
  95                 .length         = IXP23XX_PCI_MEM_SIZE,
  96                 .type           = MT_DEVICE,
  97         }
  98 };
  99
 100 void __init ixp23xx_map_io(void)
 101 {
 102         iotable_init(ixp23xx_io_desc, ARRAY_SIZE(ixp23xx_io_desc));
 103 }
 104
 105
 106 /***************************************************************************
 107  * IXP23xx Interrupt Handling
 108  ***************************************************************************/
 109 enum ixp23xx_irq_type {
 110         IXP23XX_IRQ_LEVEL, IXP23XX_IRQ_EDGE
 111 };
 112
 113 static void ixp23xx_config_irq(unsigned int, enum ixp23xx_irq_type);
 114
 115 static int ixp23xx_irq_set_type(unsigned int irq, unsigned int type)
 116 {
 117         int line = irq - IRQ_IXP23XX_GPIO6 + 6;
 118         u32 int_style;
 119         enum ixp23xx_irq_type irq_type;
 120         volatile u32 *int_reg;
 121
 122         /*
 123          * Only GPIOs 6-15 are wired to interrupts on IXP23xx
 124          */
 125         if (line < 6 || line > 15)
 126                 return -EINVAL;
 127
 128         switch (type) {
 129         case IRQT_BOTHEDGE:
 130                 int_style = IXP23XX_GPIO_STYLE_TRANSITIONAL;
 131                 irq_type = IXP23XX_IRQ_EDGE;
 132                 break;
 133         case IRQT_RISING:
 134                 int_style = IXP23XX_GPIO_STYLE_RISING_EDGE;
 135                 irq_type = IXP23XX_IRQ_EDGE;
 136                 break;
 137         case IRQT_FALLING:
 138                 int_style = IXP23XX_GPIO_STYLE_FALLING_EDGE;
 139                 irq_type = IXP23XX_IRQ_EDGE;
 140                 break;
 141         case IRQT_HIGH:
 142                 int_style = IXP23XX_GPIO_STYLE_ACTIVE_HIGH;
 143                 irq_type = IXP23XX_IRQ_LEVEL;
 144                 break;
 145         case IRQT_LOW:
 146                 int_style = IXP23XX_GPIO_STYLE_ACTIVE_LOW;
 147                 irq_type = IXP23XX_IRQ_LEVEL;
 148                 break;
 149         default:
 150                 return -EINVAL;
 151         }
 152
 153         ixp23xx_config_irq(irq, irq_type);
 154
 155         if (line >= 8) {        /* pins 8-15 */
 156                 line -= 8;
 157                 int_reg = (volatile u32 *)IXP23XX_GPIO_GPIT2R;
 158         } else {                /* pins 0-7 */
 159                 int_reg = (volatile u32 *)IXP23XX_GPIO_GPIT1R;
 160         }
 161
 162         /*
 163          * Clear pending interrupts
 164          */
 165         *IXP23XX_GPIO_GPISR = (1 << line);
 166
 167         /* Clear the style for the appropriate pin */
 168         *int_reg &= ~(IXP23XX_GPIO_STYLE_MASK <<
 169                         (line * IXP23XX_GPIO_STYLE_SIZE));
 170
 171         /* Set the new style */
 172         *int_reg |= (int_style << (line * IXP23XX_GPIO_STYLE_SIZE));
 173
 174         return 0;
 175 }
 176
 177 static void ixp23xx_irq_mask(unsigned int irq)
 178 {
 179         volatile unsigned long *intr_reg;
 180
 181         if (irq >= 56)
 182                 irq += 8;
 183
 184         intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
 185         *intr_reg &= ~(1 << (irq % 32));
 186 }
 187
 188 static void ixp23xx_irq_ack(unsigned int irq)
 189 {
 190         int line = irq - IRQ_IXP23XX_GPIO6 + 6;
 191
 192         if ((line < 6) || (line > 15))
 193                 return;
 194
 195         *IXP23XX_GPIO_GPISR = (1 << line);
 196 }
 197
 198 /*
 199  * Level triggered interrupts on GPIO lines can only be cleared when the
 200  * interrupt condition disappears.
 201  */
 202 static void ixp23xx_irq_level_unmask(unsigned int irq)
 203 {
 204         volatile unsigned long *intr_reg;
 205
 206         ixp23xx_irq_ack(irq);
 207
 208         if (irq >= 56)
 209                 irq += 8;
 210
 211         intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
 212         *intr_reg |= (1 << (irq % 32));
 213 }
 214
 215 static void ixp23xx_irq_edge_unmask(unsigned int irq)
 216 {
 217         volatile unsigned long *intr_reg;
 218
 219         if (irq >= 56)
 220                 irq += 8;
 221
 222         intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
 223         *intr_reg |= (1 << (irq % 32));
 224 }
 225
 226 static struct irq_chip ixp23xx_irq_level_chip = {
 227         .ack            = ixp23xx_irq_mask,
 228         .mask           = ixp23xx_irq_mask,
 229         .unmask         = ixp23xx_irq_level_unmask,
 230         .set_type       = ixp23xx_irq_set_type
 231 };
 232
 233 static struct irq_chip ixp23xx_irq_edge_chip = {
 234         .ack            = ixp23xx_irq_ack,
 235         .mask           = ixp23xx_irq_mask,
 236         .unmask         = ixp23xx_irq_edge_unmask,
 237         .set_type       = ixp23xx_irq_set_type
 238 };
 239
 240 static void ixp23xx_pci_irq_mask(unsigned int irq)
 241 {
 242         *IXP23XX_PCI_XSCALE_INT_ENABLE &= ~(1 << (IRQ_IXP23XX_INTA + 27 - irq));
 243 }
 244
 245 static void ixp23xx_pci_irq_unmask(unsigned int irq)
 246 {
 247         *IXP23XX_PCI_XSCALE_INT_ENABLE |= (1 << (IRQ_IXP23XX_INTA + 27 - irq));
 248 }
 249
 250 /*
 251  * TODO: Should this just be done at ASM level?
 252  */
 253 static void pci_handler(unsigned int irq, struct irq_desc *desc)
 254 {
 255         u32 pci_interrupt;
 256         unsigned int irqno;
 257         struct irq_desc *int_desc;
 258
 259         pci_interrupt = *IXP23XX_PCI_XSCALE_INT_STATUS;
 260
 261         desc->chip->ack(irq);
 262
 263         /* See which PCI_INTA, or PCI_INTB interrupted */
 264         if (pci_interrupt & (1 << 26)) {
 265                 irqno = IRQ_IXP23XX_INTB;
 266         } else if (pci_interrupt & (1 << 27)) {
 267                 irqno = IRQ_IXP23XX_INTA;
 268         } else {
 269                 BUG();
 270         }
 271
 272         int_desc = irq_desc + irqno;
 273         desc_handle_irq(irqno, int_desc);
 274
 275         desc->chip->unmask(irq);
 276 }
 277
 278 static struct irq_chip ixp23xx_pci_irq_chip = {
 279         .ack    = ixp23xx_pci_irq_mask,
 280         .mask   = ixp23xx_pci_irq_mask,
 281         .unmask = ixp23xx_pci_irq_unmask
 282 };
 283
 284 static void ixp23xx_config_irq(unsigned int irq, enum ixp23xx_irq_type type)
 285 {
 286         switch (type) {
 287         case IXP23XX_IRQ_LEVEL:
 288                 set_irq_chip(irq, &ixp23xx_irq_level_chip);
 289                 set_irq_handler(irq, handle_level_irq);
 290                 break;
 291         case IXP23XX_IRQ_EDGE:
 292                 set_irq_chip(irq, &ixp23xx_irq_edge_chip);
 293                 set_irq_handler(irq, handle_edge_irq);
 294                 break;
 295         }
 296         set_irq_flags(irq, IRQF_VALID);
 297 }
 298
 299 void __init ixp23xx_init_irq(void)
 300 {
 301         int irq;
 302
 303         /* Route everything to IRQ */
 304         *IXP23XX_INTR_SEL1 = 0x0;
 305         *IXP23XX_INTR_SEL2 = 0x0;
 306         *IXP23XX_INTR_SEL3 = 0x0;
 307         *IXP23XX_INTR_SEL4 = 0x0;
 308
 309         /* Mask all sources */
 310         *IXP23XX_INTR_EN1 = 0x0;
 311         *IXP23XX_INTR_EN2 = 0x0;
 312         *IXP23XX_INTR_EN3 = 0x0;
 313         *IXP23XX_INTR_EN4 = 0x0;
 314
 315         /*
 316          * Configure all IRQs for level-sensitive operation
 317          */
 318         for (irq = 0; irq <= NUM_IXP23XX_RAW_IRQS; irq++) {
 319                 ixp23xx_config_irq(irq, IXP23XX_IRQ_LEVEL);
 320         }
 321
 322         for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) {
 323                 set_irq_chip(irq, &ixp23xx_pci_irq_chip);
 324                 set_irq_handler(irq, handle_level_irq);
 325                 set_irq_flags(irq, IRQF_VALID);
 326         }
 327
 328         set_irq_chained_handler(IRQ_IXP23XX_PCI_INT_RPH, pci_handler);
 329 }
 330
 331
 332 /*************************************************************************
 333  * Timer-tick functions for IXP23xx
 334  *************************************************************************/
 335 #define CLOCK_TICKS_PER_USEC    (CLOCK_TICK_RATE / USEC_PER_SEC)
 336
 337 static unsigned long next_jiffy_time;
 338
 339 static unsigned long
 340 ixp23xx_gettimeoffset(void)
 341 {
 342         unsigned long elapsed;
 343
 344         elapsed = *IXP23XX_TIMER_CONT - (next_jiffy_time - LATCH);
 345
 346         return elapsed / CLOCK_TICKS_PER_USEC;
 347 }
 348
 349 static irqreturn_t
 350 ixp23xx_timer_interrupt(int irq, void *dev_id)
 351 {
 352         /* Clear Pending Interrupt by writing '1' to it */
 353         *IXP23XX_TIMER_STATUS = IXP23XX_TIMER1_INT_PEND;
 354         while ((signed long)(*IXP23XX_TIMER_CONT - next_jiffy_time) >= LATCH) {
 355                 timer_tick();
 356                 next_jiffy_time += LATCH;
 357         }
 358
 359         return IRQ_HANDLED;
 360 }
 361
 362 static struct irqaction ixp23xx_timer_irq = {
 363         .name           = "IXP23xx Timer Tick",
 364         .handler        = ixp23xx_timer_interrupt,
 365         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 366 };
 367
 368 void __init ixp23xx_init_timer(void)
 369 {
 370         /* Clear Pending Interrupt by writing '1' to it */
 371         *IXP23XX_TIMER_STATUS = IXP23XX_TIMER1_INT_PEND;
 372
 373         /* Setup the Timer counter value */
 374         *IXP23XX_TIMER1_RELOAD =
 375                 (LATCH & ~IXP23XX_TIMER_RELOAD_MASK) | IXP23XX_TIMER_ENABLE;
 376
 377         *IXP23XX_TIMER_CONT = 0;
 378         next_jiffy_time = LATCH;
 379
 380         /* Connect the interrupt handler and enable the interrupt */
 381         setup_irq(IRQ_IXP23XX_TIMER1, &ixp23xx_timer_irq);
 382 }
 383
 384 struct sys_timer ixp23xx_timer = {
 385         .init           = ixp23xx_init_timer,
 386         .offset         = ixp23xx_gettimeoffset,
 387 };
 388
 389
 390 /*************************************************************************
 391  * IXP23xx Platform Initialization
 392  *************************************************************************/
 393 static struct resource ixp23xx_uart_resources[] = {
 394         {
 395                 .start          = IXP23XX_UART1_PHYS,
 396                 .end            = IXP23XX_UART1_PHYS + 0x0fff,
 397                 .flags          = IORESOURCE_MEM
 398         }, {
 399                 .start          = IXP23XX_UART2_PHYS,
 400                 .end            = IXP23XX_UART2_PHYS + 0x0fff,
 401                 .flags          = IORESOURCE_MEM
 402         }
 403 };
 404
 405 static struct plat_serial8250_port ixp23xx_uart_data[] = {
 406         {
 407                 .mapbase        = IXP23XX_UART1_PHYS,
 408                 .membase        = (char *)(IXP23XX_UART1_VIRT + 3),
 409                 .irq            = IRQ_IXP23XX_UART1,
 410                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 411                 .iotype         = UPIO_MEM,
 412                 .regshift       = 2,
 413                 .uartclk        = IXP23XX_UART_XTAL,
 414         }, {
 415                 .mapbase        = IXP23XX_UART2_PHYS,
 416                 .membase        = (char *)(IXP23XX_UART2_VIRT + 3),
 417                 .irq            = IRQ_IXP23XX_UART2,
 418                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 419                 .iotype         = UPIO_MEM,
 420                 .regshift       = 2,
 421                 .uartclk        = IXP23XX_UART_XTAL,
 422         },
 423         { },
 424 };
 425
 426 static struct platform_device ixp23xx_uart = {
 427         .name                   = "serial8250",
 428         .id                     = 0,
 429         .dev.platform_data      = ixp23xx_uart_data,
 430         .num_resources          = 2,
 431         .resource               = ixp23xx_uart_resources,
 432 };
 433
 434 static struct platform_device *ixp23xx_devices[] __initdata = {
 435         &ixp23xx_uart,
 436 };
 437
 438 void __init ixp23xx_sys_init(void)
 439 {
 440         *IXP23XX_EXP_UNIT_FUSE |= 0xf;
 441         platform_add_devices(ixp23xx_devices, ARRAY_SIZE(ixp23xx_devices));
 442 }