2 * File: arch/blackfin/mach-bf537/ints-priority.c
3 * Based on: arch/blackfin/mach-bf533/ints-priority.c
4 * Author: Michael Hennerich
7 * Description: Set up the interrupt priorities
10 * Copyright 2004-2006 Analog Devices Inc.
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
30 #include <linux/module.h>
31 #include <linux/irq.h>
32 #include <asm/blackfin.h>
34 void program_IAR(void)
36 /* Program the IAR0 Register with the configured priority */
37 bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP
- 7) << IRQ_PLL_WAKEUP_POS
) |
38 ((CONFIG_IRQ_DMAC0_ERR
- 7) << IRQ_DMAC0_ERR_POS
) |
39 ((CONFIG_IRQ_EPPI0_ERR
- 7) << IRQ_EPPI0_ERR_POS
) |
40 ((CONFIG_IRQ_SPORT0_ERR
- 7) << IRQ_SPORT0_ERR_POS
) |
41 ((CONFIG_IRQ_SPORT1_ERR
- 7) << IRQ_SPORT1_ERR_POS
) |
42 ((CONFIG_IRQ_SPI0_ERR
- 7) << IRQ_SPI0_ERR_POS
) |
43 ((CONFIG_IRQ_UART0_ERR
- 7) << IRQ_UART0_ERR_POS
) |
44 ((CONFIG_IRQ_RTC
- 7) << IRQ_RTC_POS
));
46 bfin_write_SIC_IAR1(((CONFIG_IRQ_EPPI0
- 7) << IRQ_EPPI0_POS
) |
47 ((CONFIG_IRQ_SPORT0_RX
- 7) << IRQ_SPORT0_RX_POS
) |
48 ((CONFIG_IRQ_SPORT0_TX
- 7) << IRQ_SPORT0_TX_POS
) |
49 ((CONFIG_IRQ_SPORT1_RX
- 7) << IRQ_SPORT1_RX_POS
) |
50 ((CONFIG_IRQ_SPORT1_TX
- 7) << IRQ_SPORT1_TX_POS
) |
51 ((CONFIG_IRQ_SPI0
- 7) << IRQ_SPI0_POS
) |
52 ((CONFIG_IRQ_UART0_RX
- 7) << IRQ_UART0_RX_POS
) |
53 ((CONFIG_IRQ_UART0_TX
- 7) << IRQ_UART0_TX_POS
));
55 bfin_write_SIC_IAR2(((CONFIG_IRQ_TIMER8
- 7) << IRQ_TIMER8_POS
) |
56 ((CONFIG_IRQ_TIMER9
- 7) << IRQ_TIMER9_POS
) |
57 ((CONFIG_IRQ_PINT0
- 7) << IRQ_PINT0_POS
) |
58 ((CONFIG_IRQ_PINT1
- 7) << IRQ_PINT1_POS
) |
59 ((CONFIG_IRQ_MDMAS0
- 7) << IRQ_MDMAS0_POS
) |
60 ((CONFIG_IRQ_MDMAS1
- 7) << IRQ_MDMAS1_POS
) |
61 ((CONFIG_IRQ_WATCHDOG
- 7) << IRQ_WATCH_POS
));
63 bfin_write_SIC_IAR3(((CONFIG_IRQ_DMAC1_ERR
- 7) << IRQ_DMAC1_ERR_POS
) |
64 ((CONFIG_IRQ_SPORT2_ERR
- 7) << IRQ_SPORT2_ERR_POS
) |
65 ((CONFIG_IRQ_SPORT3_ERR
- 7) << IRQ_SPORT3_ERR_POS
) |
66 ((CONFIG_IRQ_MXVR_DATA
- 7) << IRQ_MXVR_DATA_POS
) |
67 ((CONFIG_IRQ_SPI1_ERR
- 7) << IRQ_SPI1_ERR_POS
) |
68 ((CONFIG_IRQ_SPI2_ERR
- 7) << IRQ_SPI2_ERR_POS
) |
69 ((CONFIG_IRQ_UART1_ERR
- 7) << IRQ_UART1_ERR_POS
) |
70 ((CONFIG_IRQ_UART2_ERR
- 7) << IRQ_UART2_ERR_POS
));
72 bfin_write_SIC_IAR4(((CONFIG_IRQ_CAN0_ERR
- 7) << IRQ_CAN0_ERR_POS
) |
73 ((CONFIG_IRQ_SPORT2_RX
- 7) << IRQ_SPORT2_RX_POS
) |
74 ((CONFIG_IRQ_SPORT2_TX
- 7) << IRQ_SPORT2_TX_POS
) |
75 ((CONFIG_IRQ_SPORT3_RX
- 7) << IRQ_SPORT3_RX_POS
) |
76 ((CONFIG_IRQ_SPORT3_TX
- 7) << IRQ_SPORT3_TX_POS
) |
77 ((CONFIG_IRQ_EPPI1
- 7) << IRQ_EPPI1_POS
) |
78 ((CONFIG_IRQ_EPPI2
- 7) << IRQ_EPPI2_POS
) |
79 ((CONFIG_IRQ_SPI1
- 7) << IRQ_SPI1_POS
));
81 bfin_write_SIC_IAR5(((CONFIG_IRQ_SPI2
- 7) << IRQ_SPI2_POS
) |
82 ((CONFIG_IRQ_UART1_RX
- 7) << IRQ_UART1_RX_POS
) |
83 ((CONFIG_IRQ_UART1_TX
- 7) << IRQ_UART1_TX_POS
) |
84 ((CONFIG_IRQ_ATAPI_RX
- 7) << IRQ_ATAPI_RX_POS
) |
85 ((CONFIG_IRQ_ATAPI_TX
- 7) << IRQ_ATAPI_TX_POS
) |
86 ((CONFIG_IRQ_TWI0
- 7) << IRQ_TWI0_POS
) |
87 ((CONFIG_IRQ_TWI1
- 7) << IRQ_TWI1_POS
) |
88 ((CONFIG_IRQ_CAN0_RX
- 7) << IRQ_CAN0_RX_POS
));
90 bfin_write_SIC_IAR6(((CONFIG_IRQ_CAN0_TX
- 7) << IRQ_CAN0_TX_POS
) |
91 ((CONFIG_IRQ_MDMAS2
- 7) << IRQ_MDMAS2_POS
) |
92 ((CONFIG_IRQ_MDMAS3
- 7) << IRQ_MDMAS3_POS
) |
93 ((CONFIG_IRQ_MXVR_ERR
- 7) << IRQ_MXVR_ERR_POS
) |
94 ((CONFIG_IRQ_MXVR_MSG
- 7) << IRQ_MXVR_MSG_POS
) |
95 ((CONFIG_IRQ_MXVR_PKT
- 7) << IRQ_MXVR_PKT_POS
) |
96 ((CONFIG_IRQ_EPPI1_ERR
- 7) << IRQ_EPPI1_ERR_POS
) |
97 ((CONFIG_IRQ_EPPI2_ERR
- 7) << IRQ_EPPI2_ERR_POS
));
99 bfin_write_SIC_IAR7(((CONFIG_IRQ_UART3_ERR
- 7) << IRQ_UART3_ERR_POS
) |
100 ((CONFIG_IRQ_HOST_ERR
- 7) << IRQ_HOST_ERR_POS
) |
101 ((CONFIG_IRQ_PIXC_ERR
- 7) << IRQ_PIXC_ERR_POS
) |
102 ((CONFIG_IRQ_NFC_ERR
- 7) << IRQ_NFC_ERR_POS
) |
103 ((CONFIG_IRQ_ATAPI_ERR
- 7) << IRQ_ATAPI_ERR_POS
) |
104 ((CONFIG_IRQ_CAN1_ERR
- 7) << IRQ_CAN1_ERR_POS
) |
105 ((CONFIG_IRQ_HS_DMA_ERR
- 7) << IRQ_HS_DMA_ERR_POS
));
107 bfin_write_SIC_IAR8(((CONFIG_IRQ_PIXC_IN0
- 7) << IRQ_PIXC_IN1_POS
) |
108 ((CONFIG_IRQ_PIXC_IN1
- 7) << IRQ_PIXC_IN1_POS
) |
109 ((CONFIG_IRQ_PIXC_OUT
- 7) << IRQ_PIXC_OUT_POS
) |
110 ((CONFIG_IRQ_SDH
- 7) << IRQ_SDH_POS
) |
111 ((CONFIG_IRQ_CNT
- 7) << IRQ_CNT_POS
) |
112 ((CONFIG_IRQ_KEY
- 7) << IRQ_KEY_POS
) |
113 ((CONFIG_IRQ_CAN1_RX
- 7) << IRQ_CAN1_RX_POS
) |
114 ((CONFIG_IRQ_CAN1_TX
- 7) << IRQ_CAN1_TX_POS
));
116 bfin_write_SIC_IAR9(((CONFIG_IRQ_SDH_MASK0
- 7) << IRQ_SDH_MASK0_POS
) |
117 ((CONFIG_IRQ_SDH_MASK1
- 7) << IRQ_SDH_MASK1_POS
) |
118 ((CONFIG_IRQ_USB_INT0
- 7) << IRQ_USB_INT0_POS
) |
119 ((CONFIG_IRQ_USB_INT1
- 7) << IRQ_USB_INT1_POS
) |
120 ((CONFIG_IRQ_USB_INT2
- 7) << IRQ_USB_INT2_POS
) |
121 ((CONFIG_IRQ_USB_DMA
- 7) << IRQ_USB_DMA_POS
) |
122 ((CONFIG_IRQ_OTPSEC
- 7) << IRQ_OTPSEC_POS
));
124 bfin_write_SIC_IAR10(((CONFIG_IRQ_TIMER0
- 7) << IRQ_TIMER0_POS
) |
125 ((CONFIG_IRQ_TIMER1
- 7) << IRQ_TIMER1_POS
));
127 bfin_write_SIC_IAR11(((CONFIG_IRQ_TIMER2
- 7) << IRQ_TIMER2_POS
) |
128 ((CONFIG_IRQ_TIMER3
- 7) << IRQ_TIMER3_POS
) |
129 ((CONFIG_IRQ_TIMER4
- 7) << IRQ_TIMER4_POS
) |
130 ((CONFIG_IRQ_TIMER5
- 7) << IRQ_TIMER5_POS
) |
131 ((CONFIG_IRQ_TIMER6
- 7) << IRQ_TIMER6_POS
) |
132 ((CONFIG_IRQ_TIMER7
- 7) << IRQ_TIMER7_POS
) |
133 ((CONFIG_IRQ_PINT2
- 7) << IRQ_PINT2_POS
) |
134 ((CONFIG_IRQ_PINT3
- 7) << IRQ_PINT3_POS
));
