Linux 2.6.25-rc4
[linux-2.6/next.git] / arch / mips / kernel / mips-mt.c
blob640fb0cc6e393050355750d02c10c027c6b30e37
1 /*
2 * General MIPS MT support routines, usable in AP/SP, SMVP, or SMTC kernels
3 * Copyright (C) 2005 Mips Technologies, Inc
4 */
6 #include <linux/device.h>
7 #include <linux/kallsyms.h>
8 #include <linux/kernel.h>
9 #include <linux/sched.h>
10 #include <linux/module.h>
11 #include <linux/interrupt.h>
12 #include <linux/security.h>
14 #include <asm/cpu.h>
15 #include <asm/processor.h>
16 #include <asm/atomic.h>
17 #include <asm/system.h>
18 #include <asm/hardirq.h>
19 #include <asm/mmu_context.h>
20 #include <asm/mipsmtregs.h>
21 #include <asm/r4kcache.h>
22 #include <asm/cacheflush.h>
24 int vpelimit;
26 static int __init maxvpes(char *str)
28 get_option(&str, &vpelimit);
30 return 1;
33 __setup("maxvpes=", maxvpes);
35 int tclimit;
37 static int __init maxtcs(char *str)
39 get_option(&str, &tclimit);
41 return 1;
44 __setup("maxtcs=", maxtcs);
47 * Dump new MIPS MT state for the core. Does not leave TCs halted.
48 * Takes an argument which taken to be a pre-call MVPControl value.
51 void mips_mt_regdump(unsigned long mvpctl)
53 unsigned long flags;
54 unsigned long vpflags;
55 unsigned long mvpconf0;
56 int nvpe;
57 int ntc;
58 int i;
59 int tc;
60 unsigned long haltval;
61 unsigned long tcstatval;
62 #ifdef CONFIG_MIPS_MT_SMTC
63 void smtc_soft_dump(void);
64 #endif /* CONFIG_MIPT_MT_SMTC */
66 local_irq_save(flags);
67 vpflags = dvpe();
68 printk("=== MIPS MT State Dump ===\n");
69 printk("-- Global State --\n");
70 printk(" MVPControl Passed: %08lx\n", mvpctl);
71 printk(" MVPControl Read: %08lx\n", vpflags);
72 printk(" MVPConf0 : %08lx\n", (mvpconf0 = read_c0_mvpconf0()));
73 nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
74 ntc = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
75 printk("-- per-VPE State --\n");
76 for (i = 0; i < nvpe; i++) {
77 for (tc = 0; tc < ntc; tc++) {
78 settc(tc);
79 if ((read_tc_c0_tcbind() & TCBIND_CURVPE) == i) {
80 printk(" VPE %d\n", i);
81 printk(" VPEControl : %08lx\n",
82 read_vpe_c0_vpecontrol());
83 printk(" VPEConf0 : %08lx\n",
84 read_vpe_c0_vpeconf0());
85 printk(" VPE%d.Status : %08lx\n",
86 i, read_vpe_c0_status());
87 printk(" VPE%d.EPC : %08lx ",
88 i, read_vpe_c0_epc());
89 print_symbol("%s\n", read_vpe_c0_epc());
90 printk(" VPE%d.Cause : %08lx\n",
91 i, read_vpe_c0_cause());
92 printk(" VPE%d.Config7 : %08lx\n",
93 i, read_vpe_c0_config7());
94 break; /* Next VPE */
98 printk("-- per-TC State --\n");
99 for (tc = 0; tc < ntc; tc++) {
100 settc(tc);
101 if (read_tc_c0_tcbind() == read_c0_tcbind()) {
102 /* Are we dumping ourself? */
103 haltval = 0; /* Then we're not halted, and mustn't be */
104 tcstatval = flags; /* And pre-dump TCStatus is flags */
105 printk(" TC %d (current TC with VPE EPC above)\n", tc);
106 } else {
107 haltval = read_tc_c0_tchalt();
108 write_tc_c0_tchalt(1);
109 tcstatval = read_tc_c0_tcstatus();
110 printk(" TC %d\n", tc);
112 printk(" TCStatus : %08lx\n", tcstatval);
113 printk(" TCBind : %08lx\n", read_tc_c0_tcbind());
114 printk(" TCRestart : %08lx ", read_tc_c0_tcrestart());
115 print_symbol("%s\n", read_tc_c0_tcrestart());
116 printk(" TCHalt : %08lx\n", haltval);
117 printk(" TCContext : %08lx\n", read_tc_c0_tccontext());
118 if (!haltval)
119 write_tc_c0_tchalt(0);
121 #ifdef CONFIG_MIPS_MT_SMTC
122 smtc_soft_dump();
123 #endif /* CONFIG_MIPT_MT_SMTC */
124 printk("===========================\n");
125 evpe(vpflags);
126 local_irq_restore(flags);
129 static int mt_opt_norps = 0;
130 static int mt_opt_rpsctl = -1;
131 static int mt_opt_nblsu = -1;
132 static int mt_opt_forceconfig7 = 0;
133 static int mt_opt_config7 = -1;
135 static int __init rps_disable(char *s)
137 mt_opt_norps = 1;
138 return 1;
140 __setup("norps", rps_disable);
142 static int __init rpsctl_set(char *str)
144 get_option(&str, &mt_opt_rpsctl);
145 return 1;
147 __setup("rpsctl=", rpsctl_set);
149 static int __init nblsu_set(char *str)
151 get_option(&str, &mt_opt_nblsu);
152 return 1;
154 __setup("nblsu=", nblsu_set);
156 static int __init config7_set(char *str)
158 get_option(&str, &mt_opt_config7);
159 mt_opt_forceconfig7 = 1;
160 return 1;
162 __setup("config7=", config7_set);
164 /* Experimental cache flush control parameters that should go away some day */
165 int mt_protiflush = 0;
166 int mt_protdflush = 0;
167 int mt_n_iflushes = 1;
168 int mt_n_dflushes = 1;
170 static int __init set_protiflush(char *s)
172 mt_protiflush = 1;
173 return 1;
175 __setup("protiflush", set_protiflush);
177 static int __init set_protdflush(char *s)
179 mt_protdflush = 1;
180 return 1;
182 __setup("protdflush", set_protdflush);
184 static int __init niflush(char *s)
186 get_option(&s, &mt_n_iflushes);
187 return 1;
189 __setup("niflush=", niflush);
191 static int __init ndflush(char *s)
193 get_option(&s, &mt_n_dflushes);
194 return 1;
196 __setup("ndflush=", ndflush);
198 static unsigned int itc_base = 0;
200 static int __init set_itc_base(char *str)
202 get_option(&str, &itc_base);
203 return 1;
206 __setup("itcbase=", set_itc_base);
208 void mips_mt_set_cpuoptions(void)
210 unsigned int oconfig7 = read_c0_config7();
211 unsigned int nconfig7 = oconfig7;
213 if (mt_opt_norps) {
214 printk("\"norps\" option deprectated: use \"rpsctl=\"\n");
216 if (mt_opt_rpsctl >= 0) {
217 printk("34K return prediction stack override set to %d.\n",
218 mt_opt_rpsctl);
219 if (mt_opt_rpsctl)
220 nconfig7 |= (1 << 2);
221 else
222 nconfig7 &= ~(1 << 2);
224 if (mt_opt_nblsu >= 0) {
225 printk("34K ALU/LSU sync override set to %d.\n", mt_opt_nblsu);
226 if (mt_opt_nblsu)
227 nconfig7 |= (1 << 5);
228 else
229 nconfig7 &= ~(1 << 5);
231 if (mt_opt_forceconfig7) {
232 printk("CP0.Config7 forced to 0x%08x.\n", mt_opt_config7);
233 nconfig7 = mt_opt_config7;
235 if (oconfig7 != nconfig7) {
236 __asm__ __volatile("sync");
237 write_c0_config7(nconfig7);
238 ehb();
239 printk("Config7: 0x%08x\n", read_c0_config7());
242 /* Report Cache management debug options */
243 if (mt_protiflush)
244 printk("I-cache flushes single-threaded\n");
245 if (mt_protdflush)
246 printk("D-cache flushes single-threaded\n");
247 if (mt_n_iflushes != 1)
248 printk("I-Cache Flushes Repeated %d times\n", mt_n_iflushes);
249 if (mt_n_dflushes != 1)
250 printk("D-Cache Flushes Repeated %d times\n", mt_n_dflushes);
252 if (itc_base != 0) {
254 * Configure ITC mapping. This code is very
255 * specific to the 34K core family, which uses
256 * a special mode bit ("ITC") in the ErrCtl
257 * register to enable access to ITC control
258 * registers via cache "tag" operations.
260 unsigned long ectlval;
261 unsigned long itcblkgrn;
263 /* ErrCtl register is known as "ecc" to Linux */
264 ectlval = read_c0_ecc();
265 write_c0_ecc(ectlval | (0x1 << 26));
266 ehb();
267 #define INDEX_0 (0x80000000)
268 #define INDEX_8 (0x80000008)
269 /* Read "cache tag" for Dcache pseudo-index 8 */
270 cache_op(Index_Load_Tag_D, INDEX_8);
271 ehb();
272 itcblkgrn = read_c0_dtaglo();
273 itcblkgrn &= 0xfffe0000;
274 /* Set for 128 byte pitch of ITC cells */
275 itcblkgrn |= 0x00000c00;
276 /* Stage in Tag register */
277 write_c0_dtaglo(itcblkgrn);
278 ehb();
279 /* Write out to ITU with CACHE op */
280 cache_op(Index_Store_Tag_D, INDEX_8);
281 /* Now set base address, and turn ITC on with 0x1 bit */
282 write_c0_dtaglo((itc_base & 0xfffffc00) | 0x1 );
283 ehb();
284 /* Write out to ITU with CACHE op */
285 cache_op(Index_Store_Tag_D, INDEX_0);
286 write_c0_ecc(ectlval);
287 ehb();
288 printk("Mapped %ld ITC cells starting at 0x%08x\n",
289 ((itcblkgrn & 0x7fe00000) >> 20), itc_base);
294 * Function to protect cache flushes from concurrent execution
295 * depends on MP software model chosen.
298 void mt_cflush_lockdown(void)
300 #ifdef CONFIG_MIPS_MT_SMTC
301 void smtc_cflush_lockdown(void);
303 smtc_cflush_lockdown();
304 #endif /* CONFIG_MIPS_MT_SMTC */
305 /* FILL IN VSMP and AP/SP VERSIONS HERE */
308 void mt_cflush_release(void)
310 #ifdef CONFIG_MIPS_MT_SMTC
311 void smtc_cflush_release(void);
313 smtc_cflush_release();
314 #endif /* CONFIG_MIPS_MT_SMTC */
315 /* FILL IN VSMP and AP/SP VERSIONS HERE */
318 struct class *mt_class;
320 static int __init mt_init(void)
322 struct class *mtc;
324 mtc = class_create(THIS_MODULE, "mt");
325 if (IS_ERR(mtc))
326 return PTR_ERR(mtc);
328 mt_class = mtc;
330 return 0;
333 subsys_initcall(mt_init);