arch/mips/pmc-sierra/yosemite/setup.c

   1 /*
   2  *  Copyright (C) 2003 PMC-Sierra Inc.
   3  *  Author: Manish Lachwani (lachwani@pmc-sierra.com)
   4  *
   5  * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
   6  *
   7  *  This program is free software; you can redistribute  it and/or modify it
   8  *  under  the terms of  the GNU General  Public License as published by the
   9  *  Free Software Foundation;  either version 2 of the  License, or (at your
  10  *  option) any later version.
  11  *
  12  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  13  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  14  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  15  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  16  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  17  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  18  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  19  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  20  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  21  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  22  *
  23  *  You should have received a copy of the  GNU General Public License along
  24  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  25  *  675 Mass Ave, Cambridge, MA 02139, USA.
  26  */
  27 #include <linux/bcd.h>
  28 #include <linux/init.h>
  29 #include <linux/kernel.h>
  30 #include <linux/types.h>
  31 #include <linux/mm.h>
  32 #include <linux/bootmem.h>
  33 #include <linux/swap.h>
  34 #include <linux/ioport.h>
  35 #include <linux/sched.h>
  36 #include <linux/interrupt.h>
  37 #include <linux/timex.h>
  38 #include <linux/termios.h>
  39 #include <linux/tty.h>
  40 #include <linux/serial.h>
  41 #include <linux/serial_core.h>
  42 #include <linux/serial_8250.h>
  43
  44 #include <asm/time.h>
  45 #include <asm/bootinfo.h>
  46 #include <asm/page.h>
  47 #include <asm/io.h>
  48 #include <asm/irq.h>
  49 #include <asm/processor.h>
  50 #include <asm/reboot.h>
  51 #include <asm/serial.h>
  52 #include <asm/titan_dep.h>
  53 #include <asm/m48t37.h>
  54
  55 #include "setup.h"
  56
  57 unsigned char titan_ge_mac_addr_base[6] = {
  58         // 0x00, 0x03, 0xcc, 0x1d, 0x22, 0x00
  59         0x00, 0xe0, 0x04, 0x00, 0x00, 0x21
  60 };
  61
  62 unsigned long cpu_clock_freq;
  63 unsigned long yosemite_base;
  64
  65 static struct m48t37_rtc *m48t37_base;
  66
  67 void __init bus_error_init(void)
  68 {
  69         /* Do nothing */
  70 }
  71
  72
  73 unsigned long read_persistent_clock(void)
  74 {
  75         unsigned int year, month, day, hour, min, sec;
  76         unsigned long flags;
  77
  78         spin_lock_irqsave(&rtc_lock, flags);
  79         /* Stop the update to the time */
  80         m48t37_base->control = 0x40;
  81
  82         year = BCD2BIN(m48t37_base->year);
  83         year += BCD2BIN(m48t37_base->century) * 100;
  84
  85         month = BCD2BIN(m48t37_base->month);
  86         day = BCD2BIN(m48t37_base->date);
  87         hour = BCD2BIN(m48t37_base->hour);
  88         min = BCD2BIN(m48t37_base->min);
  89         sec = BCD2BIN(m48t37_base->sec);
  90
  91         /* Start the update to the time again */
  92         m48t37_base->control = 0x00;
  93         spin_unlock_irqrestore(&rtc_lock, flags);
  94
  95         return mktime(year, month, day, hour, min, sec);
  96 }
  97
  98 int rtc_mips_set_time(unsigned long tim)
  99 {
 100         struct rtc_time tm;
 101         unsigned long flags;
 102
 103         /*
 104          * Convert to a more useful format -- note months count from 0
 105          * and years from 1900
 106          */
 107         rtc_time_to_tm(tim, &tm);
 108         tm.tm_year += 1900;
 109         tm.tm_mon += 1;
 110
 111         spin_lock_irqsave(&rtc_lock, flags);
 112         /* enable writing */
 113         m48t37_base->control = 0x80;
 114
 115         /* year */
 116         m48t37_base->year = BIN2BCD(tm.tm_year % 100);
 117         m48t37_base->century = BIN2BCD(tm.tm_year / 100);
 118
 119         /* month */
 120         m48t37_base->month = BIN2BCD(tm.tm_mon);
 121
 122         /* day */
 123         m48t37_base->date = BIN2BCD(tm.tm_mday);
 124
 125         /* hour/min/sec */
 126         m48t37_base->hour = BIN2BCD(tm.tm_hour);
 127         m48t37_base->min = BIN2BCD(tm.tm_min);
 128         m48t37_base->sec = BIN2BCD(tm.tm_sec);
 129
 130         /* day of week -- not really used, but let's keep it up-to-date */
 131         m48t37_base->day = BIN2BCD(tm.tm_wday + 1);
 132
 133         /* disable writing */
 134         m48t37_base->control = 0x00;
 135         spin_unlock_irqrestore(&rtc_lock, flags);
 136
 137         return 0;
 138 }
 139
 140 void __init plat_time_init(void)
 141 {
 142         mips_hpt_frequency = cpu_clock_freq / 2;
 143 mips_hpt_frequency = 33000000 * 3 * 5;
 144 }
 145
 146 /* No other usable initialization hook than this ...  */
 147 extern void (*late_time_init)(void);
 148
 149 unsigned long ocd_base;
 150
 151 EXPORT_SYMBOL(ocd_base);
 152
 153 /*
 154  * Common setup before any secondaries are started
 155  */
 156
 157 #define TITAN_UART_CLK          3686400
 158 #define TITAN_SERIAL_BASE_BAUD  (TITAN_UART_CLK / 16)
 159 #define TITAN_SERIAL_IRQ        4
 160 #define TITAN_SERIAL_BASE       0xfd000008UL
 161
 162 static void __init py_map_ocd(void)
 163 {
 164         ocd_base = (unsigned long) ioremap(OCD_BASE, OCD_SIZE);
 165         if (!ocd_base)
 166                 panic("Mapping OCD failed - game over.  Your score is 0.");
 167
 168         /* Kludge for PMON bug ... */
 169         OCD_WRITE(0x0710, 0x0ffff029);
 170 }
 171
 172 static void __init py_uart_setup(void)
 173 {
 174 #ifdef CONFIG_SERIAL_8250
 175         struct uart_port up;
 176
 177         /*
 178          * Register to interrupt zero because we share the interrupt with
 179          * the serial driver which we don't properly support yet.
 180          */
 181         memset(&up, 0, sizeof(up));
 182         up.membase      = (unsigned char *) ioremap(TITAN_SERIAL_BASE, 8);
 183         up.irq          = TITAN_SERIAL_IRQ;
 184         up.uartclk      = TITAN_UART_CLK;
 185         up.regshift     = 0;
 186         up.iotype       = UPIO_MEM;
 187         up.flags        = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
 188         up.line         = 0;
 189
 190         if (early_serial_setup(&up))
 191                 printk(KERN_ERR "Early serial init of port 0 failed\n");
 192 #endif /* CONFIG_SERIAL_8250 */
 193 }
 194
 195 static void __init py_rtc_setup(void)
 196 {
 197         m48t37_base = ioremap(YOSEMITE_RTC_BASE, YOSEMITE_RTC_SIZE);
 198         if (!m48t37_base)
 199                 printk(KERN_ERR "Mapping the RTC failed\n");
 200 }
 201
 202 /* Not only time init but that's what the hook it's called through is named */
 203 static void __init py_late_time_init(void)
 204 {
 205         py_map_ocd();
 206         py_uart_setup();
 207         py_rtc_setup();
 208 }
 209
 210 void __init plat_mem_setup(void)
 211 {
 212         late_time_init = py_late_time_init;
 213
 214         /* Add memory regions */
 215         add_memory_region(0x00000000, 0x10000000, BOOT_MEM_RAM);
 216
 217 #if 0 /* XXX Crash ...  */
 218         OCD_WRITE(RM9000x2_OCD_HTSC,
 219                   OCD_READ(RM9000x2_OCD_HTSC) | HYPERTRANSPORT_ENABLE);
 220
 221         /* Set the BAR. Shifted mode */
 222         OCD_WRITE(RM9000x2_OCD_HTBAR0, HYPERTRANSPORT_BAR0_ADDR);
 223         OCD_WRITE(RM9000x2_OCD_HTMASK0, HYPERTRANSPORT_SIZE0);
 224 #endif
 225 }