arch/ppc/kernel/traps.c

   1 /*
   2  *  Copyright (C) 1995-1996  Gary Thomas (gdt@linuxppc.org)
   3  *
   4  *  This program is free software; you can redistribute it and/or
   5  *  modify it under the terms of the GNU General Public License
   6  *  as published by the Free Software Foundation; either version
   7  *  2 of the License, or (at your option) any later version.
   8  *
   9  *  Modified by Cort Dougan (cort@cs.nmt.edu)
  10  *  and Paul Mackerras (paulus@cs.anu.edu.au)
  11  */
  12
  13 /*
  14  * This file handles the architecture-dependent parts of hardware exceptions
  15  */
  16
  17 #include <linux/errno.h>
  18 #include <linux/sched.h>
  19 #include <linux/kernel.h>
  20 #include <linux/mm.h>
  21 #include <linux/stddef.h>
  22 #include <linux/unistd.h>
  23 #include <linux/ptrace.h>
  24 #include <linux/slab.h>
  25 #include <linux/user.h>
  26 #include <linux/a.out.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/init.h>
  29 #include <linux/module.h>
  30 #include <linux/prctl.h>
  31 #include <linux/bug.h>
  32
  33 #include <asm/pgtable.h>
  34 #include <asm/uaccess.h>
  35 #include <asm/system.h>
  36 #include <asm/io.h>
  37 #include <asm/reg.h>
  38 #include <asm/xmon.h>
  39 #include <asm/pmc.h>
  40
  41 #ifdef CONFIG_XMON
  42 extern int xmon_bpt(struct pt_regs *regs);
  43 extern int xmon_sstep(struct pt_regs *regs);
  44 extern int xmon_iabr_match(struct pt_regs *regs);
  45 extern int xmon_dabr_match(struct pt_regs *regs);
  46
  47 int (*debugger)(struct pt_regs *regs) = xmon;
  48 int (*debugger_bpt)(struct pt_regs *regs) = xmon_bpt;
  49 int (*debugger_sstep)(struct pt_regs *regs) = xmon_sstep;
  50 int (*debugger_iabr_match)(struct pt_regs *regs) = xmon_iabr_match;
  51 int (*debugger_dabr_match)(struct pt_regs *regs) = xmon_dabr_match;
  52 void (*debugger_fault_handler)(struct pt_regs *regs);
  53 #else
  54 #ifdef CONFIG_KGDB
  55 int (*debugger)(struct pt_regs *regs);
  56 int (*debugger_bpt)(struct pt_regs *regs);
  57 int (*debugger_sstep)(struct pt_regs *regs);
  58 int (*debugger_iabr_match)(struct pt_regs *regs);
  59 int (*debugger_dabr_match)(struct pt_regs *regs);
  60 void (*debugger_fault_handler)(struct pt_regs *regs);
  61 #else
  62 #define debugger(regs)                  do { } while (0)
  63 #define debugger_bpt(regs)              0
  64 #define debugger_sstep(regs)            0
  65 #define debugger_iabr_match(regs)       0
  66 #define debugger_dabr_match(regs)       0
  67 #define debugger_fault_handler          ((void (*)(struct pt_regs *))0)
  68 #endif
  69 #endif
  70
  71 /*
  72  * Trap & Exception support
  73  */
  74
  75 DEFINE_SPINLOCK(die_lock);
  76
  77 int die(const char * str, struct pt_regs * fp, long err)
  78 {
  79         static int die_counter;
  80         int nl = 0;
  81         console_verbose();
  82         spin_lock_irq(&die_lock);
  83         printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
  84 #ifdef CONFIG_PREEMPT
  85         printk("PREEMPT ");
  86         nl = 1;
  87 #endif
  88 #ifdef CONFIG_SMP
  89         printk("SMP NR_CPUS=%d ", NR_CPUS);
  90         nl = 1;
  91 #endif
  92         if (nl)
  93                 printk("\n");
  94         show_regs(fp);
  95         add_taint(TAINT_DIE);
  96         spin_unlock_irq(&die_lock);
  97         /* do_exit() should take care of panic'ing from an interrupt
  98          * context so we don't handle it here
  99          */
 100         do_exit(err);
 101 }
 102
 103 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
 104 {
 105         siginfo_t info;
 106
 107         if (!user_mode(regs)) {
 108                 debugger(regs);
 109                 die("Exception in kernel mode", regs, signr);
 110         }
 111         info.si_signo = signr;
 112         info.si_errno = 0;
 113         info.si_code = code;
 114         info.si_addr = (void __user *) addr;
 115         force_sig_info(signr, &info, current);
 116
 117         /*
 118          * Init gets no signals that it doesn't have a handler for.
 119          * That's all very well, but if it has caused a synchronous
 120          * exception and we ignore the resulting signal, it will just
 121          * generate the same exception over and over again and we get
 122          * nowhere.  Better to kill it and let the kernel panic.
 123          */
 124         if (is_global_init(current)) {
 125                 __sighandler_t handler;
 126
 127                 spin_lock_irq(&current->sighand->siglock);
 128                 handler = current->sighand->action[signr-1].sa.sa_handler;
 129                 spin_unlock_irq(&current->sighand->siglock);
 130                 if (handler == SIG_DFL) {
 131                         /* init has generated a synchronous exception
 132                            and it doesn't have a handler for the signal */
 133                         printk(KERN_CRIT "init has generated signal %d "
 134                                "but has no handler for it\n", signr);
 135                         do_exit(signr);
 136                 }
 137         }
 138 }
 139
 140 /*
 141  * I/O accesses can cause machine checks on powermacs.
 142  * Check if the NIP corresponds to the address of a sync
 143  * instruction for which there is an entry in the exception
 144  * table.
 145  * Note that the 601 only takes a machine check on TEA
 146  * (transfer error ack) signal assertion, and does not
 147  * set any of the top 16 bits of SRR1.
 148  *  -- paulus.
 149  */
 150 static inline int check_io_access(struct pt_regs *regs)
 151 {
 152 #if defined CONFIG_8xx
 153         unsigned long msr = regs->msr;
 154         const struct exception_table_entry *entry;
 155         unsigned int *nip = (unsigned int *)regs->nip;
 156
 157         if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
 158             && (entry = search_exception_tables(regs->nip)) != NULL) {
 159                 /*
 160                  * Check that it's a sync instruction, or somewhere
 161                  * in the twi; isync; nop sequence that inb/inw/inl uses.
 162                  * As the address is in the exception table
 163                  * we should be able to read the instr there.
 164                  * For the debug message, we look at the preceding
 165                  * load or store.
 166                  */
 167                 if (*nip == 0x60000000)         /* nop */
 168                         nip -= 2;
 169                 else if (*nip == 0x4c00012c)    /* isync */
 170                         --nip;
 171                 /* eieio from I/O string functions */
 172                 else if ((*nip) == 0x7c0006ac || *(nip+1) == 0x7c0006ac)
 173                         nip += 2;
 174                 if (*nip == 0x7c0004ac || (*nip >> 26) == 3 ||
 175                         (*(nip+1) >> 26) == 3) {
 176                         /* sync or twi */
 177                         unsigned int rb;
 178
 179                         --nip;
 180                         rb = (*nip >> 11) & 0x1f;
 181                         printk(KERN_DEBUG "%s bad port %lx at %p\n",
 182                                (*nip & 0x100)? "OUT to": "IN from",
 183                                regs->gpr[rb] - _IO_BASE, nip);
 184                         regs->msr |= MSR_RI;
 185                         regs->nip = entry->fixup;
 186                         return 1;
 187                 }
 188         }
 189 #endif /* CONFIG_8xx */
 190         return 0;
 191 }
 192
 193 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
 194 /* On 4xx, the reason for the machine check or program exception
 195    is in the ESR. */
 196 #define get_reason(regs)        ((regs)->dsisr)
 197 #define get_mc_reason(regs)     ((regs)->dsisr)
 198 #define REASON_FP               ESR_FP
 199 #define REASON_ILLEGAL          (ESR_PIL | ESR_PUO)
 200 #define REASON_PRIVILEGED       ESR_PPR
 201 #define REASON_TRAP             ESR_PTR
 202
 203 /* single-step stuff */
 204 #define single_stepping(regs)   (current->thread.dbcr0 & DBCR0_IC)
 205 #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC)
 206
 207 #else
 208 /* On non-4xx, the reason for the machine check or program
 209    exception is in the MSR. */
 210 #define get_reason(regs)        ((regs)->msr)
 211 #define get_mc_reason(regs)     ((regs)->msr)
 212 #define REASON_FP               0x100000
 213 #define REASON_ILLEGAL          0x80000
 214 #define REASON_PRIVILEGED       0x40000
 215 #define REASON_TRAP             0x20000
 216
 217 #define single_stepping(regs)   ((regs)->msr & MSR_SE)
 218 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
 219 #endif
 220
 221 /*
 222  * This is "fall-back" implementation for configurations
 223  * which don't provide platform-specific machine check info
 224  */
 225 void __attribute__ ((weak))
 226 platform_machine_check(struct pt_regs *regs)
 227 {
 228 }
 229
 230 #if defined(CONFIG_4xx)
 231 int machine_check_4xx(struct pt_regs *regs)
 232 {
 233         unsigned long reason = get_mc_reason(regs);
 234
 235         if (reason & ESR_IMCP) {
 236                 printk("Instruction");
 237                 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
 238         } else
 239                 printk("Data");
 240         printk(" machine check in kernel mode.\n");
 241
 242         return 0;
 243 }
 244
 245 int machine_check_440A(struct pt_regs *regs)
 246 {
 247         unsigned long reason = get_mc_reason(regs);
 248
 249         printk("Machine check in kernel mode.\n");
 250         if (reason & ESR_IMCP){
 251                 printk("Instruction Synchronous Machine Check exception\n");
 252                 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
 253         }
 254         else {
 255                 u32 mcsr = mfspr(SPRN_MCSR);
 256                 if (mcsr & MCSR_IB)
 257                         printk("Instruction Read PLB Error\n");
 258                 if (mcsr & MCSR_DRB)
 259                         printk("Data Read PLB Error\n");
 260                 if (mcsr & MCSR_DWB)
 261                         printk("Data Write PLB Error\n");
 262                 if (mcsr & MCSR_TLBP)
 263                         printk("TLB Parity Error\n");
 264                 if (mcsr & MCSR_ICP){
 265                         flush_instruction_cache();
 266                         printk("I-Cache Parity Error\n");
 267                 }
 268                 if (mcsr & MCSR_DCSP)
 269                         printk("D-Cache Search Parity Error\n");
 270                 if (mcsr & MCSR_DCFP)
 271                         printk("D-Cache Flush Parity Error\n");
 272                 if (mcsr & MCSR_IMPE)
 273                         printk("Machine Check exception is imprecise\n");
 274
 275                 /* Clear MCSR */
 276                 mtspr(SPRN_MCSR, mcsr);
 277         }
 278         return 0;
 279 }
 280 #else
 281 int machine_check_generic(struct pt_regs *regs)
 282 {
 283         unsigned long reason = get_mc_reason(regs);
 284
 285         printk("Machine check in kernel mode.\n");
 286         printk("Caused by (from SRR1=%lx): ", reason);
 287         switch (reason & 0x601F0000) {
 288         case 0x80000:
 289                 printk("Machine check signal\n");
 290                 break;
 291         case 0:         /* for 601 */
 292         case 0x40000:
 293         case 0x140000:  /* 7450 MSS error and TEA */
 294                 printk("Transfer error ack signal\n");
 295                 break;
 296         case 0x20000:
 297                 printk("Data parity error signal\n");
 298                 break;
 299         case 0x10000:
 300                 printk("Address parity error signal\n");
 301                 break;
 302         case 0x20000000:
 303                 printk("L1 Data Cache error\n");
 304                 break;
 305         case 0x40000000:
 306                 printk("L1 Instruction Cache error\n");
 307                 break;
 308         case 0x00100000:
 309                 printk("L2 data cache parity error\n");
 310                 break;
 311         default:
 312                 printk("Unknown values in msr\n");
 313         }
 314         return 0;
 315 }
 316 #endif /* everything else */
 317
 318 void machine_check_exception(struct pt_regs *regs)
 319 {
 320         int recover = 0;
 321
 322         if (cur_cpu_spec->machine_check)
 323                 recover = cur_cpu_spec->machine_check(regs);
 324         if (recover > 0)
 325                 return;
 326
 327         if (user_mode(regs)) {
 328                 regs->msr |= MSR_RI;
 329                 _exception(SIGBUS, regs, BUS_ADRERR, regs->nip);
 330                 return;
 331         }
 332
 333 #if defined(CONFIG_8xx) && defined(CONFIG_PCI)
 334         /* the qspan pci read routines can cause machine checks -- Cort */
 335         bad_page_fault(regs, regs->dar, SIGBUS);
 336         return;
 337 #endif
 338
 339         if (debugger_fault_handler) {
 340                 debugger_fault_handler(regs);
 341                 regs->msr |= MSR_RI;
 342                 return;
 343         }
 344
 345         if (check_io_access(regs))
 346                 return;
 347
 348         /*
 349          * Optional platform-provided routine to print out
 350          * additional info, e.g. bus error registers.
 351          */
 352         platform_machine_check(regs);
 353
 354         debugger(regs);
 355         die("machine check", regs, SIGBUS);
 356 }
 357
 358 void SMIException(struct pt_regs *regs)
 359 {
 360         debugger(regs);
 361 #if !(defined(CONFIG_XMON) || defined(CONFIG_KGDB))
 362         show_regs(regs);
 363         panic("System Management Interrupt");
 364 #endif
 365 }
 366
 367 void unknown_exception(struct pt_regs *regs)
 368 {
 369         printk("Bad trap at PC: %lx, MSR: %lx, vector=%lx    %s\n",
 370                regs->nip, regs->msr, regs->trap, print_tainted());
 371         _exception(SIGTRAP, regs, 0, 0);
 372 }
 373
 374 void instruction_breakpoint_exception(struct pt_regs *regs)
 375 {
 376         if (debugger_iabr_match(regs))
 377                 return;
 378         _exception(SIGTRAP, regs, TRAP_BRKPT, 0);
 379 }
 380
 381 void RunModeException(struct pt_regs *regs)
 382 {
 383         _exception(SIGTRAP, regs, 0, 0);
 384 }
 385
 386 /* Illegal instruction emulation support.  Originally written to
 387  * provide the PVR to user applications using the mfspr rd, PVR.
 388  * Return non-zero if we can't emulate, or -EFAULT if the associated
 389  * memory access caused an access fault.  Return zero on success.
 390  *
 391  * There are a couple of ways to do this, either "decode" the instruction
 392  * or directly match lots of bits.  In this case, matching lots of
 393  * bits is faster and easier.
 394  *
 395  */
 396 #define INST_MFSPR_PVR          0x7c1f42a6
 397 #define INST_MFSPR_PVR_MASK     0xfc1fffff
 398
 399 #define INST_DCBA               0x7c0005ec
 400 #define INST_DCBA_MASK          0x7c0007fe
 401
 402 #define INST_MCRXR              0x7c000400
 403 #define INST_MCRXR_MASK         0x7c0007fe
 404
 405 #define INST_STRING             0x7c00042a
 406 #define INST_STRING_MASK        0x7c0007fe
 407 #define INST_STRING_GEN_MASK    0x7c00067e
 408 #define INST_LSWI               0x7c0004aa
 409 #define INST_LSWX               0x7c00042a
 410 #define INST_STSWI              0x7c0005aa
 411 #define INST_STSWX              0x7c00052a
 412
 413 static int emulate_string_inst(struct pt_regs *regs, u32 instword)
 414 {
 415         u8 rT = (instword >> 21) & 0x1f;
 416         u8 rA = (instword >> 16) & 0x1f;
 417         u8 NB_RB = (instword >> 11) & 0x1f;
 418         u32 num_bytes;
 419         unsigned long EA;
 420         int pos = 0;
 421
 422         /* Early out if we are an invalid form of lswx */
 423         if ((instword & INST_STRING_MASK) == INST_LSWX)
 424                 if ((rT == rA) || (rT == NB_RB))
 425                         return -EINVAL;
 426
 427         EA = (rA == 0) ? 0 : regs->gpr[rA];
 428
 429         switch (instword & INST_STRING_MASK) {
 430                 case INST_LSWX:
 431                 case INST_STSWX:
 432                         EA += NB_RB;
 433                         num_bytes = regs->xer & 0x7f;
 434                         break;
 435                 case INST_LSWI:
 436                 case INST_STSWI:
 437                         num_bytes = (NB_RB == 0) ? 32 : NB_RB;
 438                         break;
 439                 default:
 440                         return -EINVAL;
 441         }
 442
 443         while (num_bytes != 0)
 444         {
 445                 u8 val;
 446                 u32 shift = 8 * (3 - (pos & 0x3));
 447
 448                 switch ((instword & INST_STRING_MASK)) {
 449                         case INST_LSWX:
 450                         case INST_LSWI:
 451                                 if (get_user(val, (u8 __user *)EA))
 452                                         return -EFAULT;
 453                                 /* first time updating this reg,
 454                                  * zero it out */
 455                                 if (pos == 0)
 456                                         regs->gpr[rT] = 0;
 457                                 regs->gpr[rT] |= val << shift;
 458                                 break;
 459                         case INST_STSWI:
 460                         case INST_STSWX:
 461                                 val = regs->gpr[rT] >> shift;
 462                                 if (put_user(val, (u8 __user *)EA))
 463                                         return -EFAULT;
 464                                 break;
 465                 }
 466                 /* move EA to next address */
 467                 EA += 1;
 468                 num_bytes--;
 469
 470                 /* manage our position within the register */
 471                 if (++pos == 4) {
 472                         pos = 0;
 473                         if (++rT == 32)
 474                                 rT = 0;
 475                 }
 476         }
 477
 478         return 0;
 479 }
 480
 481 static int emulate_instruction(struct pt_regs *regs)
 482 {
 483         u32 instword;
 484         u32 rd;
 485
 486         if (!user_mode(regs))
 487                 return -EINVAL;
 488         CHECK_FULL_REGS(regs);
 489
 490         if (get_user(instword, (u32 __user *)(regs->nip)))
 491                 return -EFAULT;
 492
 493         /* Emulate the mfspr rD, PVR.
 494          */
 495         if ((instword & INST_MFSPR_PVR_MASK) == INST_MFSPR_PVR) {
 496                 rd = (instword >> 21) & 0x1f;
 497                 regs->gpr[rd] = mfspr(SPRN_PVR);
 498                 return 0;
 499         }
 500
 501         /* Emulating the dcba insn is just a no-op.  */
 502         if ((instword & INST_DCBA_MASK) == INST_DCBA)
 503                 return 0;
 504
 505         /* Emulate the mcrxr insn.  */
 506         if ((instword & INST_MCRXR_MASK) == INST_MCRXR) {
 507                 int shift = (instword >> 21) & 0x1c;
 508                 unsigned long msk = 0xf0000000UL >> shift;
 509
 510                 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
 511                 regs->xer &= ~0xf0000000UL;
 512                 return 0;
 513         }
 514
 515         /* Emulate load/store string insn. */
 516         if ((instword & INST_STRING_GEN_MASK) == INST_STRING)
 517                 return emulate_string_inst(regs, instword);
 518
 519         return -EINVAL;
 520 }
 521
 522 /*
 523  * After we have successfully emulated an instruction, we have to
 524  * check if the instruction was being single-stepped, and if so,
 525  * pretend we got a single-step exception.  This was pointed out
 526  * by Kumar Gala.  -- paulus
 527  */
 528 static void emulate_single_step(struct pt_regs *regs)
 529 {
 530         if (single_stepping(regs)) {
 531                 clear_single_step(regs);
 532                 _exception(SIGTRAP, regs, TRAP_TRACE, 0);
 533         }
 534 }
 535
 536 int is_valid_bugaddr(unsigned long addr)
 537 {
 538         return addr >= PAGE_OFFSET;
 539 }
 540
 541 void program_check_exception(struct pt_regs *regs)
 542 {
 543         unsigned int reason = get_reason(regs);
 544         extern int do_mathemu(struct pt_regs *regs);
 545
 546 #ifdef CONFIG_MATH_EMULATION
 547         /* (reason & REASON_ILLEGAL) would be the obvious thing here,
 548          * but there seems to be a hardware bug on the 405GP (RevD)
 549          * that means ESR is sometimes set incorrectly - either to
 550          * ESR_DST (!?) or 0.  In the process of chasing this with the
 551          * hardware people - not sure if it can happen on any illegal
 552          * instruction or only on FP instructions, whether there is a
 553          * pattern to occurrences etc. -dgibson 31/Mar/2003 */
 554         if (!(reason & REASON_TRAP) && do_mathemu(regs) == 0) {
 555                 emulate_single_step(regs);
 556                 return;
 557         }
 558 #endif /* CONFIG_MATH_EMULATION */
 559
 560         if (reason & REASON_FP) {
 561                 /* IEEE FP exception */
 562                 int code = 0;
 563                 u32 fpscr;
 564
 565                 /* We must make sure the FP state is consistent with
 566                  * our MSR_FP in regs
 567                  */
 568                 preempt_disable();
 569                 if (regs->msr & MSR_FP)
 570                         giveup_fpu(current);
 571                 preempt_enable();
 572
 573                 fpscr = current->thread.fpscr.val;
 574                 fpscr &= fpscr << 22;   /* mask summary bits with enables */
 575                 if (fpscr & FPSCR_VX)
 576                         code = FPE_FLTINV;
 577                 else if (fpscr & FPSCR_OX)
 578                         code = FPE_FLTOVF;
 579                 else if (fpscr & FPSCR_UX)
 580                         code = FPE_FLTUND;
 581                 else if (fpscr & FPSCR_ZX)
 582                         code = FPE_FLTDIV;
 583                 else if (fpscr & FPSCR_XX)
 584                         code = FPE_FLTRES;
 585                 _exception(SIGFPE, regs, code, regs->nip);
 586                 return;
 587         }
 588
 589         if (reason & REASON_TRAP) {
 590                 /* trap exception */
 591                 if (debugger_bpt(regs))
 592                         return;
 593
 594                 if (!(regs->msr & MSR_PR) &&  /* not user-mode */
 595                     report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) {
 596                         regs->nip += 4;
 597                         return;
 598                 }
 599                 _exception(SIGTRAP, regs, TRAP_BRKPT, 0);
 600                 return;
 601         }
 602
 603         /* Try to emulate it if we should. */
 604         if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
 605                 switch (emulate_instruction(regs)) {
 606                 case 0:
 607                         regs->nip += 4;
 608                         emulate_single_step(regs);
 609                         return;
 610                 case -EFAULT:
 611                         _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
 612                         return;
 613                 }
 614         }
 615
 616         if (reason & REASON_PRIVILEGED)
 617                 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
 618         else
 619                 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
 620 }
 621
 622 void single_step_exception(struct pt_regs *regs)
 623 {
 624         regs->msr &= ~(MSR_SE | MSR_BE);  /* Turn off 'trace' bits */
 625         if (debugger_sstep(regs))
 626                 return;
 627         _exception(SIGTRAP, regs, TRAP_TRACE, 0);
 628 }
 629
 630 void alignment_exception(struct pt_regs *regs)
 631 {
 632         int sig, code, fixed = 0;
 633
 634         fixed = fix_alignment(regs);
 635         if (fixed == 1) {
 636                 regs->nip += 4; /* skip over emulated instruction */
 637                 emulate_single_step(regs);
 638                 return;
 639         }
 640         if (fixed == -EFAULT) {
 641                 sig = SIGSEGV;
 642                 code = SEGV_ACCERR;
 643         } else {
 644                 sig = SIGBUS;
 645                 code = BUS_ADRALN;
 646         }
 647         if (user_mode(regs))
 648                 _exception(sig, regs, code, regs->dar);
 649         else
 650                 bad_page_fault(regs, regs->dar, sig);
 651 }
 652
 653 void StackOverflow(struct pt_regs *regs)
 654 {
 655         printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n",
 656                current, regs->gpr[1]);
 657         debugger(regs);
 658         show_regs(regs);
 659         panic("kernel stack overflow");
 660 }
 661
 662 void nonrecoverable_exception(struct pt_regs *regs)
 663 {
 664         printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n",
 665                regs->nip, regs->msr);
 666         debugger(regs);
 667         die("nonrecoverable exception", regs, SIGKILL);
 668 }
 669
 670 void trace_syscall(struct pt_regs *regs)
 671 {
 672         printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld    %s\n",
 673                current, current->pid, regs->nip, regs->link, regs->gpr[0],
 674                regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted());
 675 }
 676
 677 #ifdef CONFIG_8xx
 678 void SoftwareEmulation(struct pt_regs *regs)
 679 {
 680         extern int do_mathemu(struct pt_regs *);
 681         extern int Soft_emulate_8xx(struct pt_regs *);
 682         int errcode;
 683
 684         CHECK_FULL_REGS(regs);
 685
 686         if (!user_mode(regs)) {
 687                 debugger(regs);
 688                 die("Kernel Mode Software FPU Emulation", regs, SIGFPE);
 689         }
 690
 691 #ifdef CONFIG_MATH_EMULATION
 692         errcode = do_mathemu(regs);
 693 #else
 694         errcode = Soft_emulate_8xx(regs);
 695 #endif
 696         if (errcode) {
 697                 if (errcode > 0)
 698                         _exception(SIGFPE, regs, 0, 0);
 699                 else if (errcode == -EFAULT)
 700                         _exception(SIGSEGV, regs, 0, 0);
 701                 else
 702                         _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
 703         } else
 704                 emulate_single_step(regs);
 705 }
 706 #endif /* CONFIG_8xx */
 707
 708 #if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
 709
 710 void DebugException(struct pt_regs *regs, unsigned long debug_status)
 711 {
 712         if (debug_status & DBSR_IC) {   /* instruction completion */
 713                 regs->msr &= ~MSR_DE;
 714                 if (user_mode(regs)) {
 715                         current->thread.dbcr0 &= ~DBCR0_IC;
 716                 } else {
 717                         /* Disable instruction completion */
 718                         mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
 719                         /* Clear the instruction completion event */
 720                         mtspr(SPRN_DBSR, DBSR_IC);
 721                         if (debugger_sstep(regs))
 722                                 return;
 723                 }
 724                 _exception(SIGTRAP, regs, TRAP_TRACE, 0);
 725         }
 726 }
 727 #endif /* CONFIG_4xx || CONFIG_BOOKE */
 728
 729 #if !defined(CONFIG_TAU_INT)
 730 void TAUException(struct pt_regs *regs)
 731 {
 732         printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx    %s\n",
 733                regs->nip, regs->msr, regs->trap, print_tainted());
 734 }
 735 #endif /* CONFIG_INT_TAU */
 736
 737 /*
 738  * FP unavailable trap from kernel - print a message, but let
 739  * the task use FP in the kernel until it returns to user mode.
 740  */
 741 void kernel_fp_unavailable_exception(struct pt_regs *regs)
 742 {
 743         regs->msr |= MSR_FP;
 744         printk(KERN_ERR "floating point used in kernel (task=%p, pc=%lx)\n",
 745                current, regs->nip);
 746 }
 747
 748 void altivec_unavailable_exception(struct pt_regs *regs)
 749 {
 750         static int kernel_altivec_count;
 751
 752 #ifndef CONFIG_ALTIVEC
 753         if (user_mode(regs)) {
 754                 /* A user program has executed an altivec instruction,
 755                    but this kernel doesn't support altivec. */
 756                 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
 757                 return;
 758         }
 759 #endif
 760         /* The kernel has executed an altivec instruction without
 761            first enabling altivec.  Whinge but let it do it. */
 762         if (++kernel_altivec_count < 10)
 763                 printk(KERN_ERR "AltiVec used in kernel (task=%p, pc=%lx)\n",
 764                        current, regs->nip);
 765         regs->msr |= MSR_VEC;
 766 }
 767
 768 #ifdef CONFIG_ALTIVEC
 769 void altivec_assist_exception(struct pt_regs *regs)
 770 {
 771         int err;
 772
 773         preempt_disable();
 774         if (regs->msr & MSR_VEC)
 775                 giveup_altivec(current);
 776         preempt_enable();
 777         if (!user_mode(regs)) {
 778                 printk(KERN_ERR "altivec assist exception in kernel mode"
 779                        " at %lx\n", regs->nip);
 780                 debugger(regs);
 781                 die("altivec assist exception", regs, SIGFPE);
 782                 return;
 783         }
 784
 785         err = emulate_altivec(regs);
 786         if (err == 0) {
 787                 regs->nip += 4;         /* skip emulated instruction */
 788                 emulate_single_step(regs);
 789                 return;
 790         }
 791
 792         if (err == -EFAULT) {
 793                 /* got an error reading the instruction */
 794                 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
 795         } else {
 796                 /* didn't recognize the instruction */
 797                 /* XXX quick hack for now: set the non-Java bit in the VSCR */
 798                 printk(KERN_ERR "unrecognized altivec instruction "
 799                        "in %s at %lx\n", current->comm, regs->nip);
 800                 current->thread.vscr.u[3] |= 0x10000;
 801         }
 802 }
 803 #endif /* CONFIG_ALTIVEC */
 804
 805 #ifdef CONFIG_BOOKE_WDT
 806 /*
 807  * Default handler for a Watchdog exception,
 808  * spins until a reboot occurs
 809  */
 810 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
 811 {
 812         /* Generic WatchdogHandler, implement your own */
 813         mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
 814         return;
 815 }
 816
 817 void WatchdogException(struct pt_regs *regs)
 818 {
 819         printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
 820         WatchdogHandler(regs);
 821 }
 822 #endif
 823
 824 void __init trap_init(void)
 825 {
 826 }