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staging: fix usbip printk format warning
[linux-2.6/next.git] / sound / pci / asihpi / hpi6000.c
blobdf4aed5295dddd33526c12051691456c8800a900
1 /******************************************************************************
2
3 AudioScience HPI driver
4 Copyright (C) 1997-2010 AudioScience Inc. <support@audioscience.com>
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of version 2 of the GNU General Public License as
8 published by the Free Software Foundation;
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18
19 Hardware Programming Interface (HPI) for AudioScience ASI6200 series adapters.
20 These PCI bus adapters are based on the TI C6711 DSP.
21
22 Exported functions:
23 void HPI_6000(struct hpi_message *phm, struct hpi_response *phr)
24
25 #defines
26 HIDE_PCI_ASSERTS to show the PCI asserts
27 PROFILE_DSP2 get profile data from DSP2 if present (instead of DSP 1)
28
29 (C) Copyright AudioScience Inc. 1998-2003
30 *******************************************************************************/
31 #define SOURCEFILE_NAME "hpi6000.c"
32
33 #include "hpi_internal.h"
34 #include "hpimsginit.h"
35 #include "hpidebug.h"
36 #include "hpi6000.h"
37 #include "hpidspcd.h"
38 #include "hpicmn.h"
39
40 #define HPI_HIF_BASE (0x00000200) /* start of C67xx internal RAM */
41 #define HPI_HIF_ADDR(member) \
42 (HPI_HIF_BASE + offsetof(struct hpi_hif_6000, member))
43 #define HPI_HIF_ERROR_MASK 0x4000
44
45 /* HPI6000 specific error codes */
46 #define HPI6000_ERROR_BASE 900 /* not actually used anywhere */
47
48 /* operational/messaging errors */
49 #define HPI6000_ERROR_MSG_RESP_IDLE_TIMEOUT 901
50
51 #define HPI6000_ERROR_MSG_RESP_GET_RESP_ACK 903
52 #define HPI6000_ERROR_MSG_GET_ADR 904
53 #define HPI6000_ERROR_RESP_GET_ADR 905
54 #define HPI6000_ERROR_MSG_RESP_BLOCKWRITE32 906
55 #define HPI6000_ERROR_MSG_RESP_BLOCKREAD32 907
56
57 #define HPI6000_ERROR_CONTROL_CACHE_PARAMS 909
58
59 #define HPI6000_ERROR_SEND_DATA_IDLE_TIMEOUT 911
60 #define HPI6000_ERROR_SEND_DATA_ACK 912
61 #define HPI6000_ERROR_SEND_DATA_ADR 913
62 #define HPI6000_ERROR_SEND_DATA_TIMEOUT 914
63 #define HPI6000_ERROR_SEND_DATA_CMD 915
64 #define HPI6000_ERROR_SEND_DATA_WRITE 916
65 #define HPI6000_ERROR_SEND_DATA_IDLECMD 917
66
67 #define HPI6000_ERROR_GET_DATA_IDLE_TIMEOUT 921
68 #define HPI6000_ERROR_GET_DATA_ACK 922
69 #define HPI6000_ERROR_GET_DATA_CMD 923
70 #define HPI6000_ERROR_GET_DATA_READ 924
71 #define HPI6000_ERROR_GET_DATA_IDLECMD 925
72
73 #define HPI6000_ERROR_CONTROL_CACHE_ADDRLEN 951
74 #define HPI6000_ERROR_CONTROL_CACHE_READ 952
75 #define HPI6000_ERROR_CONTROL_CACHE_FLUSH 953
76
77 #define HPI6000_ERROR_MSG_RESP_GETRESPCMD 961
78 #define HPI6000_ERROR_MSG_RESP_IDLECMD 962
79
80 /* Initialisation/bootload errors */
81 #define HPI6000_ERROR_UNHANDLED_SUBSYS_ID 930
82
83 /* can't access PCI2040 */
84 #define HPI6000_ERROR_INIT_PCI2040 931
85 /* can't access DSP HPI i/f */
86 #define HPI6000_ERROR_INIT_DSPHPI 932
87 /* can't access internal DSP memory */
88 #define HPI6000_ERROR_INIT_DSPINTMEM 933
89 /* can't access SDRAM - test#1 */
90 #define HPI6000_ERROR_INIT_SDRAM1 934
91 /* can't access SDRAM - test#2 */
92 #define HPI6000_ERROR_INIT_SDRAM2 935
93
94 #define HPI6000_ERROR_INIT_VERIFY 938
95
96 #define HPI6000_ERROR_INIT_NOACK 939
97
98 #define HPI6000_ERROR_INIT_PLDTEST1 941
99 #define HPI6000_ERROR_INIT_PLDTEST2 942
100
101 /* local defines */
102
103 #define HIDE_PCI_ASSERTS
104 #define PROFILE_DSP2
105
106 /* for PCI2040 i/f chip */
107 /* HPI CSR registers */
108 /* word offsets from CSR base */
109 /* use when io addresses defined as u32 * */
110
111 #define INTERRUPT_EVENT_SET 0
112 #define INTERRUPT_EVENT_CLEAR 1
113 #define INTERRUPT_MASK_SET 2
114 #define INTERRUPT_MASK_CLEAR 3
115 #define HPI_ERROR_REPORT 4
116 #define HPI_RESET 5
117 #define HPI_DATA_WIDTH 6
118
119 #define MAX_DSPS 2
120 /* HPI registers, spaced 8K bytes = 2K words apart */
121 #define DSP_SPACING 0x800
122
123 #define CONTROL 0x0000
124 #define ADDRESS 0x0200
125 #define DATA_AUTOINC 0x0400
126 #define DATA 0x0600
127
128 #define TIMEOUT 500000
129
130 struct dsp_obj {
131 __iomem u32 *prHPI_control;
132 __iomem u32 *prHPI_address;
133 __iomem u32 *prHPI_data;
134 __iomem u32 *prHPI_data_auto_inc;
135 char c_dsp_rev; /*A, B */
136 u32 control_cache_address_on_dsp;
137 u32 control_cache_length_on_dsp;
138 struct hpi_adapter_obj *pa_parent_adapter;
139 };
140
141 struct hpi_hw_obj {
142 __iomem u32 *dw2040_HPICSR;
143 __iomem u32 *dw2040_HPIDSP;
144
145 u16 num_dsp;
146 struct dsp_obj ado[MAX_DSPS];
147
148 u32 message_buffer_address_on_dsp;
149 u32 response_buffer_address_on_dsp;
150 u32 pCI2040HPI_error_count;
151
152 struct hpi_control_cache_single control_cache[HPI_NMIXER_CONTROLS];
153 struct hpi_control_cache *p_cache;
154 };
155
156 static u16 hpi6000_dsp_block_write32(struct hpi_adapter_obj *pao,
157 u16 dsp_index, u32 hpi_address, u32 *source, u32 count);
158 static u16 hpi6000_dsp_block_read32(struct hpi_adapter_obj *pao,
159 u16 dsp_index, u32 hpi_address, u32 *dest, u32 count);
160
161 static short hpi6000_adapter_boot_load_dsp(struct hpi_adapter_obj *pao,
162 u32 *pos_error_code);
163 static short hpi6000_check_PCI2040_error_flag(struct hpi_adapter_obj *pao,
164 u16 read_or_write);
165 #define H6READ 1
166 #define H6WRITE 0
167
168 static short hpi6000_update_control_cache(struct hpi_adapter_obj *pao,
169 struct hpi_message *phm);
170 static short hpi6000_message_response_sequence(struct hpi_adapter_obj *pao,
171 u16 dsp_index, struct hpi_message *phm, struct hpi_response *phr);
172
173 static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm,
174 struct hpi_response *phr);
175
176 static short hpi6000_wait_dsp_ack(struct hpi_adapter_obj *pao, u16 dsp_index,
177 u32 ack_value);
178
179 static short hpi6000_send_host_command(struct hpi_adapter_obj *pao,
180 u16 dsp_index, u32 host_cmd);
181
182 static void hpi6000_send_dsp_interrupt(struct dsp_obj *pdo);
183
184 static short hpi6000_send_data(struct hpi_adapter_obj *pao, u16 dsp_index,
185 struct hpi_message *phm, struct hpi_response *phr);
186
187 static short hpi6000_get_data(struct hpi_adapter_obj *pao, u16 dsp_index,
188 struct hpi_message *phm, struct hpi_response *phr);
189
190 static void hpi_write_word(struct dsp_obj *pdo, u32 address, u32 data);
191
192 static u32 hpi_read_word(struct dsp_obj *pdo, u32 address);
193
194 static void hpi_write_block(struct dsp_obj *pdo, u32 address, u32 *pdata,
195 u32 length);
196
197 static void hpi_read_block(struct dsp_obj *pdo, u32 address, u32 *pdata,
198 u32 length);
199
200 static void subsys_create_adapter(struct hpi_message *phm,
201 struct hpi_response *phr);
202
203 static void adapter_delete(struct hpi_adapter_obj *pao,
204 struct hpi_message *phm, struct hpi_response *phr);
205
206 static void adapter_get_asserts(struct hpi_adapter_obj *pao,
207 struct hpi_message *phm, struct hpi_response *phr);
208
209 static short create_adapter_obj(struct hpi_adapter_obj *pao,
210 u32 *pos_error_code);
211
212 static void delete_adapter_obj(struct hpi_adapter_obj *pao);
213
214 /* local globals */
215
216 static u16 gw_pci_read_asserts; /* used to count PCI2040 errors */
217 static u16 gw_pci_write_asserts; /* used to count PCI2040 errors */
218
219 static void subsys_message(struct hpi_message *phm, struct hpi_response *phr)
220 {
221 switch (phm->function) {
222 case HPI_SUBSYS_CREATE_ADAPTER:
223 subsys_create_adapter(phm, phr);
224 break;
225 default:
226 phr->error = HPI_ERROR_INVALID_FUNC;
227 break;
228 }
229 }
230
231 static void control_message(struct hpi_adapter_obj *pao,
232 struct hpi_message *phm, struct hpi_response *phr)
233 {
234 switch (phm->function) {
235 case HPI_CONTROL_GET_STATE:
236 if (pao->has_control_cache) {
237 u16 err;
238 err = hpi6000_update_control_cache(pao, phm);
239
240 if (err) {
241 if (err >= HPI_ERROR_BACKEND_BASE) {
242 phr->error =
243 HPI_ERROR_CONTROL_CACHING;
244 phr->specific_error = err;
245 } else {
246 phr->error = err;
247 }
248 break;
249 }
250
251 if (hpi_check_control_cache(((struct hpi_hw_obj *)
252 pao->priv)->p_cache, phm,
253 phr))
254 break;
255 }
256 hw_message(pao, phm, phr);
257 break;
258 case HPI_CONTROL_SET_STATE:
259 hw_message(pao, phm, phr);
260 hpi_cmn_control_cache_sync_to_msg(((struct hpi_hw_obj *)pao->
261 priv)->p_cache, phm, phr);
262 break;
263
264 case HPI_CONTROL_GET_INFO:
265 default:
266 hw_message(pao, phm, phr);
267 break;
268 }
269 }
270
271 static void adapter_message(struct hpi_adapter_obj *pao,
272 struct hpi_message *phm, struct hpi_response *phr)
273 {
274 switch (phm->function) {
275 case HPI_ADAPTER_GET_ASSERT:
276 adapter_get_asserts(pao, phm, phr);
277 break;
278
279 case HPI_ADAPTER_DELETE:
280 adapter_delete(pao, phm, phr);
281 break;
282
283 default:
284 hw_message(pao, phm, phr);
285 break;
286 }
287 }
288
289 static void outstream_message(struct hpi_adapter_obj *pao,
290 struct hpi_message *phm, struct hpi_response *phr)
291 {
292 switch (phm->function) {
293 case HPI_OSTREAM_HOSTBUFFER_ALLOC:
294 case HPI_OSTREAM_HOSTBUFFER_FREE:
295 /* Don't let these messages go to the HW function because
296 * they're called without locking the spinlock.
297 * For the HPI6000 adapters the HW would return
298 * HPI_ERROR_INVALID_FUNC anyway.
299 */
300 phr->error = HPI_ERROR_INVALID_FUNC;
301 break;
302 default:
303 hw_message(pao, phm, phr);
304 return;
305 }
306 }
307
308 static void instream_message(struct hpi_adapter_obj *pao,
309 struct hpi_message *phm, struct hpi_response *phr)
310 {
311
312 switch (phm->function) {
313 case HPI_ISTREAM_HOSTBUFFER_ALLOC:
314 case HPI_ISTREAM_HOSTBUFFER_FREE:
315 /* Don't let these messages go to the HW function because
316 * they're called without locking the spinlock.
317 * For the HPI6000 adapters the HW would return
318 * HPI_ERROR_INVALID_FUNC anyway.
319 */
320 phr->error = HPI_ERROR_INVALID_FUNC;
321 break;
322 default:
323 hw_message(pao, phm, phr);
324 return;
325 }
326 }
327
328 /************************************************************************/
329 /** HPI_6000()
330 * Entry point from HPIMAN
331 * All calls to the HPI start here
332 */
333 void HPI_6000(struct hpi_message *phm, struct hpi_response *phr)
334 {
335 struct hpi_adapter_obj *pao = NULL;
336
337 if (phm->object != HPI_OBJ_SUBSYSTEM) {
338 pao = hpi_find_adapter(phm->adapter_index);
339 if (!pao) {
340 hpi_init_response(phr, phm->object, phm->function,
341 HPI_ERROR_BAD_ADAPTER_NUMBER);
342 HPI_DEBUG_LOG(DEBUG, "invalid adapter index: %d \n",
343 phm->adapter_index);
344 return;
345 }
346
347 /* Don't even try to communicate with crashed DSP */
348 if (pao->dsp_crashed >= 10) {
349 hpi_init_response(phr, phm->object, phm->function,
350 HPI_ERROR_DSP_HARDWARE);
351 HPI_DEBUG_LOG(DEBUG, "adapter %d dsp crashed\n",
352 phm->adapter_index);
353 return;
354 }
355 }
356 /* Init default response including the size field */
357 if (phm->function != HPI_SUBSYS_CREATE_ADAPTER)
358 hpi_init_response(phr, phm->object, phm->function,
359 HPI_ERROR_PROCESSING_MESSAGE);
360
361 switch (phm->type) {
362 case HPI_TYPE_MESSAGE:
363 switch (phm->object) {
364 case HPI_OBJ_SUBSYSTEM:
365 subsys_message(phm, phr);
366 break;
367
368 case HPI_OBJ_ADAPTER:
369 phr->size =
370 sizeof(struct hpi_response_header) +
371 sizeof(struct hpi_adapter_res);
372 adapter_message(pao, phm, phr);
373 break;
374
375 case HPI_OBJ_CONTROL:
376 control_message(pao, phm, phr);
377 break;
378
379 case HPI_OBJ_OSTREAM:
380 outstream_message(pao, phm, phr);
381 break;
382
383 case HPI_OBJ_ISTREAM:
384 instream_message(pao, phm, phr);
385 break;
386
387 default:
388 hw_message(pao, phm, phr);
389 break;
390 }
391 break;
392
393 default:
394 phr->error = HPI_ERROR_INVALID_TYPE;
395 break;
396 }
397 }
398
399 /************************************************************************/
400 /* SUBSYSTEM */
401
402 /* create an adapter object and initialise it based on resource information
403 * passed in in the message
404 * NOTE - you cannot use this function AND the FindAdapters function at the
405 * same time, the application must use only one of them to get the adapters
406 */
407 static void subsys_create_adapter(struct hpi_message *phm,
408 struct hpi_response *phr)
409 {
410 /* create temp adapter obj, because we don't know what index yet */
411 struct hpi_adapter_obj ao;
412 struct hpi_adapter_obj *pao;
413 u32 os_error_code;
414 u16 err = 0;
415 u32 dsp_index = 0;
416
417 HPI_DEBUG_LOG(VERBOSE, "subsys_create_adapter\n");
418
419 memset(&ao, 0, sizeof(ao));
420
421 ao.priv = kzalloc(sizeof(struct hpi_hw_obj), GFP_KERNEL);
422 if (!ao.priv) {
423 HPI_DEBUG_LOG(ERROR, "can't get mem for adapter object\n");
424 phr->error = HPI_ERROR_MEMORY_ALLOC;
425 return;
426 }
427
428 /* create the adapter object based on the resource information */
429 ao.pci = *phm->u.s.resource.r.pci;
430
431 err = create_adapter_obj(&ao, &os_error_code);
432 if (err) {
433 delete_adapter_obj(&ao);
434 if (err >= HPI_ERROR_BACKEND_BASE) {
435 phr->error = HPI_ERROR_DSP_BOOTLOAD;
436 phr->specific_error = err;
437 } else {
438 phr->error = err;
439 }
440
441 phr->u.s.data = os_error_code;
442 return;
443 }
444 /* need to update paParentAdapter */
445 pao = hpi_find_adapter(ao.index);
446 if (!pao) {
447 /* We just added this adapter, why can't we find it!? */
448 HPI_DEBUG_LOG(ERROR, "lost adapter after boot\n");
449 phr->error = HPI_ERROR_BAD_ADAPTER;
450 return;
451 }
452
453 for (dsp_index = 0; dsp_index < MAX_DSPS; dsp_index++) {
454 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
455 phw->ado[dsp_index].pa_parent_adapter = pao;
456 }
457
458 phr->u.s.adapter_type = ao.adapter_type;
459 phr->u.s.adapter_index = ao.index;
460 phr->error = 0;
461 }
462
463 static void adapter_delete(struct hpi_adapter_obj *pao,
464 struct hpi_message *phm, struct hpi_response *phr)
465 {
466 delete_adapter_obj(pao);
467 hpi_delete_adapter(pao);
468 phr->error = 0;
469 }
470
471 /* this routine is called from SubSysFindAdapter and SubSysCreateAdapter */
472 static short create_adapter_obj(struct hpi_adapter_obj *pao,
473 u32 *pos_error_code)
474 {
475 short boot_error = 0;
476 u32 dsp_index = 0;
477 u32 control_cache_size = 0;
478 u32 control_cache_count = 0;
479 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
480
481 /* The PCI2040 has the following address map */
482 /* BAR0 - 4K = HPI control and status registers on PCI2040 (HPI CSR) */
483 /* BAR1 - 32K = HPI registers on DSP */
484 phw->dw2040_HPICSR = pao->pci.ap_mem_base[0];
485 phw->dw2040_HPIDSP = pao->pci.ap_mem_base[1];
486 HPI_DEBUG_LOG(VERBOSE, "csr %p, dsp %p\n", phw->dw2040_HPICSR,
487 phw->dw2040_HPIDSP);
488
489 /* set addresses for the possible DSP HPI interfaces */
490 for (dsp_index = 0; dsp_index < MAX_DSPS; dsp_index++) {
491 phw->ado[dsp_index].prHPI_control =
492 phw->dw2040_HPIDSP + (CONTROL +
493 DSP_SPACING * dsp_index);
494
495 phw->ado[dsp_index].prHPI_address =
496 phw->dw2040_HPIDSP + (ADDRESS +
497 DSP_SPACING * dsp_index);
498 phw->ado[dsp_index].prHPI_data =
499 phw->dw2040_HPIDSP + (DATA + DSP_SPACING * dsp_index);
500
501 phw->ado[dsp_index].prHPI_data_auto_inc =
502 phw->dw2040_HPIDSP + (DATA_AUTOINC +
503 DSP_SPACING * dsp_index);
504
505 HPI_DEBUG_LOG(VERBOSE, "ctl %p, adr %p, dat %p, dat++ %p\n",
506 phw->ado[dsp_index].prHPI_control,
507 phw->ado[dsp_index].prHPI_address,
508 phw->ado[dsp_index].prHPI_data,
509 phw->ado[dsp_index].prHPI_data_auto_inc);
510
511 phw->ado[dsp_index].pa_parent_adapter = pao;
512 }
513
514 phw->pCI2040HPI_error_count = 0;
515 pao->has_control_cache = 0;
516
517 /* Set the default number of DSPs on this card */
518 /* This is (conditionally) adjusted after bootloading */
519 /* of the first DSP in the bootload section. */
520 phw->num_dsp = 1;
521
522 boot_error = hpi6000_adapter_boot_load_dsp(pao, pos_error_code);
523 if (boot_error)
524 return boot_error;
525
526 HPI_DEBUG_LOG(INFO, "bootload DSP OK\n");
527
528 phw->message_buffer_address_on_dsp = 0L;
529 phw->response_buffer_address_on_dsp = 0L;
530
531 /* get info about the adapter by asking the adapter */
532 /* send a HPI_ADAPTER_GET_INFO message */
533 {
534 struct hpi_message hm;
535 struct hpi_response hr0; /* response from DSP 0 */
536 struct hpi_response hr1; /* response from DSP 1 */
537 u16 error = 0;
538
539 HPI_DEBUG_LOG(VERBOSE, "send ADAPTER_GET_INFO\n");
540 memset(&hm, 0, sizeof(hm));
541 hm.type = HPI_TYPE_MESSAGE;
542 hm.size = sizeof(struct hpi_message);
543 hm.object = HPI_OBJ_ADAPTER;
544 hm.function = HPI_ADAPTER_GET_INFO;
545 hm.adapter_index = 0;
546 memset(&hr0, 0, sizeof(hr0));
547 memset(&hr1, 0, sizeof(hr1));
548 hr0.size = sizeof(hr0);
549 hr1.size = sizeof(hr1);
550
551 error = hpi6000_message_response_sequence(pao, 0, &hm, &hr0);
552 if (hr0.error) {
553 HPI_DEBUG_LOG(DEBUG, "message error %d\n", hr0.error);
554 return hr0.error;
555 }
556 if (phw->num_dsp == 2) {
557 error = hpi6000_message_response_sequence(pao, 1, &hm,
558 &hr1);
559 if (error)
560 return error;
561 }
562 pao->adapter_type = hr0.u.ax.info.adapter_type;
563 pao->index = hr0.u.ax.info.adapter_index;
564 }
565
566 memset(&phw->control_cache[0], 0,
567 sizeof(struct hpi_control_cache_single) *
568 HPI_NMIXER_CONTROLS);
569 /* Read the control cache length to figure out if it is turned on */
570 control_cache_size =
571 hpi_read_word(&phw->ado[0],
572 HPI_HIF_ADDR(control_cache_size_in_bytes));
573 if (control_cache_size) {
574 control_cache_count =
575 hpi_read_word(&phw->ado[0],
576 HPI_HIF_ADDR(control_cache_count));
577
578 phw->p_cache =
579 hpi_alloc_control_cache(control_cache_count,
580 control_cache_size, (unsigned char *)
581 &phw->control_cache[0]
582 );
583 if (phw->p_cache)
584 pao->has_control_cache = 1;
585 }
586
587 HPI_DEBUG_LOG(DEBUG, "get adapter info ASI%04X index %d\n",
588 pao->adapter_type, pao->index);
589 pao->open = 0; /* upon creation the adapter is closed */
590
591 if (phw->p_cache)
592 phw->p_cache->adap_idx = pao->index;
593
594 return hpi_add_adapter(pao);
595 }
596
597 static void delete_adapter_obj(struct hpi_adapter_obj *pao)
598 {
599 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
600
601 if (pao->has_control_cache)
602 hpi_free_control_cache(phw->p_cache);
603
604 /* reset DSPs on adapter */
605 iowrite32(0x0003000F, phw->dw2040_HPICSR + HPI_RESET);
606
607 kfree(phw);
608 }
609
610 /************************************************************************/
611 /* ADAPTER */
612
613 static void adapter_get_asserts(struct hpi_adapter_obj *pao,
614 struct hpi_message *phm, struct hpi_response *phr)
615 {
616 #ifndef HIDE_PCI_ASSERTS
617 /* if we have PCI2040 asserts then collect them */
618 if ((gw_pci_read_asserts > 0) || (gw_pci_write_asserts > 0)) {
619 phr->u.ax.assert.p1 =
620 gw_pci_read_asserts * 100 + gw_pci_write_asserts;
621 phr->u.ax.assert.p2 = 0;
622 phr->u.ax.assert.count = 1; /* assert count */
623 phr->u.ax.assert.dsp_index = -1; /* "dsp index" */
624 strcpy(phr->u.ax.assert.sz_message, "PCI2040 error");
625 phr->u.ax.assert.dsp_msg_addr = 0;
626 gw_pci_read_asserts = 0;
627 gw_pci_write_asserts = 0;
628 phr->error = 0;
629 } else
630 #endif
631 hw_message(pao, phm, phr); /*get DSP asserts */
632
633 return;
634 }
635
636 /************************************************************************/
637 /* LOW-LEVEL */
638
639 static short hpi6000_adapter_boot_load_dsp(struct hpi_adapter_obj *pao,
640 u32 *pos_error_code)
641 {
642 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
643 short error;
644 u32 timeout;
645 u32 read = 0;
646 u32 i = 0;
647 u32 data = 0;
648 u32 j = 0;
649 u32 test_addr = 0x80000000;
650 u32 test_data = 0x00000001;
651 u32 dw2040_reset = 0;
652 u32 dsp_index = 0;
653 u32 endian = 0;
654 u32 adapter_info = 0;
655 u32 delay = 0;
656
657 struct dsp_code dsp_code;
658 u16 boot_load_family = 0;
659
660 /* NOTE don't use wAdapterType in this routine. It is not setup yet */
661
662 switch (pao->pci.pci_dev->subsystem_device) {
663 case 0x5100:
664 case 0x5110: /* ASI5100 revB or higher with C6711D */
665 case 0x5200: /* ASI5200 PCIe version of ASI5100 */
666 case 0x6100:
667 case 0x6200:
668 boot_load_family = HPI_ADAPTER_FAMILY_ASI(0x6200);
669 break;
670 default:
671 return HPI6000_ERROR_UNHANDLED_SUBSYS_ID;
672 }
673
674 /* reset all DSPs, indicate two DSPs are present
675 * set RST3-=1 to disconnect HAD8 to set DSP in little endian mode
676 */
677 endian = 0;
678 dw2040_reset = 0x0003000F;
679 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
680
681 /* read back register to make sure PCI2040 chip is functioning
682 * note that bits 4..15 are read-only and so should always return zero,
683 * even though we wrote 1 to them
684 */
685 hpios_delay_micro_seconds(1000);
686 delay = ioread32(phw->dw2040_HPICSR + HPI_RESET);
687
688 if (delay != dw2040_reset) {
689 HPI_DEBUG_LOG(ERROR, "INIT_PCI2040 %x %x\n", dw2040_reset,
690 delay);
691 return HPI6000_ERROR_INIT_PCI2040;
692 }
693
694 /* Indicate that DSP#0,1 is a C6X */
695 iowrite32(0x00000003, phw->dw2040_HPICSR + HPI_DATA_WIDTH);
696 /* set Bit30 and 29 - which will prevent Target aborts from being
697 * issued upon HPI or GP error
698 */
699 iowrite32(0x60000000, phw->dw2040_HPICSR + INTERRUPT_MASK_SET);
700
701 /* isolate DSP HAD8 line from PCI2040 so that
702 * Little endian can be set by pullup
703 */
704 dw2040_reset = dw2040_reset & (~(endian << 3));
705 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
706
707 phw->ado[0].c_dsp_rev = 'B'; /* revB */
708 phw->ado[1].c_dsp_rev = 'B'; /* revB */
709
710 /*Take both DSPs out of reset, setting HAD8 to the correct Endian */
711 dw2040_reset = dw2040_reset & (~0x00000001); /* start DSP 0 */
712 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
713 dw2040_reset = dw2040_reset & (~0x00000002); /* start DSP 1 */
714 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
715
716 /* set HAD8 back to PCI2040, now that DSP set to little endian mode */
717 dw2040_reset = dw2040_reset & (~0x00000008);
718 iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
719 /*delay to allow DSP to get going */
720 hpios_delay_micro_seconds(100);
721
722 /* loop through all DSPs, downloading DSP code */
723 for (dsp_index = 0; dsp_index < phw->num_dsp; dsp_index++) {
724 struct dsp_obj *pdo = &phw->ado[dsp_index];
725
726 /* configure DSP so that we download code into the SRAM */
727 /* set control reg for little endian, HWOB=1 */
728 iowrite32(0x00010001, pdo->prHPI_control);
729
730 /* test access to the HPI address register (HPIA) */
731 test_data = 0x00000001;
732 for (j = 0; j < 32; j++) {
733 iowrite32(test_data, pdo->prHPI_address);
734 data = ioread32(pdo->prHPI_address);
735 if (data != test_data) {
736 HPI_DEBUG_LOG(ERROR, "INIT_DSPHPI %x %x %x\n",
737 test_data, data, dsp_index);
738 return HPI6000_ERROR_INIT_DSPHPI;
739 }
740 test_data = test_data << 1;
741 }
742
743 /* if C6713 the setup PLL to generate 225MHz from 25MHz.
744 * Since the PLLDIV1 read is sometimes wrong, even on a C6713,
745 * we're going to do this unconditionally
746 */
747 /* PLLDIV1 should have a value of 8000 after reset */
748 /*
749 if (HpiReadWord(pdo,0x01B7C118) == 0x8000)
750 */
751 {
752 /* C6713 datasheet says we cannot program PLL from HPI,
753 * and indeed if we try to set the PLL multiply from the
754 * HPI, the PLL does not seem to lock,
755 * so we enable the PLL and use the default of x 7
756 */
757 /* bypass PLL */
758 hpi_write_word(pdo, 0x01B7C100, 0x0000);
759 hpios_delay_micro_seconds(100);
760
761 /* ** use default of PLL x7 ** */
762 /* EMIF = 225/3=75MHz */
763 hpi_write_word(pdo, 0x01B7C120, 0x8002);
764 hpios_delay_micro_seconds(100);
765
766 /* peri = 225/2 */
767 hpi_write_word(pdo, 0x01B7C11C, 0x8001);
768 hpios_delay_micro_seconds(100);
769
770 /* cpu = 225/1 */
771 hpi_write_word(pdo, 0x01B7C118, 0x8000);
772
773 /* ~2ms delay */
774 hpios_delay_micro_seconds(2000);
775
776 /* PLL not bypassed */
777 hpi_write_word(pdo, 0x01B7C100, 0x0001);
778 /* ~2ms delay */
779 hpios_delay_micro_seconds(2000);
780 }
781
782 /* test r/w to internal DSP memory
783 * C6711 has L2 cache mapped to 0x0 when reset
784 *
785 * revB - because of bug 3.0.1 last HPI read
786 * (before HPI address issued) must be non-autoinc
787 */
788 /* test each bit in the 32bit word */
789 for (i = 0; i < 100; i++) {
790 test_addr = 0x00000000;
791 test_data = 0x00000001;
792 for (j = 0; j < 32; j++) {
793 hpi_write_word(pdo, test_addr + i, test_data);
794 data = hpi_read_word(pdo, test_addr + i);
795 if (data != test_data) {
796 HPI_DEBUG_LOG(ERROR,
797 "DSP mem %x %x %x %x\n",
798 test_addr + i, test_data,
799 data, dsp_index);
800
801 return HPI6000_ERROR_INIT_DSPINTMEM;
802 }
803 test_data = test_data << 1;
804 }
805 }
806
807 /* memory map of ASI6200
808 00000000-0000FFFF 16Kx32 internal program
809 01800000-019FFFFF Internal peripheral
810 80000000-807FFFFF CE0 2Mx32 SDRAM running @ 100MHz
811 90000000-9000FFFF CE1 Async peripherals:
812
813 EMIF config
814 ------------
815 Global EMIF control
816 0 -
817 1 -
818 2 -
819 3 CLK2EN = 1 CLKOUT2 enabled
820 4 CLK1EN = 0 CLKOUT1 disabled
821 5 EKEN = 1 <--!! C6713 specific, enables ECLKOUT
822 6 -
823 7 NOHOLD = 1 external HOLD disabled
824 8 HOLDA = 0 HOLDA output is low
825 9 HOLD = 0 HOLD input is low
826 10 ARDY = 1 ARDY input is high
827 11 BUSREQ = 0 BUSREQ output is low
828 12,13 Reserved = 1
829 */
830 hpi_write_word(pdo, 0x01800000, 0x34A8);
831
832 /* EMIF CE0 setup - 2Mx32 Sync DRAM
833 31..28 Wr setup
834 27..22 Wr strobe
835 21..20 Wr hold
836 19..16 Rd setup
837 15..14 -
838 13..8 Rd strobe
839 7..4 MTYPE 0011 Sync DRAM 32bits
840 3 Wr hold MSB
841 2..0 Rd hold
842 */
843 hpi_write_word(pdo, 0x01800008, 0x00000030);
844
845 /* EMIF SDRAM Extension
846 31-21 0
847 20 WR2RD = 0
848 19-18 WR2DEAC = 1
849 17 WR2WR = 0
850 16-15 R2WDQM = 2
851 14-12 RD2WR = 4
852 11-10 RD2DEAC = 1
853 9 RD2RD = 1
854 8-7 THZP = 10b
855 6-5 TWR = 2-1 = 01b (tWR = 10ns)
856 4 TRRD = 0b = 2 ECLK (tRRD = 14ns)
857 3-1 TRAS = 5-1 = 100b (Tras=42ns = 5 ECLK)
858 1 CAS latency = 3 ECLK
859 (for Micron 2M32-7 operating at 100Mhz)
860 */
861
862 /* need to use this else DSP code crashes */
863 hpi_write_word(pdo, 0x01800020, 0x001BDF29);
864
865 /* EMIF SDRAM control - set up for a 2Mx32 SDRAM (512x32x4 bank)
866 31 - -
867 30 SDBSZ 1 4 bank
868 29..28 SDRSZ 00 11 row address pins
869 27..26 SDCSZ 01 8 column address pins
870 25 RFEN 1 refersh enabled
871 24 INIT 1 init SDRAM
872 23..20 TRCD 0001
873 19..16 TRP 0001
874 15..12 TRC 0110
875 11..0 - -
876 */
877 /* need to use this else DSP code crashes */
878 hpi_write_word(pdo, 0x01800018, 0x47117000);
879
880 /* EMIF SDRAM Refresh Timing */
881 hpi_write_word(pdo, 0x0180001C, 0x00000410);
882
883 /*MIF CE1 setup - Async peripherals
884 @100MHz bus speed, each cycle is 10ns,
885 31..28 Wr setup = 1
886 27..22 Wr strobe = 3 30ns
887 21..20 Wr hold = 1
888 19..16 Rd setup =1
889 15..14 Ta = 2
890 13..8 Rd strobe = 3 30ns
891 7..4 MTYPE 0010 Async 32bits
892 3 Wr hold MSB =0
893 2..0 Rd hold = 1
894 */
895 {
896 u32 cE1 =
897 (1L << 28) | (3L << 22) | (1L << 20) | (1L <<
898 16) | (2L << 14) | (3L << 8) | (2L << 4) | 1L;
899 hpi_write_word(pdo, 0x01800004, cE1);
900 }
901
902 /* delay a little to allow SDRAM and DSP to "get going" */
903 hpios_delay_micro_seconds(1000);
904
905 /* test access to SDRAM */
906 {
907 test_addr = 0x80000000;
908 test_data = 0x00000001;
909 /* test each bit in the 32bit word */
910 for (j = 0; j < 32; j++) {
911 hpi_write_word(pdo, test_addr, test_data);
912 data = hpi_read_word(pdo, test_addr);
913 if (data != test_data) {
914 HPI_DEBUG_LOG(ERROR,
915 "DSP dram %x %x %x %x\n",
916 test_addr, test_data, data,
917 dsp_index);
918
919 return HPI6000_ERROR_INIT_SDRAM1;
920 }
921 test_data = test_data << 1;
922 }
923 /* test every Nth address in the DRAM */
924 #define DRAM_SIZE_WORDS 0x200000 /*2_mx32 */
925 #define DRAM_INC 1024
926 test_addr = 0x80000000;
927 test_data = 0x0;
928 for (i = 0; i < DRAM_SIZE_WORDS; i = i + DRAM_INC) {
929 hpi_write_word(pdo, test_addr + i, test_data);
930 test_data++;
931 }
932 test_addr = 0x80000000;
933 test_data = 0x0;
934 for (i = 0; i < DRAM_SIZE_WORDS; i = i + DRAM_INC) {
935 data = hpi_read_word(pdo, test_addr + i);
936 if (data != test_data) {
937 HPI_DEBUG_LOG(ERROR,
938 "DSP dram %x %x %x %x\n",
939 test_addr + i, test_data,
940 data, dsp_index);
941 return HPI6000_ERROR_INIT_SDRAM2;
942 }
943 test_data++;
944 }
945
946 }
947
948 /* write the DSP code down into the DSPs memory */
949 /*HpiDspCode_Open(nBootLoadFamily,&DspCode,pdwOsErrorCode); */
950 dsp_code.ps_dev = pao->pci.pci_dev;
951
952 error = hpi_dsp_code_open(boot_load_family, &dsp_code,
953 pos_error_code);
954
955 if (error)
956 return error;
957
958 while (1) {
959 u32 length;
960 u32 address;
961 u32 type;
962 u32 *pcode;
963
964 error = hpi_dsp_code_read_word(&dsp_code, &length);
965 if (error)
966 break;
967 if (length == 0xFFFFFFFF)
968 break; /* end of code */
969
970 error = hpi_dsp_code_read_word(&dsp_code, &address);
971 if (error)
972 break;
973 error = hpi_dsp_code_read_word(&dsp_code, &type);
974 if (error)
975 break;
976 error = hpi_dsp_code_read_block(length, &dsp_code,
977 &pcode);
978 if (error)
979 break;
980 error = hpi6000_dsp_block_write32(pao, (u16)dsp_index,
981 address, pcode, length);
982 if (error)
983 break;
984 }
985
986 if (error) {
987 hpi_dsp_code_close(&dsp_code);
988 return error;
989 }
990 /* verify that code was written correctly */
991 /* this time through, assume no errors in DSP code file/array */
992 hpi_dsp_code_rewind(&dsp_code);
993 while (1) {
994 u32 length;
995 u32 address;
996 u32 type;
997 u32 *pcode;
998
999 hpi_dsp_code_read_word(&dsp_code, &length);
1000 if (length == 0xFFFFFFFF)
1001 break; /* end of code */
1002
1003 hpi_dsp_code_read_word(&dsp_code, &address);
1004 hpi_dsp_code_read_word(&dsp_code, &type);
1005 hpi_dsp_code_read_block(length, &dsp_code, &pcode);
1006
1007 for (i = 0; i < length; i++) {
1008 data = hpi_read_word(pdo, address);
1009 if (data != *pcode) {
1010 error = HPI6000_ERROR_INIT_VERIFY;
1011 HPI_DEBUG_LOG(ERROR,
1012 "DSP verify %x %x %x %x\n",
1013 address, *pcode, data,
1014 dsp_index);
1015 break;
1016 }
1017 pcode++;
1018 address += 4;
1019 }
1020 if (error)
1021 break;
1022 }
1023 hpi_dsp_code_close(&dsp_code);
1024 if (error)
1025 return error;
1026
1027 /* zero out the hostmailbox */
1028 {
1029 u32 address = HPI_HIF_ADDR(host_cmd);
1030 for (i = 0; i < 4; i++) {
1031 hpi_write_word(pdo, address, 0);
1032 address += 4;
1033 }
1034 }
1035 /* write the DSP number into the hostmailbox */
1036 /* structure before starting the DSP */
1037 hpi_write_word(pdo, HPI_HIF_ADDR(dsp_number), dsp_index);
1038
1039 /* write the DSP adapter Info into the */
1040 /* hostmailbox before starting the DSP */
1041 if (dsp_index > 0)
1042 hpi_write_word(pdo, HPI_HIF_ADDR(adapter_info),
1043 adapter_info);
1044
1045 /* step 3. Start code by sending interrupt */
1046 iowrite32(0x00030003, pdo->prHPI_control);
1047 hpios_delay_micro_seconds(10000);
1048
1049 /* wait for a non-zero value in hostcmd -
1050 * indicating initialization is complete
1051 *
1052 * Init could take a while if DSP checks SDRAM memory
1053 * Was 200000. Increased to 2000000 for ASI8801 so we
1054 * don't get 938 errors.
1055 */
1056 timeout = 2000000;
1057 while (timeout) {
1058 do {
1059 read = hpi_read_word(pdo,
1060 HPI_HIF_ADDR(host_cmd));
1061 } while (--timeout
1062 && hpi6000_check_PCI2040_error_flag(pao,
1063 H6READ));
1064
1065 if (read)
1066 break;
1067 /* The following is a workaround for bug #94:
1068 * Bluescreen on install and subsequent boots on a
1069 * DELL PowerEdge 600SC PC with 1.8GHz P4 and
1070 * ServerWorks chipset. Without this delay the system
1071 * locks up with a bluescreen (NOT GPF or pagefault).
1072 */
1073 else
1074 hpios_delay_micro_seconds(10000);
1075 }
1076 if (timeout == 0)
1077 return HPI6000_ERROR_INIT_NOACK;
1078
1079 /* read the DSP adapter Info from the */
1080 /* hostmailbox structure after starting the DSP */
1081 if (dsp_index == 0) {
1082 /*u32 dwTestData=0; */
1083 u32 mask = 0;
1084
1085 adapter_info =
1086 hpi_read_word(pdo,
1087 HPI_HIF_ADDR(adapter_info));
1088 if (HPI_ADAPTER_FAMILY_ASI
1089 (HPI_HIF_ADAPTER_INFO_EXTRACT_ADAPTER
1090 (adapter_info)) ==
1091 HPI_ADAPTER_FAMILY_ASI(0x6200))
1092 /* all 6200 cards have this many DSPs */
1093 phw->num_dsp = 2;
1094
1095 /* test that the PLD is programmed */
1096 /* and we can read/write 24bits */
1097 #define PLD_BASE_ADDRESS 0x90000000L /*for ASI6100/6200/8800 */
1098
1099 switch (boot_load_family) {
1100 case HPI_ADAPTER_FAMILY_ASI(0x6200):
1101 /* ASI6100/6200 has 24bit path to FPGA */
1102 mask = 0xFFFFFF00L;
1103 /* ASI5100 uses AX6 code, */
1104 /* but has no PLD r/w register to test */
1105 if (HPI_ADAPTER_FAMILY_ASI(pao->pci.pci_dev->
1106 subsystem_device) ==
1107 HPI_ADAPTER_FAMILY_ASI(0x5100))
1108 mask = 0x00000000L;
1109 /* ASI5200 uses AX6 code, */
1110 /* but has no PLD r/w register to test */
1111 if (HPI_ADAPTER_FAMILY_ASI(pao->pci.pci_dev->
1112 subsystem_device) ==
1113 HPI_ADAPTER_FAMILY_ASI(0x5200))
1114 mask = 0x00000000L;
1115 break;
1116 case HPI_ADAPTER_FAMILY_ASI(0x8800):
1117 /* ASI8800 has 16bit path to FPGA */
1118 mask = 0xFFFF0000L;
1119 break;
1120 }
1121 test_data = 0xAAAAAA00L & mask;
1122 /* write to 24 bit Debug register (D31-D8) */
1123 hpi_write_word(pdo, PLD_BASE_ADDRESS + 4L, test_data);
1124 read = hpi_read_word(pdo,
1125 PLD_BASE_ADDRESS + 4L) & mask;
1126 if (read != test_data) {
1127 HPI_DEBUG_LOG(ERROR, "PLD %x %x\n", test_data,
1128 read);
1129 return HPI6000_ERROR_INIT_PLDTEST1;
1130 }
1131 test_data = 0x55555500L & mask;
1132 hpi_write_word(pdo, PLD_BASE_ADDRESS + 4L, test_data);
1133 read = hpi_read_word(pdo,
1134 PLD_BASE_ADDRESS + 4L) & mask;
1135 if (read != test_data) {
1136 HPI_DEBUG_LOG(ERROR, "PLD %x %x\n", test_data,
1137 read);
1138 return HPI6000_ERROR_INIT_PLDTEST2;
1139 }
1140 }
1141 } /* for numDSP */
1142 return 0;
1143 }
1144
1145 #define PCI_TIMEOUT 100
1146
1147 static int hpi_set_address(struct dsp_obj *pdo, u32 address)
1148 {
1149 u32 timeout = PCI_TIMEOUT;
1150
1151 do {
1152 iowrite32(address, pdo->prHPI_address);
1153 } while (hpi6000_check_PCI2040_error_flag(pdo->pa_parent_adapter,
1154 H6WRITE)
1155 && --timeout);
1156
1157 if (timeout)
1158 return 0;
1159
1160 return 1;
1161 }
1162
1163 /* write one word to the HPI port */
1164 static void hpi_write_word(struct dsp_obj *pdo, u32 address, u32 data)
1165 {
1166 if (hpi_set_address(pdo, address))
1167 return;
1168 iowrite32(data, pdo->prHPI_data);
1169 }
1170
1171 /* read one word from the HPI port */
1172 static u32 hpi_read_word(struct dsp_obj *pdo, u32 address)
1173 {
1174 u32 data = 0;
1175
1176 if (hpi_set_address(pdo, address))
1177 return 0; /*? No way to return error */
1178
1179 /* take care of errata in revB DSP (2.0.1) */
1180 data = ioread32(pdo->prHPI_data);
1181 return data;
1182 }
1183
1184 /* write a block of 32bit words to the DSP HPI port using auto-inc mode */
1185 static void hpi_write_block(struct dsp_obj *pdo, u32 address, u32 *pdata,
1186 u32 length)
1187 {
1188 u16 length16 = length - 1;
1189
1190 if (length == 0)
1191 return;
1192
1193 if (hpi_set_address(pdo, address))
1194 return;
1195
1196 iowrite32_rep(pdo->prHPI_data_auto_inc, pdata, length16);
1197
1198 /* take care of errata in revB DSP (2.0.1) */
1199 /* must end with non auto-inc */
1200 iowrite32(*(pdata + length - 1), pdo->prHPI_data);
1201 }
1202
1203 /** read a block of 32bit words from the DSP HPI port using auto-inc mode
1204 */
1205 static void hpi_read_block(struct dsp_obj *pdo, u32 address, u32 *pdata,
1206 u32 length)
1207 {
1208 u16 length16 = length - 1;
1209
1210 if (length == 0)
1211 return;
1212
1213 if (hpi_set_address(pdo, address))
1214 return;
1215
1216 ioread32_rep(pdo->prHPI_data_auto_inc, pdata, length16);
1217
1218 /* take care of errata in revB DSP (2.0.1) */
1219 /* must end with non auto-inc */
1220 *(pdata + length - 1) = ioread32(pdo->prHPI_data);
1221 }
1222
1223 static u16 hpi6000_dsp_block_write32(struct hpi_adapter_obj *pao,
1224 u16 dsp_index, u32 hpi_address, u32 *source, u32 count)
1225 {
1226 struct dsp_obj *pdo =
1227 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
1228 u32 time_out = PCI_TIMEOUT;
1229 int c6711_burst_size = 128;
1230 u32 local_hpi_address = hpi_address;
1231 int local_count = count;
1232 int xfer_size;
1233 u32 *pdata = source;
1234
1235 while (local_count) {
1236 if (local_count > c6711_burst_size)
1237 xfer_size = c6711_burst_size;
1238 else
1239 xfer_size = local_count;
1240
1241 time_out = PCI_TIMEOUT;
1242 do {
1243 hpi_write_block(pdo, local_hpi_address, pdata,
1244 xfer_size);
1245 } while (hpi6000_check_PCI2040_error_flag(pao, H6WRITE)
1246 && --time_out);
1247
1248 if (!time_out)
1249 break;
1250 pdata += xfer_size;
1251 local_hpi_address += sizeof(u32) * xfer_size;
1252 local_count -= xfer_size;
1253 }
1254
1255 if (time_out)
1256 return 0;
1257 else
1258 return 1;
1259 }
1260
1261 static u16 hpi6000_dsp_block_read32(struct hpi_adapter_obj *pao,
1262 u16 dsp_index, u32 hpi_address, u32 *dest, u32 count)
1263 {
1264 struct dsp_obj *pdo =
1265 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
1266 u32 time_out = PCI_TIMEOUT;
1267 int c6711_burst_size = 16;
1268 u32 local_hpi_address = hpi_address;
1269 int local_count = count;
1270 int xfer_size;
1271 u32 *pdata = dest;
1272 u32 loop_count = 0;
1273
1274 while (local_count) {
1275 if (local_count > c6711_burst_size)
1276 xfer_size = c6711_burst_size;
1277 else
1278 xfer_size = local_count;
1279
1280 time_out = PCI_TIMEOUT;
1281 do {
1282 hpi_read_block(pdo, local_hpi_address, pdata,
1283 xfer_size);
1284 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)
1285 && --time_out);
1286 if (!time_out)
1287 break;
1288
1289 pdata += xfer_size;
1290 local_hpi_address += sizeof(u32) * xfer_size;
1291 local_count -= xfer_size;
1292 loop_count++;
1293 }
1294
1295 if (time_out)
1296 return 0;
1297 else
1298 return 1;
1299 }
1300
1301 static short hpi6000_message_response_sequence(struct hpi_adapter_obj *pao,
1302 u16 dsp_index, struct hpi_message *phm, struct hpi_response *phr)
1303 {
1304 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
1305 struct dsp_obj *pdo = &phw->ado[dsp_index];
1306 u32 timeout;
1307 u16 ack;
1308 u32 address;
1309 u32 length;
1310 u32 *p_data;
1311 u16 error = 0;
1312
1313 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_IDLE);
1314 if (ack & HPI_HIF_ERROR_MASK) {
1315 pao->dsp_crashed++;
1316 return HPI6000_ERROR_MSG_RESP_IDLE_TIMEOUT;
1317 }
1318 pao->dsp_crashed = 0;
1319
1320 /* get the message address and size */
1321 if (phw->message_buffer_address_on_dsp == 0) {
1322 timeout = TIMEOUT;
1323 do {
1324 address =
1325 hpi_read_word(pdo,
1326 HPI_HIF_ADDR(message_buffer_address));
1327 phw->message_buffer_address_on_dsp = address;
1328 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)
1329 && --timeout);
1330 if (!timeout)
1331 return HPI6000_ERROR_MSG_GET_ADR;
1332 } else
1333 address = phw->message_buffer_address_on_dsp;
1334
1335 length = phm->size;
1336
1337 /* send the message */
1338 p_data = (u32 *)phm;
1339 if (hpi6000_dsp_block_write32(pao, dsp_index, address, p_data,
1340 (u16)length / 4))
1341 return HPI6000_ERROR_MSG_RESP_BLOCKWRITE32;
1342
1343 if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_GET_RESP))
1344 return HPI6000_ERROR_MSG_RESP_GETRESPCMD;
1345 hpi6000_send_dsp_interrupt(pdo);
1346
1347 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_GET_RESP);
1348 if (ack & HPI_HIF_ERROR_MASK)
1349 return HPI6000_ERROR_MSG_RESP_GET_RESP_ACK;
1350
1351 /* get the response address */
1352 if (phw->response_buffer_address_on_dsp == 0) {
1353 timeout = TIMEOUT;
1354 do {
1355 address =
1356 hpi_read_word(pdo,
1357 HPI_HIF_ADDR(response_buffer_address));
1358 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)
1359 && --timeout);
1360 phw->response_buffer_address_on_dsp = address;
1361
1362 if (!timeout)
1363 return HPI6000_ERROR_RESP_GET_ADR;
1364 } else
1365 address = phw->response_buffer_address_on_dsp;
1366
1367 /* read the length of the response back from the DSP */
1368 timeout = TIMEOUT;
1369 do {
1370 length = hpi_read_word(pdo, HPI_HIF_ADDR(length));
1371 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) && --timeout);
1372 if (!timeout)
1373 length = sizeof(struct hpi_response);
1374
1375 /* get the response */
1376 p_data = (u32 *)phr;
1377 if (hpi6000_dsp_block_read32(pao, dsp_index, address, p_data,
1378 (u16)length / 4))
1379 return HPI6000_ERROR_MSG_RESP_BLOCKREAD32;
1380
1381 /* set i/f back to idle */
1382 if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_IDLE))
1383 return HPI6000_ERROR_MSG_RESP_IDLECMD;
1384 hpi6000_send_dsp_interrupt(pdo);
1385
1386 error = hpi_validate_response(phm, phr);
1387 return error;
1388 }
1389
1390 /* have to set up the below defines to match stuff in the MAP file */
1391
1392 #define MSG_ADDRESS (HPI_HIF_BASE+0x18)
1393 #define MSG_LENGTH 11
1394 #define RESP_ADDRESS (HPI_HIF_BASE+0x44)
1395 #define RESP_LENGTH 16
1396 #define QUEUE_START (HPI_HIF_BASE+0x88)
1397 #define QUEUE_SIZE 0x8000
1398
1399 static short hpi6000_send_data_check_adr(u32 address, u32 length_in_dwords)
1400 {
1401 /*#define CHECKING // comment this line in to enable checking */
1402 #ifdef CHECKING
1403 if (address < (u32)MSG_ADDRESS)
1404 return 0;
1405 if (address > (u32)(QUEUE_START + QUEUE_SIZE))
1406 return 0;
1407 if ((address + (length_in_dwords << 2)) >
1408 (u32)(QUEUE_START + QUEUE_SIZE))
1409 return 0;
1410 #else
1411 (void)address;
1412 (void)length_in_dwords;
1413 return 1;
1414 #endif
1415 }
1416
1417 static short hpi6000_send_data(struct hpi_adapter_obj *pao, u16 dsp_index,
1418 struct hpi_message *phm, struct hpi_response *phr)
1419 {
1420 struct dsp_obj *pdo =
1421 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
1422 u32 data_sent = 0;
1423 u16 ack;
1424 u32 length, address;
1425 u32 *p_data = (u32 *)phm->u.d.u.data.pb_data;
1426 u16 time_out = 8;
1427
1428 (void)phr;
1429
1430 /* round dwDataSize down to nearest 4 bytes */
1431 while ((data_sent < (phm->u.d.u.data.data_size & ~3L))
1432 && --time_out) {
1433 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_IDLE);
1434 if (ack & HPI_HIF_ERROR_MASK)
1435 return HPI6000_ERROR_SEND_DATA_IDLE_TIMEOUT;
1436
1437 if (hpi6000_send_host_command(pao, dsp_index,
1438 HPI_HIF_SEND_DATA))
1439 return HPI6000_ERROR_SEND_DATA_CMD;
1440
1441 hpi6000_send_dsp_interrupt(pdo);
1442
1443 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_SEND_DATA);
1444
1445 if (ack & HPI_HIF_ERROR_MASK)
1446 return HPI6000_ERROR_SEND_DATA_ACK;
1447
1448 do {
1449 /* get the address and size */
1450 address = hpi_read_word(pdo, HPI_HIF_ADDR(address));
1451 /* DSP returns number of DWORDS */
1452 length = hpi_read_word(pdo, HPI_HIF_ADDR(length));
1453 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ));
1454
1455 if (!hpi6000_send_data_check_adr(address, length))
1456 return HPI6000_ERROR_SEND_DATA_ADR;
1457
1458 /* send the data. break data into 512 DWORD blocks (2K bytes)
1459 * and send using block write. 2Kbytes is the max as this is the
1460 * memory window given to the HPI data register by the PCI2040
1461 */
1462
1463 {
1464 u32 len = length;
1465 u32 blk_len = 512;
1466 while (len) {
1467 if (len < blk_len)
1468 blk_len = len;
1469 if (hpi6000_dsp_block_write32(pao, dsp_index,
1470 address, p_data, blk_len))
1471 return HPI6000_ERROR_SEND_DATA_WRITE;
1472 address += blk_len * 4;
1473 p_data += blk_len;
1474 len -= blk_len;
1475 }
1476 }
1477
1478 if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_IDLE))
1479 return HPI6000_ERROR_SEND_DATA_IDLECMD;
1480
1481 hpi6000_send_dsp_interrupt(pdo);
1482
1483 data_sent += length * 4;
1484 }
1485 if (!time_out)
1486 return HPI6000_ERROR_SEND_DATA_TIMEOUT;
1487 return 0;
1488 }
1489
1490 static short hpi6000_get_data(struct hpi_adapter_obj *pao, u16 dsp_index,
1491 struct hpi_message *phm, struct hpi_response *phr)
1492 {
1493 struct dsp_obj *pdo =
1494 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
1495 u32 data_got = 0;
1496 u16 ack;
1497 u32 length, address;
1498 u32 *p_data = (u32 *)phm->u.d.u.data.pb_data;
1499
1500 (void)phr; /* this parameter not used! */
1501
1502 /* round dwDataSize down to nearest 4 bytes */
1503 while (data_got < (phm->u.d.u.data.data_size & ~3L)) {
1504 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_IDLE);
1505 if (ack & HPI_HIF_ERROR_MASK)
1506 return HPI6000_ERROR_GET_DATA_IDLE_TIMEOUT;
1507
1508 if (hpi6000_send_host_command(pao, dsp_index,
1509 HPI_HIF_GET_DATA))
1510 return HPI6000_ERROR_GET_DATA_CMD;
1511 hpi6000_send_dsp_interrupt(pdo);
1512
1513 ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_GET_DATA);
1514
1515 if (ack & HPI_HIF_ERROR_MASK)
1516 return HPI6000_ERROR_GET_DATA_ACK;
1517
1518 /* get the address and size */
1519 do {
1520 address = hpi_read_word(pdo, HPI_HIF_ADDR(address));
1521 length = hpi_read_word(pdo, HPI_HIF_ADDR(length));
1522 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ));
1523
1524 /* read the data */
1525 {
1526 u32 len = length;
1527 u32 blk_len = 512;
1528 while (len) {
1529 if (len < blk_len)
1530 blk_len = len;
1531 if (hpi6000_dsp_block_read32(pao, dsp_index,
1532 address, p_data, blk_len))
1533 return HPI6000_ERROR_GET_DATA_READ;
1534 address += blk_len * 4;
1535 p_data += blk_len;
1536 len -= blk_len;
1537 }
1538 }
1539
1540 if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_IDLE))
1541 return HPI6000_ERROR_GET_DATA_IDLECMD;
1542 hpi6000_send_dsp_interrupt(pdo);
1543
1544 data_got += length * 4;
1545 }
1546 return 0;
1547 }
1548
1549 static void hpi6000_send_dsp_interrupt(struct dsp_obj *pdo)
1550 {
1551 iowrite32(0x00030003, pdo->prHPI_control); /* DSPINT */
1552 }
1553
1554 static short hpi6000_send_host_command(struct hpi_adapter_obj *pao,
1555 u16 dsp_index, u32 host_cmd)
1556 {
1557 struct dsp_obj *pdo =
1558 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
1559 u32 timeout = TIMEOUT;
1560
1561 /* set command */
1562 do {
1563 hpi_write_word(pdo, HPI_HIF_ADDR(host_cmd), host_cmd);
1564 /* flush the FIFO */
1565 hpi_set_address(pdo, HPI_HIF_ADDR(host_cmd));
1566 } while (hpi6000_check_PCI2040_error_flag(pao, H6WRITE) && --timeout);
1567
1568 /* reset the interrupt bit */
1569 iowrite32(0x00040004, pdo->prHPI_control);
1570
1571 if (timeout)
1572 return 0;
1573 else
1574 return 1;
1575 }
1576
1577 /* if the PCI2040 has recorded an HPI timeout, reset the error and return 1 */
1578 static short hpi6000_check_PCI2040_error_flag(struct hpi_adapter_obj *pao,
1579 u16 read_or_write)
1580 {
1581 u32 hPI_error;
1582
1583 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
1584
1585 /* read the error bits from the PCI2040 */
1586 hPI_error = ioread32(phw->dw2040_HPICSR + HPI_ERROR_REPORT);
1587 if (hPI_error) {
1588 /* reset the error flag */
1589 iowrite32(0L, phw->dw2040_HPICSR + HPI_ERROR_REPORT);
1590 phw->pCI2040HPI_error_count++;
1591 if (read_or_write == 1)
1592 gw_pci_read_asserts++; /************* inc global */
1593 else
1594 gw_pci_write_asserts++;
1595 return 1;
1596 } else
1597 return 0;
1598 }
1599
1600 static short hpi6000_wait_dsp_ack(struct hpi_adapter_obj *pao, u16 dsp_index,
1601 u32 ack_value)
1602 {
1603 struct dsp_obj *pdo =
1604 &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
1605 u32 ack = 0L;
1606 u32 timeout;
1607 u32 hPIC = 0L;
1608
1609 /* wait for host interrupt to signal ack is ready */
1610 timeout = TIMEOUT;
1611 while (--timeout) {
1612 hPIC = ioread32(pdo->prHPI_control);
1613 if (hPIC & 0x04) /* 0x04 = HINT from DSP */
1614 break;
1615 }
1616 if (timeout == 0)
1617 return HPI_HIF_ERROR_MASK;
1618
1619 /* wait for dwAckValue */
1620 timeout = TIMEOUT;
1621 while (--timeout) {
1622 /* read the ack mailbox */
1623 ack = hpi_read_word(pdo, HPI_HIF_ADDR(dsp_ack));
1624 if (ack == ack_value)
1625 break;
1626 if ((ack & HPI_HIF_ERROR_MASK)
1627 && !hpi6000_check_PCI2040_error_flag(pao, H6READ))
1628 break;
1629 /*for (i=0;i<1000;i++) */
1630 /* dwPause=i+1; */
1631 }
1632 if (ack & HPI_HIF_ERROR_MASK)
1633 /* indicates bad read from DSP -
1634 typically 0xffffff is read for some reason */
1635 ack = HPI_HIF_ERROR_MASK;
1636
1637 if (timeout == 0)
1638 ack = HPI_HIF_ERROR_MASK;
1639 return (short)ack;
1640 }
1641
1642 static short hpi6000_update_control_cache(struct hpi_adapter_obj *pao,
1643 struct hpi_message *phm)
1644 {
1645 const u16 dsp_index = 0;
1646 struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
1647 struct dsp_obj *pdo = &phw->ado[dsp_index];
1648 u32 timeout;
1649 u32 cache_dirty_flag;
1650 u16 err;
1651
1652 hpios_dsplock_lock(pao);
1653
1654 timeout = TIMEOUT;
1655 do {
1656 cache_dirty_flag =
1657 hpi_read_word((struct dsp_obj *)pdo,
1658 HPI_HIF_ADDR(control_cache_is_dirty));
1659 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) && --timeout);
1660 if (!timeout) {
1661 err = HPI6000_ERROR_CONTROL_CACHE_PARAMS;
1662 goto unlock;
1663 }
1664
1665 if (cache_dirty_flag) {
1666 /* read the cached controls */
1667 u32 address;
1668 u32 length;
1669
1670 timeout = TIMEOUT;
1671 if (pdo->control_cache_address_on_dsp == 0) {
1672 do {
1673 address =
1674 hpi_read_word((struct dsp_obj *)pdo,
1675 HPI_HIF_ADDR(control_cache_address));
1676
1677 length = hpi_read_word((struct dsp_obj *)pdo,
1678 HPI_HIF_ADDR
1679 (control_cache_size_in_bytes));
1680 } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)
1681 && --timeout);
1682 if (!timeout) {
1683 err = HPI6000_ERROR_CONTROL_CACHE_ADDRLEN;
1684 goto unlock;
1685 }
1686 pdo->control_cache_address_on_dsp = address;
1687 pdo->control_cache_length_on_dsp = length;
1688 } else {
1689 address = pdo->control_cache_address_on_dsp;
1690 length = pdo->control_cache_length_on_dsp;
1691 }
1692
1693 if (hpi6000_dsp_block_read32(pao, dsp_index, address,
1694 (u32 *)&phw->control_cache[0],
1695 length / sizeof(u32))) {
1696 err = HPI6000_ERROR_CONTROL_CACHE_READ;
1697 goto unlock;
1698 }
1699 do {
1700 hpi_write_word((struct dsp_obj *)pdo,
1701 HPI_HIF_ADDR(control_cache_is_dirty), 0);
1702 /* flush the FIFO */
1703 hpi_set_address(pdo, HPI_HIF_ADDR(host_cmd));
1704 } while (hpi6000_check_PCI2040_error_flag(pao, H6WRITE)
1705 && --timeout);
1706 if (!timeout) {
1707 err = HPI6000_ERROR_CONTROL_CACHE_FLUSH;
1708 goto unlock;
1709 }
1710
1711 }
1712 err = 0;
1713
1714 unlock:
1715 hpios_dsplock_unlock(pao);
1716 return err;
1717 }
1718
1719 /** Get dsp index for multi DSP adapters only */
1720 static u16 get_dsp_index(struct hpi_adapter_obj *pao, struct hpi_message *phm)
1721 {
1722 u16 ret = 0;
1723 switch (phm->object) {
1724 case HPI_OBJ_ISTREAM:
1725 if (phm->obj_index < 2)
1726 ret = 1;
1727 break;
1728 case HPI_OBJ_PROFILE:
1729 ret = phm->obj_index;
1730 break;
1731 default:
1732 break;
1733 }
1734 return ret;
1735 }
1736
1737 /** Complete transaction with DSP
1738
1739 Send message, get response, send or get stream data if any.
1740 */
1741 static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm,
1742 struct hpi_response *phr)
1743 {
1744 u16 error = 0;
1745 u16 dsp_index = 0;
1746 u16 num_dsp = ((struct hpi_hw_obj *)pao->priv)->num_dsp;
1747
1748 if (num_dsp < 2)
1749 dsp_index = 0;
1750 else {
1751 dsp_index = get_dsp_index(pao, phm);
1752
1753 /* is this checked on the DSP anyway? */
1754 if ((phm->function == HPI_ISTREAM_GROUP_ADD)
1755 || (phm->function == HPI_OSTREAM_GROUP_ADD)) {
1756 struct hpi_message hm;
1757 u16 add_index;
1758 hm.obj_index = phm->u.d.u.stream.stream_index;
1759 hm.object = phm->u.d.u.stream.object_type;
1760 add_index = get_dsp_index(pao, &hm);
1761 if (add_index != dsp_index) {
1762 phr->error = HPI_ERROR_NO_INTERDSP_GROUPS;
1763 return;
1764 }
1765 }
1766 }
1767
1768 hpios_dsplock_lock(pao);
1769 error = hpi6000_message_response_sequence(pao, dsp_index, phm, phr);
1770
1771 if (error) /* something failed in the HPI/DSP interface */
1772 goto err;
1773
1774 if (phr->error) /* something failed in the DSP */
1775 goto out;
1776
1777 switch (phm->function) {
1778 case HPI_OSTREAM_WRITE:
1779 case HPI_ISTREAM_ANC_WRITE:
1780 error = hpi6000_send_data(pao, dsp_index, phm, phr);
1781 break;
1782 case HPI_ISTREAM_READ:
1783 case HPI_OSTREAM_ANC_READ:
1784 error = hpi6000_get_data(pao, dsp_index, phm, phr);
1785 break;
1786 case HPI_ADAPTER_GET_ASSERT:
1787 phr->u.ax.assert.dsp_index = 0; /* dsp 0 default */
1788 if (num_dsp == 2) {
1789 if (!phr->u.ax.assert.count) {
1790 /* no assert from dsp 0, check dsp 1 */
1791 error = hpi6000_message_response_sequence(pao,
1792 1, phm, phr);
1793 phr->u.ax.assert.dsp_index = 1;
1794 }
1795 }
1796 }
1797
1798 err:
1799 if (error) {
1800 if (error >= HPI_ERROR_BACKEND_BASE) {
1801 phr->error = HPI_ERROR_DSP_COMMUNICATION;
1802 phr->specific_error = error;
1803 } else {
1804 phr->error = error;
1805 }
1806
1807 /* just the header of the response is valid */
1808 phr->size = sizeof(struct hpi_response_header);
1809 }
1810 out:
1811 hpios_dsplock_unlock(pao);
1812 return;
1813 }
linux-next