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[linux-2.6/next.git] / arch / cris / arch-v10 / kernel / time.c
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1 /* $Id: time.c,v 1.5 2004/09/29 06:12:46 starvik Exp $
3 * linux/arch/cris/arch-v10/kernel/time.c
5 * Copyright (C) 1991, 1992, 1995 Linus Torvalds
6 * Copyright (C) 1999-2002 Axis Communications AB
8 */
10 #include <linux/config.h>
11 #include <linux/timex.h>
12 #include <linux/time.h>
13 #include <linux/jiffies.h>
14 #include <linux/interrupt.h>
15 #include <linux/swap.h>
16 #include <linux/sched.h>
17 #include <linux/init.h>
18 #include <asm/arch/svinto.h>
19 #include <asm/types.h>
20 #include <asm/signal.h>
21 #include <asm/io.h>
22 #include <asm/delay.h>
23 #include <asm/rtc.h>
25 /* define this if you need to use print_timestamp */
26 /* it will make jiffies at 96 hz instead of 100 hz though */
27 #undef USE_CASCADE_TIMERS
29 extern void update_xtime_from_cmos(void);
30 extern int set_rtc_mmss(unsigned long nowtime);
31 extern int setup_irq(int, struct irqaction *);
32 extern int have_rtc;
34 unsigned long get_ns_in_jiffie(void)
36 unsigned char timer_count, t1;
37 unsigned short presc_count;
38 unsigned long ns;
39 unsigned long flags;
41 local_irq_save(flags);
42 local_irq_disable();
43 timer_count = *R_TIMER0_DATA;
44 presc_count = *R_TIM_PRESC_STATUS;
45 /* presc_count might be wrapped */
46 t1 = *R_TIMER0_DATA;
48 if (timer_count != t1){
49 /* it wrapped, read prescaler again... */
50 presc_count = *R_TIM_PRESC_STATUS;
51 timer_count = t1;
53 local_irq_restore(flags);
54 if (presc_count >= PRESCALE_VALUE/2 ){
55 presc_count = PRESCALE_VALUE - presc_count + PRESCALE_VALUE/2;
56 } else {
57 presc_count = PRESCALE_VALUE - presc_count - PRESCALE_VALUE/2;
60 ns = ( (TIMER0_DIV - timer_count) * ((1000000000/HZ)/TIMER0_DIV )) +
61 ( (presc_count) * (1000000000/PRESCALE_FREQ));
62 return ns;
65 unsigned long do_slow_gettimeoffset(void)
67 unsigned long count, t1;
68 unsigned long usec_count = 0;
69 unsigned short presc_count;
71 static unsigned long count_p = TIMER0_DIV;/* for the first call after boot */
72 static unsigned long jiffies_p = 0;
75 * cache volatile jiffies temporarily; we have IRQs turned off.
77 unsigned long jiffies_t;
79 /* The timer interrupt comes from Etrax timer 0. In order to get
80 * better precision, we check the current value. It might have
81 * underflowed already though.
84 #ifndef CONFIG_SVINTO_SIM
85 /* Not available in the xsim simulator. */
86 count = *R_TIMER0_DATA;
87 presc_count = *R_TIM_PRESC_STATUS;
88 /* presc_count might be wrapped */
89 t1 = *R_TIMER0_DATA;
90 if (count != t1){
91 /* it wrapped, read prescaler again... */
92 presc_count = *R_TIM_PRESC_STATUS;
93 count = t1;
95 #else
96 count = 0;
97 presc_count = 0;
98 #endif
100 jiffies_t = jiffies;
103 * avoiding timer inconsistencies (they are rare, but they happen)...
104 * there are one problem that must be avoided here:
105 * 1. the timer counter underflows
107 if( jiffies_t == jiffies_p ) {
108 if( count > count_p ) {
109 /* Timer wrapped, use new count and prescale
110 * increase the time corresponding to one jiffie
112 usec_count = 1000000/HZ;
114 } else
115 jiffies_p = jiffies_t;
116 count_p = count;
117 if (presc_count >= PRESCALE_VALUE/2 ){
118 presc_count = PRESCALE_VALUE - presc_count + PRESCALE_VALUE/2;
119 } else {
120 presc_count = PRESCALE_VALUE - presc_count - PRESCALE_VALUE/2;
122 /* Convert timer value to usec */
123 usec_count += ( (TIMER0_DIV - count) * (1000000/HZ)/TIMER0_DIV ) +
124 (( (presc_count) * (1000000000/PRESCALE_FREQ))/1000);
126 return usec_count;
129 /* Excerpt from the Etrax100 HSDD about the built-in watchdog:
131 * 3.10.4 Watchdog timer
133 * When the watchdog timer is started, it generates an NMI if the watchdog
134 * isn't restarted or stopped within 0.1 s. If it still isn't restarted or
135 * stopped after an additional 3.3 ms, the watchdog resets the chip.
136 * The watchdog timer is stopped after reset. The watchdog timer is controlled
137 * by the R_WATCHDOG register. The R_WATCHDOG register contains an enable bit
138 * and a 3-bit key value. The effect of writing to the R_WATCHDOG register is
139 * described in the table below:
141 * Watchdog Value written:
142 * state: To enable: To key: Operation:
143 * -------- ---------- ------- ----------
144 * stopped 0 X No effect.
145 * stopped 1 key_val Start watchdog with key = key_val.
146 * started 0 ~key Stop watchdog
147 * started 1 ~key Restart watchdog with key = ~key.
148 * started X new_key_val Change key to new_key_val.
150 * Note: '~' is the bitwise NOT operator.
154 /* right now, starting the watchdog is the same as resetting it */
155 #define start_watchdog reset_watchdog
157 #if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
158 static int watchdog_key = 0; /* arbitrary number */
159 #endif
161 /* number of pages to consider "out of memory". it is normal that the memory
162 * is used though, so put this really low.
165 #define WATCHDOG_MIN_FREE_PAGES 8
167 void
168 reset_watchdog(void)
170 #if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
171 /* only keep watchdog happy as long as we have memory left! */
172 if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) {
173 /* reset the watchdog with the inverse of the old key */
174 watchdog_key ^= 0x7; /* invert key, which is 3 bits */
175 *R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) |
176 IO_STATE(R_WATCHDOG, enable, start);
178 #endif
181 /* stop the watchdog - we still need the correct key */
183 void
184 stop_watchdog(void)
186 #if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
187 watchdog_key ^= 0x7; /* invert key, which is 3 bits */
188 *R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) |
189 IO_STATE(R_WATCHDOG, enable, stop);
190 #endif
193 /* last time the cmos clock got updated */
194 static long last_rtc_update = 0;
197 * timer_interrupt() needs to keep up the real-time clock,
198 * as well as call the "do_timer()" routine every clocktick
201 //static unsigned short myjiff; /* used by our debug routine print_timestamp */
203 extern void cris_do_profile(struct pt_regs *regs);
205 static inline irqreturn_t
206 timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
208 /* acknowledge the timer irq */
210 #ifdef USE_CASCADE_TIMERS
211 *R_TIMER_CTRL =
212 IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
213 IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
214 IO_STATE( R_TIMER_CTRL, i1, clr) |
215 IO_STATE( R_TIMER_CTRL, tm1, run) |
216 IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
217 IO_STATE( R_TIMER_CTRL, i0, clr) |
218 IO_STATE( R_TIMER_CTRL, tm0, run) |
219 IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
220 #else
221 *R_TIMER_CTRL = r_timer_ctrl_shadow |
222 IO_STATE(R_TIMER_CTRL, i0, clr);
223 #endif
225 /* reset watchdog otherwise it resets us! */
227 reset_watchdog();
229 /* call the real timer interrupt handler */
231 do_timer(regs);
233 cris_do_profile(regs); /* Save profiling information */
236 * If we have an externally synchronized Linux clock, then update
237 * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
238 * called as close as possible to 500 ms before the new second starts.
240 * The division here is not time critical since it will run once in
241 * 11 minutes
243 if ((time_status & STA_UNSYNC) == 0 &&
244 xtime.tv_sec > last_rtc_update + 660 &&
245 (xtime.tv_nsec / 1000) >= 500000 - (tick_nsec / 1000) / 2 &&
246 (xtime.tv_nsec / 1000) <= 500000 + (tick_nsec / 1000) / 2) {
247 if (set_rtc_mmss(xtime.tv_sec) == 0)
248 last_rtc_update = xtime.tv_sec;
249 else
250 last_rtc_update = xtime.tv_sec - 600; /* do it again in 60 s */
252 return IRQ_HANDLED;
255 /* timer is SA_SHIRQ so drivers can add stuff to the timer irq chain
256 * it needs to be SA_INTERRUPT to make the jiffies update work properly
259 static struct irqaction irq2 = { timer_interrupt, SA_SHIRQ | SA_INTERRUPT,
260 CPU_MASK_NONE, "timer", NULL, NULL};
262 void __init
263 time_init(void)
265 /* probe for the RTC and read it if it exists
266 * Before the RTC can be probed the loops_per_usec variable needs
267 * to be initialized to make usleep work. A better value for
268 * loops_per_usec is calculated by the kernel later once the
269 * clock has started.
271 loops_per_usec = 50;
273 if(RTC_INIT() < 0) {
274 /* no RTC, start at 1980 */
275 xtime.tv_sec = 0;
276 xtime.tv_nsec = 0;
277 have_rtc = 0;
278 } else {
279 /* get the current time */
280 have_rtc = 1;
281 update_xtime_from_cmos();
285 * Initialize wall_to_monotonic such that adding it to xtime will yield zero, the
286 * tv_nsec field must be normalized (i.e., 0 <= nsec < NSEC_PER_SEC).
288 set_normalized_timespec(&wall_to_monotonic, -xtime.tv_sec, -xtime.tv_nsec);
290 /* Setup the etrax timers
291 * Base frequency is 25000 hz, divider 250 -> 100 HZ
292 * In normal mode, we use timer0, so timer1 is free. In cascade
293 * mode (which we sometimes use for debugging) both timers are used.
294 * Remember that linux/timex.h contains #defines that rely on the
295 * timer settings below (hz and divide factor) !!!
298 #ifdef USE_CASCADE_TIMERS
299 *R_TIMER_CTRL =
300 IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
301 IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
302 IO_STATE( R_TIMER_CTRL, i1, nop) |
303 IO_STATE( R_TIMER_CTRL, tm1, stop_ld) |
304 IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
305 IO_STATE( R_TIMER_CTRL, i0, nop) |
306 IO_STATE( R_TIMER_CTRL, tm0, stop_ld) |
307 IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
309 *R_TIMER_CTRL = r_timer_ctrl_shadow =
310 IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
311 IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
312 IO_STATE( R_TIMER_CTRL, i1, nop) |
313 IO_STATE( R_TIMER_CTRL, tm1, run) |
314 IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
315 IO_STATE( R_TIMER_CTRL, i0, nop) |
316 IO_STATE( R_TIMER_CTRL, tm0, run) |
317 IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
318 #else
319 *R_TIMER_CTRL =
320 IO_FIELD(R_TIMER_CTRL, timerdiv1, 192) |
321 IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV) |
322 IO_STATE(R_TIMER_CTRL, i1, nop) |
323 IO_STATE(R_TIMER_CTRL, tm1, stop_ld) |
324 IO_STATE(R_TIMER_CTRL, clksel1, c19k2Hz) |
325 IO_STATE(R_TIMER_CTRL, i0, nop) |
326 IO_STATE(R_TIMER_CTRL, tm0, stop_ld) |
327 IO_STATE(R_TIMER_CTRL, clksel0, flexible);
329 *R_TIMER_CTRL = r_timer_ctrl_shadow =
330 IO_FIELD(R_TIMER_CTRL, timerdiv1, 192) |
331 IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV) |
332 IO_STATE(R_TIMER_CTRL, i1, nop) |
333 IO_STATE(R_TIMER_CTRL, tm1, run) |
334 IO_STATE(R_TIMER_CTRL, clksel1, c19k2Hz) |
335 IO_STATE(R_TIMER_CTRL, i0, nop) |
336 IO_STATE(R_TIMER_CTRL, tm0, run) |
337 IO_STATE(R_TIMER_CTRL, clksel0, flexible);
339 *R_TIMER_PRESCALE = PRESCALE_VALUE;
340 #endif
342 *R_IRQ_MASK0_SET =
343 IO_STATE(R_IRQ_MASK0_SET, timer0, set); /* unmask the timer irq */
345 /* now actually register the timer irq handler that calls timer_interrupt() */
347 setup_irq(2, &irq2); /* irq 2 is the timer0 irq in etrax */
349 /* enable watchdog if we should use one */
351 #if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
352 printk("Enabling watchdog...\n");
353 start_watchdog();
355 /* If we use the hardware watchdog, we want to trap it as an NMI
356 and dump registers before it resets us. For this to happen, we
357 must set the "m" NMI enable flag (which once set, is unset only
358 when an NMI is taken).
360 The same goes for the external NMI, but that doesn't have any
361 driver or infrastructure support yet. */
362 asm ("setf m");
364 *R_IRQ_MASK0_SET =
365 IO_STATE(R_IRQ_MASK0_SET, watchdog_nmi, set);
366 *R_VECT_MASK_SET =
367 IO_STATE(R_VECT_MASK_SET, nmi, set);
368 #endif