drivers/scsi/hpsa.h

   1 /*
   2  *    Disk Array driver for HP Smart Array SAS controllers
   3  *    Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
   4  *
   5  *    This program is free software; you can redistribute it and/or modify
   6  *    it under the terms of the GNU General Public License as published by
   7  *    the Free Software Foundation; version 2 of the License.
   8  *
   9  *    This program is distributed in the hope that it will be useful,
  10  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *    MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  12  *    NON INFRINGEMENT.  See the GNU General Public License for more details.
  13  *
  14  *    You should have received a copy of the GNU General Public License
  15  *    along with this program; if not, write to the Free Software
  16  *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17  *
  18  *    Questions/Comments/Bugfixes to iss_storagedev@hp.com
  19  *
  20  */
  21 #ifndef HPSA_H
  22 #define HPSA_H
  23
  24 #include <scsi/scsicam.h>
  25
  26 #define IO_OK           0
  27 #define IO_ERROR        1
  28
  29 struct ctlr_info;
  30
  31 struct access_method {
  32         void (*submit_command)(struct ctlr_info *h,
  33                 struct CommandList *c);
  34         void (*set_intr_mask)(struct ctlr_info *h, unsigned long val);
  35         unsigned long (*fifo_full)(struct ctlr_info *h);
  36         unsigned long (*intr_pending)(struct ctlr_info *h);
  37         unsigned long (*command_completed)(struct ctlr_info *h);
  38 };
  39
  40 struct hpsa_scsi_dev_t {
  41         int devtype;
  42         int bus, target, lun;           /* as presented to the OS */
  43         unsigned char scsi3addr[8];     /* as presented to the HW */
  44 #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
  45         unsigned char device_id[16];    /* from inquiry pg. 0x83 */
  46         unsigned char vendor[8];        /* bytes 8-15 of inquiry data */
  47         unsigned char model[16];        /* bytes 16-31 of inquiry data */
  48         unsigned char revision[4];      /* bytes 32-35 of inquiry data */
  49         unsigned char raid_level;       /* from inquiry page 0xC1 */
  50 };
  51
  52 struct ctlr_info {
  53         int     ctlr;
  54         char    devname[8];
  55         char    *product_name;
  56         char    firm_ver[4]; /* Firmware version */
  57         struct pci_dev *pdev;
  58         u32     board_id;
  59         void __iomem *vaddr;
  60         unsigned long paddr;
  61         int     nr_cmds; /* Number of commands allowed on this controller */
  62         struct CfgTable __iomem *cfgtable;
  63         int     interrupts_enabled;
  64         int     major;
  65         int     max_commands;
  66         int     commands_outstanding;
  67         int     max_outstanding; /* Debug */
  68         int     usage_count;  /* number of opens all all minor devices */
  69 #       define DOORBELL_INT     0
  70 #       define PERF_MODE_INT    1
  71 #       define SIMPLE_MODE_INT  2
  72 #       define MEMQ_MODE_INT    3
  73         unsigned int intr[4];
  74         unsigned int msix_vector;
  75         unsigned int msi_vector;
  76         struct access_method access;
  77
  78         /* queue and queue Info */
  79         struct hlist_head reqQ;
  80         struct hlist_head cmpQ;
  81         unsigned int Qdepth;
  82         unsigned int maxQsinceinit;
  83         unsigned int maxSG;
  84         spinlock_t lock;
  85
  86         /* pointers to command and error info pool */
  87         struct CommandList      *cmd_pool;
  88         dma_addr_t              cmd_pool_dhandle;
  89         struct ErrorInfo        *errinfo_pool;
  90         dma_addr_t              errinfo_pool_dhandle;
  91         unsigned long           *cmd_pool_bits;
  92         int                     nr_allocs;
  93         int                     nr_frees;
  94         int                     busy_initializing;
  95         int                     busy_scanning;
  96         struct mutex            busy_shutting_down;
  97         struct list_head        scan_list;
  98         struct completion       scan_wait;
  99
 100         struct Scsi_Host *scsi_host;
 101         spinlock_t devlock; /* to protect hba[ctlr]->dev[];  */
 102         int ndevices; /* number of used elements in .dev[] array. */
 103 #define HPSA_MAX_SCSI_DEVS_PER_HBA 256
 104         struct hpsa_scsi_dev_t *dev[HPSA_MAX_SCSI_DEVS_PER_HBA];
 105 };
 106 #define HPSA_ABORT_MSG 0
 107 #define HPSA_DEVICE_RESET_MSG 1
 108 #define HPSA_BUS_RESET_MSG 2
 109 #define HPSA_HOST_RESET_MSG 3
 110 #define HPSA_MSG_SEND_RETRY_LIMIT 10
 111 #define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS 1000
 112
 113 /* Maximum time in seconds driver will wait for command completions
 114  * when polling before giving up.
 115  */
 116 #define HPSA_MAX_POLL_TIME_SECS (20)
 117
 118 /* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines
 119  * how many times to retry TEST UNIT READY on a device
 120  * while waiting for it to become ready before giving up.
 121  * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval
 122  * between sending TURs while waiting for a device
 123  * to become ready.
 124  */
 125 #define HPSA_TUR_RETRY_LIMIT (20)
 126 #define HPSA_MAX_WAIT_INTERVAL_SECS (30)
 127
 128 /* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board
 129  * to become ready, in seconds, before giving up on it.
 130  * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
 131  * between polling the board to see if it is ready, in
 132  * milliseconds.  HPSA_BOARD_READY_POLL_INTERVAL and
 133  * HPSA_BOARD_READY_ITERATIONS are derived from those.
 134  */
 135 #define HPSA_BOARD_READY_WAIT_SECS (120)
 136 #define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100)
 137 #define HPSA_BOARD_READY_POLL_INTERVAL \
 138         ((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000)
 139 #define HPSA_BOARD_READY_ITERATIONS \
 140         ((HPSA_BOARD_READY_WAIT_SECS * 1000) / \
 141                 HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
 142 #define HPSA_POST_RESET_PAUSE_MSECS (3000)
 143 #define HPSA_POST_RESET_NOOP_RETRIES (12)
 144
 145 /*  Defining the diffent access_menthods */
 146 /*
 147  * Memory mapped FIFO interface (SMART 53xx cards)
 148  */
 149 #define SA5_DOORBELL    0x20
 150 #define SA5_REQUEST_PORT_OFFSET 0x40
 151 #define SA5_REPLY_INTR_MASK_OFFSET      0x34
 152 #define SA5_REPLY_PORT_OFFSET           0x44
 153 #define SA5_INTR_STATUS         0x30
 154 #define SA5_SCRATCHPAD_OFFSET   0xB0
 155
 156 #define SA5_CTCFG_OFFSET        0xB4
 157 #define SA5_CTMEM_OFFSET        0xB8
 158
 159 #define SA5_INTR_OFF            0x08
 160 #define SA5B_INTR_OFF           0x04
 161 #define SA5_INTR_PENDING        0x08
 162 #define SA5B_INTR_PENDING       0x04
 163 #define FIFO_EMPTY              0xffffffff
 164 #define HPSA_FIRMWARE_READY     0xffff0000 /* value in scratchpad register */
 165
 166 #define HPSA_ERROR_BIT          0x02
 167
 168 #define HPSA_INTR_ON    1
 169 #define HPSA_INTR_OFF   0
 170 /*
 171         Send the command to the hardware
 172 */
 173 static void SA5_submit_command(struct ctlr_info *h,
 174         struct CommandList *c)
 175 {
 176         dev_dbg(&h->pdev->dev, "Sending %x\n", c->busaddr);
 177         writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
 178         h->commands_outstanding++;
 179         if (h->commands_outstanding > h->max_outstanding)
 180                 h->max_outstanding = h->commands_outstanding;
 181 }
 182
 183 /*
 184  *  This card is the opposite of the other cards.
 185  *   0 turns interrupts on...
 186  *   0x08 turns them off...
 187  */
 188 static void SA5_intr_mask(struct ctlr_info *h, unsigned long val)
 189 {
 190         if (val) { /* Turn interrupts on */
 191                 h->interrupts_enabled = 1;
 192                 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
 193         } else { /* Turn them off */
 194                 h->interrupts_enabled = 0;
 195                 writel(SA5_INTR_OFF,
 196                         h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
 197         }
 198 }
 199 /*
 200  *  Returns true if fifo is full.
 201  *
 202  */
 203 static unsigned long SA5_fifo_full(struct ctlr_info *h)
 204 {
 205         if (h->commands_outstanding >= h->max_commands)
 206                 return 1;
 207         else
 208                 return 0;
 209
 210 }
 211 /*
 212  *   returns value read from hardware.
 213  *     returns FIFO_EMPTY if there is nothing to read
 214  */
 215 static unsigned long SA5_completed(struct ctlr_info *h)
 216 {
 217         unsigned long register_value
 218                 = readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
 219
 220         if (register_value != FIFO_EMPTY)
 221                 h->commands_outstanding--;
 222
 223 #ifdef HPSA_DEBUG
 224         if (register_value != FIFO_EMPTY)
 225                 dev_dbg(&h->pdev->dev, "Read %lx back from board\n",
 226                         register_value);
 227         else
 228                 dev_dbg(&h->pdev->dev, "hpsa: FIFO Empty read\n");
 229 #endif
 230
 231         return register_value;
 232 }
 233 /*
 234  *      Returns true if an interrupt is pending..
 235  */
 236 static unsigned long SA5_intr_pending(struct ctlr_info *h)
 237 {
 238         unsigned long register_value  =
 239                 readl(h->vaddr + SA5_INTR_STATUS);
 240         dev_dbg(&h->pdev->dev, "intr_pending %lx\n", register_value);
 241         if (register_value &  SA5_INTR_PENDING)
 242                 return  1;
 243         return 0 ;
 244 }
 245
 246
 247 static struct access_method SA5_access = {
 248         SA5_submit_command,
 249         SA5_intr_mask,
 250         SA5_fifo_full,
 251         SA5_intr_pending,
 252         SA5_completed,
 253 };
 254
 255 struct board_type {
 256         u32     board_id;
 257         char    *product_name;
 258         struct access_method *access;
 259 };
 260
 261
 262 /* end of old hpsa_scsi.h file */
 263
 264 #endif /* HPSA_H */
 265