drivers/dma/ste_dma40_ll.h

   1 /*
   2  * driver/dma/ste_dma40_ll.h
   3  *
   4  * Copyright (C) ST-Ericsson 2007-2010
   5  * License terms: GNU General Public License (GPL) version 2
   6  * Author: Per Friden <per.friden@stericsson.com>
   7  * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
   8  */
   9 #ifndef STE_DMA40_LL_H
  10 #define STE_DMA40_LL_H
  11
  12 #define D40_DREG_PCBASE         0x400
  13 #define D40_DREG_PCDELTA        (8 * 4)
  14 #define D40_LLI_ALIGN           16 /* LLI alignment must be 16 bytes. */
  15
  16 #define D40_TYPE_TO_GROUP(type) (type / 16)
  17 #define D40_TYPE_TO_EVENT(type) (type % 16)
  18
  19 /* Most bits of the CFG register are the same in log as in phy mode */
  20 #define D40_SREG_CFG_MST_POS            15
  21 #define D40_SREG_CFG_TIM_POS            14
  22 #define D40_SREG_CFG_EIM_POS            13
  23 #define D40_SREG_CFG_LOG_INCR_POS       12
  24 #define D40_SREG_CFG_PHY_PEN_POS        12
  25 #define D40_SREG_CFG_PSIZE_POS          10
  26 #define D40_SREG_CFG_ESIZE_POS           8
  27 #define D40_SREG_CFG_PRI_POS             7
  28 #define D40_SREG_CFG_LBE_POS             6
  29 #define D40_SREG_CFG_LOG_GIM_POS         5
  30 #define D40_SREG_CFG_LOG_MFU_POS         4
  31 #define D40_SREG_CFG_PHY_TM_POS          4
  32 #define D40_SREG_CFG_PHY_EVTL_POS        0
  33
  34
  35 /* Standard channel parameters - basic mode (element register) */
  36 #define D40_SREG_ELEM_PHY_ECNT_POS      16
  37 #define D40_SREG_ELEM_PHY_EIDX_POS       0
  38
  39 #define D40_SREG_ELEM_PHY_ECNT_MASK     (0xFFFF << D40_SREG_ELEM_PHY_ECNT_POS)
  40
  41 /* Standard channel parameters - basic mode (Link register) */
  42 #define D40_SREG_LNK_PHY_TCP_POS        0
  43 #define D40_SREG_LNK_PHY_LMP_POS        1
  44 #define D40_SREG_LNK_PHY_PRE_POS        2
  45 /*
  46  * Source  destination link address. Contains the
  47  * 29-bit byte word aligned address of the reload area.
  48  */
  49 #define D40_SREG_LNK_PHYS_LNK_MASK      0xFFFFFFF8UL
  50
  51 /* Standard basic channel logical mode */
  52
  53 /* Element register */
  54 #define D40_SREG_ELEM_LOG_ECNT_POS      16
  55 #define D40_SREG_ELEM_LOG_LIDX_POS       8
  56 #define D40_SREG_ELEM_LOG_LOS_POS        1
  57 #define D40_SREG_ELEM_LOG_TCP_POS        0
  58
  59 #define D40_SREG_ELEM_LOG_LIDX_MASK     (0xFF << D40_SREG_ELEM_LOG_LIDX_POS)
  60
  61 /* Link register */
  62 #define D40_DEACTIVATE_EVENTLINE        0x0
  63 #define D40_ACTIVATE_EVENTLINE          0x1
  64 #define D40_EVENTLINE_POS(i)            (2 * i)
  65 #define D40_EVENTLINE_MASK(i)           (0x3 << D40_EVENTLINE_POS(i))
  66
  67 /* Standard basic channel logical params in memory */
  68
  69 /* LCSP0 */
  70 #define D40_MEM_LCSP0_ECNT_POS          16
  71 #define D40_MEM_LCSP0_SPTR_POS           0
  72
  73 #define D40_MEM_LCSP0_ECNT_MASK         (0xFFFF << D40_MEM_LCSP0_ECNT_POS)
  74 #define D40_MEM_LCSP0_SPTR_MASK         (0xFFFF << D40_MEM_LCSP0_SPTR_POS)
  75
  76 /* LCSP1 */
  77 #define D40_MEM_LCSP1_SPTR_POS          16
  78 #define D40_MEM_LCSP1_SCFG_MST_POS      15
  79 #define D40_MEM_LCSP1_SCFG_TIM_POS      14
  80 #define D40_MEM_LCSP1_SCFG_EIM_POS      13
  81 #define D40_MEM_LCSP1_SCFG_INCR_POS     12
  82 #define D40_MEM_LCSP1_SCFG_PSIZE_POS    10
  83 #define D40_MEM_LCSP1_SCFG_ESIZE_POS     8
  84 #define D40_MEM_LCSP1_SLOS_POS           1
  85 #define D40_MEM_LCSP1_STCP_POS           0
  86
  87 #define D40_MEM_LCSP1_SPTR_MASK         (0xFFFF << D40_MEM_LCSP1_SPTR_POS)
  88 #define D40_MEM_LCSP1_SCFG_TIM_MASK     (0x1 << D40_MEM_LCSP1_SCFG_TIM_POS)
  89 #define D40_MEM_LCSP1_SCFG_INCR_MASK    (0x1 << D40_MEM_LCSP1_SCFG_INCR_POS)
  90 #define D40_MEM_LCSP1_SCFG_PSIZE_MASK   (0x3 << D40_MEM_LCSP1_SCFG_PSIZE_POS)
  91 #define D40_MEM_LCSP1_SLOS_MASK         (0x7F << D40_MEM_LCSP1_SLOS_POS)
  92 #define D40_MEM_LCSP1_STCP_MASK         (0x1 << D40_MEM_LCSP1_STCP_POS)
  93
  94 /* LCSP2 */
  95 #define D40_MEM_LCSP2_ECNT_POS          16
  96
  97 #define D40_MEM_LCSP2_ECNT_MASK         (0xFFFF << D40_MEM_LCSP2_ECNT_POS)
  98
  99 /* LCSP3 */
 100 #define D40_MEM_LCSP3_DCFG_MST_POS      15
 101 #define D40_MEM_LCSP3_DCFG_TIM_POS      14
 102 #define D40_MEM_LCSP3_DCFG_EIM_POS      13
 103 #define D40_MEM_LCSP3_DCFG_INCR_POS     12
 104 #define D40_MEM_LCSP3_DCFG_PSIZE_POS    10
 105 #define D40_MEM_LCSP3_DCFG_ESIZE_POS     8
 106 #define D40_MEM_LCSP3_DLOS_POS           1
 107 #define D40_MEM_LCSP3_DTCP_POS           0
 108
 109 #define D40_MEM_LCSP3_DLOS_MASK         (0x7F << D40_MEM_LCSP3_DLOS_POS)
 110 #define D40_MEM_LCSP3_DTCP_MASK         (0x1 << D40_MEM_LCSP3_DTCP_POS)
 111
 112
 113 /* Standard channel parameter register offsets */
 114 #define D40_CHAN_REG_SSCFG      0x00
 115 #define D40_CHAN_REG_SSELT      0x04
 116 #define D40_CHAN_REG_SSPTR      0x08
 117 #define D40_CHAN_REG_SSLNK      0x0C
 118 #define D40_CHAN_REG_SDCFG      0x10
 119 #define D40_CHAN_REG_SDELT      0x14
 120 #define D40_CHAN_REG_SDPTR      0x18
 121 #define D40_CHAN_REG_SDLNK      0x1C
 122
 123 /* DMA Register Offsets */
 124 #define D40_DREG_GCC            0x000
 125 #define D40_DREG_PRTYP          0x004
 126 #define D40_DREG_PRSME          0x008
 127 #define D40_DREG_PRSMO          0x00C
 128 #define D40_DREG_PRMSE          0x010
 129 #define D40_DREG_PRMSO          0x014
 130 #define D40_DREG_PRMOE          0x018
 131 #define D40_DREG_PRMOO          0x01C
 132 #define D40_DREG_LCPA           0x020
 133 #define D40_DREG_LCLA           0x024
 134 #define D40_DREG_ACTIVE         0x050
 135 #define D40_DREG_ACTIVO         0x054
 136 #define D40_DREG_FSEB1          0x058
 137 #define D40_DREG_FSEB2          0x05C
 138 #define D40_DREG_PCMIS          0x060
 139 #define D40_DREG_PCICR          0x064
 140 #define D40_DREG_PCTIS          0x068
 141 #define D40_DREG_PCEIS          0x06C
 142 #define D40_DREG_LCMIS0         0x080
 143 #define D40_DREG_LCMIS1         0x084
 144 #define D40_DREG_LCMIS2         0x088
 145 #define D40_DREG_LCMIS3         0x08C
 146 #define D40_DREG_LCICR0         0x090
 147 #define D40_DREG_LCICR1         0x094
 148 #define D40_DREG_LCICR2         0x098
 149 #define D40_DREG_LCICR3         0x09C
 150 #define D40_DREG_LCTIS0         0x0A0
 151 #define D40_DREG_LCTIS1         0x0A4
 152 #define D40_DREG_LCTIS2         0x0A8
 153 #define D40_DREG_LCTIS3         0x0AC
 154 #define D40_DREG_LCEIS0         0x0B0
 155 #define D40_DREG_LCEIS1         0x0B4
 156 #define D40_DREG_LCEIS2         0x0B8
 157 #define D40_DREG_LCEIS3         0x0BC
 158 #define D40_DREG_STFU           0xFC8
 159 #define D40_DREG_ICFG           0xFCC
 160 #define D40_DREG_PERIPHID0      0xFE0
 161 #define D40_DREG_PERIPHID1      0xFE4
 162 #define D40_DREG_PERIPHID2      0xFE8
 163 #define D40_DREG_PERIPHID3      0xFEC
 164 #define D40_DREG_CELLID0        0xFF0
 165 #define D40_DREG_CELLID1        0xFF4
 166 #define D40_DREG_CELLID2        0xFF8
 167 #define D40_DREG_CELLID3        0xFFC
 168
 169 /* LLI related structures */
 170
 171 /**
 172  * struct d40_phy_lli - The basic configration register for each physical
 173  * channel.
 174  *
 175  * @reg_cfg: The configuration register.
 176  * @reg_elt: The element register.
 177  * @reg_ptr: The pointer register.
 178  * @reg_lnk: The link register.
 179  *
 180  * These registers are set up for both physical and logical transfers
 181  * Note that the bit in each register means differently in logical and
 182  * physical(standard) mode.
 183  *
 184  * This struct must be 16 bytes aligned, and only contain physical registers
 185  * since it will be directly accessed by the DMA.
 186  */
 187 struct d40_phy_lli {
 188         u32 reg_cfg;
 189         u32 reg_elt;
 190         u32 reg_ptr;
 191         u32 reg_lnk;
 192 };
 193
 194 /**
 195  * struct d40_phy_lli_bidir - struct for a transfer.
 196  *
 197  * @src: Register settings for src channel.
 198  * @dst: Register settings for dst channel.
 199  * @dst_addr: Physical destination address.
 200  * @src_addr: Physical source address.
 201  *
 202  * All DMA transfers have a source and a destination.
 203  */
 204
 205 struct d40_phy_lli_bidir {
 206         struct d40_phy_lli      *src;
 207         struct d40_phy_lli      *dst;
 208         dma_addr_t               dst_addr;
 209         dma_addr_t               src_addr;
 210 };
 211
 212
 213 /**
 214  * struct d40_log_lli - logical lli configuration
 215  *
 216  * @lcsp02: Either maps to register lcsp0 if src or lcsp2 if dst.
 217  * @lcsp13: Either maps to register lcsp1 if src or lcsp3 if dst.
 218  *
 219  * This struct must be 8 bytes aligned since it will be accessed directy by
 220  * the DMA. Never add any none hw mapped registers to this struct.
 221  */
 222
 223 struct d40_log_lli {
 224         u32 lcsp02;
 225         u32 lcsp13;
 226 };
 227
 228 /**
 229  * struct d40_log_lli_bidir - For both src and dst
 230  *
 231  * @src: pointer to src lli configuration.
 232  * @dst: pointer to dst lli configuration.
 233  *
 234  * You always have a src and a dst when doing DMA transfers.
 235  */
 236
 237 struct d40_log_lli_bidir {
 238         struct d40_log_lli *src;
 239         struct d40_log_lli *dst;
 240 };
 241
 242 /**
 243  * struct d40_log_lli_full - LCPA layout
 244  *
 245  * @lcsp0: Logical Channel Standard Param 0 - Src.
 246  * @lcsp1: Logical Channel Standard Param 1 - Src.
 247  * @lcsp2: Logical Channel Standard Param 2 - Dst.
 248  * @lcsp3: Logical Channel Standard Param 3 - Dst.
 249  *
 250  * This struct maps to LCPA physical memory layout. Must map to
 251  * the hw.
 252  */
 253 struct d40_log_lli_full {
 254         u32 lcsp0;
 255         u32 lcsp1;
 256         u32 lcsp2;
 257         u32 lcsp3;
 258 };
 259
 260 /**
 261  * struct d40_def_lcsp - Default LCSP1 and LCSP3 settings
 262  *
 263  * @lcsp3: The default configuration for dst.
 264  * @lcsp1: The default configuration for src.
 265  */
 266 struct d40_def_lcsp {
 267         u32 lcsp3;
 268         u32 lcsp1;
 269 };
 270
 271 /**
 272  * struct d40_lcla_elem - Info for one LCA element.
 273  *
 274  * @src_id: logical channel src id
 275  * @dst_id: logical channel dst id
 276  * @src: LCPA formated src parameters
 277  * @dst: LCPA formated dst parameters
 278  *
 279  */
 280 struct d40_lcla_elem {
 281         int                     src_id;
 282         int                     dst_id;
 283         struct d40_log_lli     *src;
 284         struct d40_log_lli     *dst;
 285 };
 286
 287 /* Physical channels */
 288
 289 void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
 290                  u32 *src_cfg, u32 *dst_cfg, bool is_log);
 291
 292 void d40_log_cfg(struct stedma40_chan_cfg *cfg,
 293                  u32 *lcsp1, u32 *lcsp2);
 294
 295 int d40_phy_sg_to_lli(struct scatterlist *sg,
 296                       int sg_len,
 297                       dma_addr_t target,
 298                       struct d40_phy_lli *lli,
 299                       dma_addr_t lli_phys,
 300                       u32 reg_cfg,
 301                       u32 data_width,
 302                       int psize,
 303                       bool term_int);
 304
 305 int d40_phy_fill_lli(struct d40_phy_lli *lli,
 306                      dma_addr_t data,
 307                      u32 data_size,
 308                      int psize,
 309                      dma_addr_t next_lli,
 310                      u32 reg_cfg,
 311                      bool term_int,
 312                      u32 data_width,
 313                      bool is_device);
 314
 315 void d40_phy_lli_write(void __iomem *virtbase,
 316                        u32 phy_chan_num,
 317                        struct d40_phy_lli *lli_dst,
 318                        struct d40_phy_lli *lli_src);
 319
 320 /* Logical channels */
 321
 322 void d40_log_fill_lli(struct d40_log_lli *lli,
 323                       dma_addr_t data, u32 data_size,
 324                       u32 lli_next_off, u32 reg_cfg,
 325                       u32 data_width,
 326                       bool term_int, bool addr_inc);
 327
 328 int d40_log_sg_to_dev(struct d40_lcla_elem *lcla,
 329                       struct scatterlist *sg,
 330                       int sg_len,
 331                       struct d40_log_lli_bidir *lli,
 332                       struct d40_def_lcsp *lcsp,
 333                       u32 src_data_width,
 334                       u32 dst_data_width,
 335                       enum dma_data_direction direction,
 336                       bool term_int, dma_addr_t dev_addr, int max_len,
 337                       int llis_per_log);
 338
 339 void d40_log_lli_write(struct d40_log_lli_full *lcpa,
 340                        struct d40_log_lli *lcla_src,
 341                        struct d40_log_lli *lcla_dst,
 342                        struct d40_log_lli *lli_dst,
 343                        struct d40_log_lli *lli_src,
 344                        int llis_per_log);
 345
 346 int d40_log_sg_to_lli(int lcla_id,
 347                       struct scatterlist *sg,
 348                       int sg_len,
 349                       struct d40_log_lli *lli_sg,
 350                       u32 lcsp13, /* src or dst*/
 351                       u32 data_width,
 352                       bool term_int, int max_len, int llis_per_log);
 353
 354 #endif /* STE_DMA40_LLI_H */