drivers/net/bnx2x/bnx2x_link.h

   1 /* Copyright 2008-2010 Broadcom Corporation
   2  *
   3  * Unless you and Broadcom execute a separate written software license
   4  * agreement governing use of this software, this software is licensed to you
   5  * under the terms of the GNU General Public License version 2, available
   6  * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
   7  *
   8  * Notwithstanding the above, under no circumstances may you combine this
   9  * software in any way with any other Broadcom software provided under a
  10  * license other than the GPL, without Broadcom's express prior written
  11  * consent.
  12  *
  13  * Written by Yaniv Rosner
  14  *
  15  */
  16
  17 #ifndef BNX2X_LINK_H
  18 #define BNX2X_LINK_H
  19
  20
  21
  22 /***********************************************************/
  23 /*                         Defines                         */
  24 /***********************************************************/
  25 #define DEFAULT_PHY_DEV_ADDR    3
  26 #define E2_DEFAULT_PHY_DEV_ADDR 5
  27
  28
  29
  30 #define BNX2X_FLOW_CTRL_AUTO            PORT_FEATURE_FLOW_CONTROL_AUTO
  31 #define BNX2X_FLOW_CTRL_TX              PORT_FEATURE_FLOW_CONTROL_TX
  32 #define BNX2X_FLOW_CTRL_RX              PORT_FEATURE_FLOW_CONTROL_RX
  33 #define BNX2X_FLOW_CTRL_BOTH            PORT_FEATURE_FLOW_CONTROL_BOTH
  34 #define BNX2X_FLOW_CTRL_NONE            PORT_FEATURE_FLOW_CONTROL_NONE
  35
  36 #define SPEED_AUTO_NEG      0
  37 #define SPEED_12000             12000
  38 #define SPEED_12500             12500
  39 #define SPEED_13000             13000
  40 #define SPEED_15000             15000
  41 #define SPEED_16000             16000
  42
  43 #define SFP_EEPROM_VENDOR_NAME_ADDR             0x14
  44 #define SFP_EEPROM_VENDOR_NAME_SIZE             16
  45 #define SFP_EEPROM_VENDOR_OUI_ADDR              0x25
  46 #define SFP_EEPROM_VENDOR_OUI_SIZE              3
  47 #define SFP_EEPROM_PART_NO_ADDR                 0x28
  48 #define SFP_EEPROM_PART_NO_SIZE         16
  49 #define PWR_FLT_ERR_MSG_LEN                     250
  50
  51 #define XGXS_EXT_PHY_TYPE(ext_phy_config) \
  52                 ((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
  53 #define XGXS_EXT_PHY_ADDR(ext_phy_config) \
  54                 (((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \
  55                  PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT)
  56 #define SERDES_EXT_PHY_TYPE(ext_phy_config) \
  57                 ((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
  58
  59 /* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */
  60 #define SINGLE_MEDIA_DIRECT(params)     (params->num_phys == 1)
  61 /* Single Media board contains single external phy */
  62 #define SINGLE_MEDIA(params)            (params->num_phys == 2)
  63 /* Dual Media board contains two external phy with different media */
  64 #define DUAL_MEDIA(params)              (params->num_phys == 3)
  65 #define FW_PARAM_MDIO_CTRL_OFFSET 16
  66 #define FW_PARAM_SET(phy_addr, phy_type, mdio_access) \
  67         (phy_addr | phy_type | mdio_access << FW_PARAM_MDIO_CTRL_OFFSET)
  68
  69 #define PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_PAUSEABLE              170
  70 #define PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_NON_PAUSEABLE          0
  71
  72 #define PFC_BRB_MAC_PAUSE_XON_THRESHOLD_PAUSEABLE                       250
  73 #define PFC_BRB_MAC_PAUSE_XON_THRESHOLD_NON_PAUSEABLE           0
  74
  75 #define PFC_BRB_MAC_FULL_XOFF_THRESHOLD_PAUSEABLE                       10
  76 #define PFC_BRB_MAC_FULL_XOFF_THRESHOLD_NON_PAUSEABLE           90
  77
  78 #define PFC_BRB_MAC_FULL_XON_THRESHOLD_PAUSEABLE                        50
  79 #define PFC_BRB_MAC_FULL_XON_THRESHOLD_NON_PAUSEABLE            250
  80
  81 #define PFC_BRB_FULL_LB_XOFF_THRESHOLD                          170
  82 #define PFC_BRB_FULL_LB_XON_THRESHOLD                           250
  83
  84 /***********************************************************/
  85 /*                         Structs                         */
  86 /***********************************************************/
  87 #define INT_PHY         0
  88 #define EXT_PHY1        1
  89 #define EXT_PHY2        2
  90 #define MAX_PHYS        3
  91
  92 /* Same configuration is shared between the XGXS and the first external phy */
  93 #define LINK_CONFIG_SIZE (MAX_PHYS - 1)
  94 #define LINK_CONFIG_IDX(_phy_idx) ((_phy_idx == INT_PHY) ? \
  95                                          0 : (_phy_idx - 1))
  96 /***********************************************************/
  97 /*                      bnx2x_phy struct                     */
  98 /*  Defines the required arguments and function per phy    */
  99 /***********************************************************/
 100 struct link_vars;
 101 struct link_params;
 102 struct bnx2x_phy;
 103
 104 typedef u8 (*config_init_t)(struct bnx2x_phy *phy, struct link_params *params,
 105                             struct link_vars *vars);
 106 typedef u8 (*read_status_t)(struct bnx2x_phy *phy, struct link_params *params,
 107                             struct link_vars *vars);
 108 typedef void (*link_reset_t)(struct bnx2x_phy *phy,
 109                              struct link_params *params);
 110 typedef void (*config_loopback_t)(struct bnx2x_phy *phy,
 111                                   struct link_params *params);
 112 typedef u8 (*format_fw_ver_t)(u32 raw, u8 *str, u16 *len);
 113 typedef void (*hw_reset_t)(struct bnx2x_phy *phy, struct link_params *params);
 114 typedef void (*set_link_led_t)(struct bnx2x_phy *phy,
 115                                struct link_params *params, u8 mode);
 116 typedef void (*phy_specific_func_t)(struct bnx2x_phy *phy,
 117                                     struct link_params *params, u32 action);
 118
 119 struct bnx2x_phy {
 120         u32 type;
 121
 122         /* Loaded during init */
 123         u8 addr;
 124
 125         u8 flags;
 126         /* Require HW lock */
 127 #define FLAGS_HW_LOCK_REQUIRED          (1<<0)
 128         /* No Over-Current detection */
 129 #define FLAGS_NOC                       (1<<1)
 130         /* Fan failure detection required */
 131 #define FLAGS_FAN_FAILURE_DET_REQ       (1<<2)
 132         /* Initialize first the XGXS and only then the phy itself */
 133 #define FLAGS_INIT_XGXS_FIRST           (1<<3)
 134 #define FLAGS_REARM_LATCH_SIGNAL        (1<<6)
 135 #define FLAGS_SFP_NOT_APPROVED          (1<<7)
 136
 137         u8 def_md_devad;
 138         u8 reserved;
 139         /* preemphasis values for the rx side */
 140         u16 rx_preemphasis[4];
 141
 142         /* preemphasis values for the tx side */
 143         u16 tx_preemphasis[4];
 144
 145         /* EMAC address for access MDIO */
 146         u32 mdio_ctrl;
 147
 148         u32 supported;
 149
 150         u32 media_type;
 151 #define ETH_PHY_UNSPECIFIED 0x0
 152 #define ETH_PHY_SFP_FIBER   0x1
 153 #define ETH_PHY_XFP_FIBER   0x2
 154 #define ETH_PHY_DA_TWINAX   0x3
 155 #define ETH_PHY_BASE_T      0x4
 156 #define ETH_PHY_NOT_PRESENT 0xff
 157
 158         /* The address in which version is located*/
 159         u32 ver_addr;
 160
 161         u16 req_flow_ctrl;
 162
 163         u16 req_line_speed;
 164
 165         u32 speed_cap_mask;
 166
 167         u16 req_duplex;
 168         u16 rsrv;
 169         /* Called per phy/port init, and it configures LASI, speed, autoneg,
 170          duplex, flow control negotiation, etc. */
 171         config_init_t config_init;
 172
 173         /* Called due to interrupt. It determines the link, speed */
 174         read_status_t read_status;
 175
 176         /* Called when driver is unloading. Should reset the phy */
 177         link_reset_t link_reset;
 178
 179         /* Set the loopback configuration for the phy */
 180         config_loopback_t config_loopback;
 181
 182         /* Format the given raw number into str up to len */
 183         format_fw_ver_t format_fw_ver;
 184
 185         /* Reset the phy (both ports) */
 186         hw_reset_t hw_reset;
 187
 188         /* Set link led mode (on/off/oper)*/
 189         set_link_led_t set_link_led;
 190
 191         /* PHY Specific tasks */
 192         phy_specific_func_t phy_specific_func;
 193 #define DISABLE_TX      1
 194 #define ENABLE_TX       2
 195 };
 196
 197 /* Inputs parameters to the CLC */
 198 struct link_params {
 199
 200         u8 port;
 201
 202         /* Default / User Configuration */
 203         u8 loopback_mode;
 204 #define LOOPBACK_NONE   0
 205 #define LOOPBACK_EMAC   1
 206 #define LOOPBACK_BMAC   2
 207 #define LOOPBACK_XGXS           3
 208 #define LOOPBACK_EXT_PHY        4
 209 #define LOOPBACK_EXT    5
 210
 211         /* Device parameters */
 212         u8 mac_addr[6];
 213
 214         u16 req_duplex[LINK_CONFIG_SIZE];
 215         u16 req_flow_ctrl[LINK_CONFIG_SIZE];
 216
 217         u16 req_line_speed[LINK_CONFIG_SIZE]; /* Also determine AutoNeg */
 218
 219         /* shmem parameters */
 220         u32 shmem_base;
 221         u32 shmem2_base;
 222         u32 speed_cap_mask[LINK_CONFIG_SIZE];
 223         u32 switch_cfg;
 224 #define SWITCH_CFG_1G           PORT_FEATURE_CON_SWITCH_1G_SWITCH
 225 #define SWITCH_CFG_10G          PORT_FEATURE_CON_SWITCH_10G_SWITCH
 226 #define SWITCH_CFG_AUTO_DETECT  PORT_FEATURE_CON_SWITCH_AUTO_DETECT
 227
 228         u32 lane_config;
 229
 230         /* Phy register parameter */
 231         u32 chip_id;
 232
 233         u32 feature_config_flags;
 234 #define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0)
 235 #define FEATURE_CONFIG_PFC_ENABLED              (1<<1)
 236 #define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2)
 237 #define FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY        (1<<3)
 238         /* Will be populated during common init */
 239         struct bnx2x_phy phy[MAX_PHYS];
 240
 241         /* Will be populated during common init */
 242         u8 num_phys;
 243
 244         u8 rsrv;
 245         u16 hw_led_mode; /* part of the hw_config read from the shmem */
 246         u32 multi_phy_config;
 247
 248         /* Device pointer passed to all callback functions */
 249         struct bnx2x *bp;
 250         u16 req_fc_auto_adv; /* Should be set to TX / BOTH when
 251                                 req_flow_ctrl is set to AUTO */
 252 };
 253
 254 /* Output parameters */
 255 struct link_vars {
 256         u8 phy_flags;
 257
 258         u8 mac_type;
 259 #define MAC_TYPE_NONE           0
 260 #define MAC_TYPE_EMAC           1
 261 #define MAC_TYPE_BMAC           2
 262
 263         u8 phy_link_up; /* internal phy link indication */
 264         u8 link_up;
 265
 266         u16 line_speed;
 267         u16 duplex;
 268
 269         u16 flow_ctrl;
 270         u16 ieee_fc;
 271
 272         /* The same definitions as the shmem parameter */
 273         u32 link_status;
 274 };
 275
 276 /***********************************************************/
 277 /*                         Functions                       */
 278 /***********************************************************/
 279 u8 bnx2x_phy_init(struct link_params *input, struct link_vars *output);
 280
 281 /* Reset the link. Should be called when driver or interface goes down
 282    Before calling phy firmware upgrade, the reset_ext_phy should be set
 283    to 0 */
 284 u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
 285                   u8 reset_ext_phy);
 286
 287 /* bnx2x_link_update should be called upon link interrupt */
 288 u8 bnx2x_link_update(struct link_params *input, struct link_vars *output);
 289
 290 /* use the following phy functions to read/write from external_phy
 291   In order to use it to read/write internal phy registers, use
 292   DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as
 293   the register */
 294 u8 bnx2x_phy_read(struct link_params *params, u8 phy_addr,
 295                   u8 devad, u16 reg, u16 *ret_val);
 296
 297 u8 bnx2x_phy_write(struct link_params *params, u8 phy_addr,
 298                    u8 devad, u16 reg, u16 val);
 299 /* Reads the link_status from the shmem,
 300    and update the link vars accordingly */
 301 void bnx2x_link_status_update(struct link_params *input,
 302                             struct link_vars *output);
 303 /* returns string representing the fw_version of the external phy */
 304 u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
 305                               u8 *version, u16 len);
 306
 307 /* Set/Unset the led
 308    Basically, the CLC takes care of the led for the link, but in case one needs
 309    to set/unset the led unnaturally, set the "mode" to LED_MODE_OPER to
 310    blink the led, and LED_MODE_OFF to set the led off.*/
 311 u8 bnx2x_set_led(struct link_params *params, struct link_vars *vars,
 312                  u8 mode, u32 speed);
 313 #define LED_MODE_OFF                    0
 314 #define LED_MODE_ON                     1
 315 #define LED_MODE_OPER                   2
 316 #define LED_MODE_FRONT_PANEL_OFF        3
 317
 318 /* bnx2x_handle_module_detect_int should be called upon module detection
 319    interrupt */
 320 void bnx2x_handle_module_detect_int(struct link_params *params);
 321
 322 /* Get the actual link status. In case it returns 0, link is up,
 323         otherwise link is down*/
 324 u8 bnx2x_test_link(struct link_params *input, struct link_vars *vars,
 325                    u8 is_serdes);
 326
 327 /* One-time initialization for external phy after power up */
 328 u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
 329                          u32 shmem2_base_path[], u32 chip_id);
 330
 331 /* Reset the external PHY using GPIO */
 332 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port);
 333
 334 /* Reset the external of SFX7101 */
 335 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy);
 336
 337 void bnx2x_hw_reset_phy(struct link_params *params);
 338
 339 /* Checks if HW lock is required for this phy/board type */
 340 u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base,
 341                           u32 shmem2_base);
 342
 343 /* Check swap bit and adjust PHY order */
 344 u32 bnx2x_phy_selection(struct link_params *params);
 345
 346 /* Probe the phys on board, and populate them in "params" */
 347 u8 bnx2x_phy_probe(struct link_params *params);
 348 /* Checks if fan failure detection is required on one of the phys on board */
 349 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, u32 shmem_base,
 350                              u32 shmem2_base, u8 port);
 351
 352 /* PFC port configuration params */
 353 struct bnx2x_nig_brb_pfc_port_params {
 354         /* NIG */
 355         u32 pause_enable;
 356         u32 llfc_out_en;
 357         u32 llfc_enable;
 358         u32 pkt_priority_to_cos;
 359         u32 rx_cos0_priority_mask;
 360         u32 rx_cos1_priority_mask;
 361         u32 llfc_high_priority_classes;
 362         u32 llfc_low_priority_classes;
 363         /* BRB */
 364         u32 cos0_pauseable;
 365         u32 cos1_pauseable;
 366 };
 367
 368 /**
 369  * Used to update the PFC attributes in EMAC, BMAC, NIG and BRB
 370  * when link is already up
 371  */
 372 void bnx2x_update_pfc(struct link_params *params,
 373                       struct link_vars *vars,
 374                       struct bnx2x_nig_brb_pfc_port_params *pfc_params);
 375
 376
 377 /* Used to configure the ETS to disable */
 378 void bnx2x_ets_disabled(struct link_params *params);
 379
 380 /* Used to configure the ETS to BW limited */
 381 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
 382                                                 const u32 cos1_bw);
 383
 384 /* Used to configure the ETS to strict */
 385 u8 bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos);
 386
 387 /* Read pfc statistic*/
 388 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
 389                                                  u32 pfc_frames_sent[2],
 390                                                  u32 pfc_frames_received[2]);
 391 #endif /* BNX2X_LINK_H */