drivers/net/wireless/ath/ar9170/hw.h

   1 /*
   2  * Atheros AR9170 driver
   3  *
   4  * Hardware-specific definitions
   5  *
   6  * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; see the file COPYING.  If not, see
  20  * http://www.gnu.org/licenses/.
  21  *
  22  * This file incorporates work covered by the following copyright and
  23  * permission notice:
  24  *    Copyright (c) 2007-2008 Atheros Communications, Inc.
  25  *
  26  *    Permission to use, copy, modify, and/or distribute this software for any
  27  *    purpose with or without fee is hereby granted, provided that the above
  28  *    copyright notice and this permission notice appear in all copies.
  29  *
  30  *    THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  31  *    WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  32  *    MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  33  *    ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  34  *    WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  35  *    ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  36  *    OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  37  */
  38 #ifndef __AR9170_HW_H
  39 #define __AR9170_HW_H
  40
  41 #define AR9170_MAX_CMD_LEN      64
  42
  43 enum ar9170_cmd {
  44         AR9170_CMD_RREG         = 0x00,
  45         AR9170_CMD_WREG         = 0x01,
  46         AR9170_CMD_RMEM         = 0x02,
  47         AR9170_CMD_WMEM         = 0x03,
  48         AR9170_CMD_BITAND       = 0x04,
  49         AR9170_CMD_BITOR        = 0x05,
  50         AR9170_CMD_EKEY         = 0x28,
  51         AR9170_CMD_DKEY         = 0x29,
  52         AR9170_CMD_FREQUENCY    = 0x30,
  53         AR9170_CMD_RF_INIT      = 0x31,
  54         AR9170_CMD_SYNTH        = 0x32,
  55         AR9170_CMD_FREQ_START   = 0x33,
  56         AR9170_CMD_ECHO         = 0x80,
  57         AR9170_CMD_TALLY        = 0x81,
  58         AR9170_CMD_TALLY_APD    = 0x82,
  59         AR9170_CMD_CONFIG       = 0x83,
  60         AR9170_CMD_RESET        = 0x90,
  61         AR9170_CMD_DKRESET      = 0x91,
  62         AR9170_CMD_DKTX_STATUS  = 0x92,
  63         AR9170_CMD_FDC          = 0xA0,
  64         AR9170_CMD_WREEPROM     = 0xB0,
  65         AR9170_CMD_WFLASH       = 0xB0,
  66         AR9170_CMD_FLASH_ERASE  = 0xB1,
  67         AR9170_CMD_FLASH_PROG   = 0xB2,
  68         AR9170_CMD_FLASH_CHKSUM = 0xB3,
  69         AR9170_CMD_FLASH_READ   = 0xB4,
  70         AR9170_CMD_FW_DL_INIT   = 0xB5,
  71         AR9170_CMD_MEM_WREEPROM = 0xBB,
  72 };
  73
  74 /* endpoints */
  75 #define AR9170_EP_TX                            1
  76 #define AR9170_EP_RX                            2
  77 #define AR9170_EP_IRQ                           3
  78 #define AR9170_EP_CMD                           4
  79
  80 #define AR9170_EEPROM_START                     0x1600
  81
  82 #define AR9170_GPIO_REG_BASE                    0x1d0100
  83 #define AR9170_GPIO_REG_PORT_TYPE               AR9170_GPIO_REG_BASE
  84 #define AR9170_GPIO_REG_DATA                    (AR9170_GPIO_REG_BASE + 4)
  85 #define AR9170_NUM_LEDS                         2
  86
  87
  88 #define AR9170_USB_REG_BASE                     0x1e1000
  89 #define AR9170_USB_REG_DMA_CTL                  (AR9170_USB_REG_BASE + 0x108)
  90 #define         AR9170_DMA_CTL_ENABLE_TO_DEVICE         0x1
  91 #define         AR9170_DMA_CTL_ENABLE_FROM_DEVICE       0x2
  92 #define         AR9170_DMA_CTL_HIGH_SPEED               0x4
  93 #define         AR9170_DMA_CTL_PACKET_MODE              0x8
  94
  95 #define AR9170_USB_REG_MAX_AGG_UPLOAD           (AR9170_USB_REG_BASE + 0x110)
  96 #define AR9170_USB_REG_UPLOAD_TIME_CTL          (AR9170_USB_REG_BASE + 0x114)
  97
  98
  99
 100 #define AR9170_MAC_REG_BASE                     0x1c3000
 101
 102 #define AR9170_MAC_REG_TSF_L                    (AR9170_MAC_REG_BASE + 0x514)
 103 #define AR9170_MAC_REG_TSF_H                    (AR9170_MAC_REG_BASE + 0x518)
 104
 105 #define AR9170_MAC_REG_ATIM_WINDOW              (AR9170_MAC_REG_BASE + 0x51C)
 106 #define AR9170_MAC_REG_BCN_PERIOD               (AR9170_MAC_REG_BASE + 0x520)
 107 #define AR9170_MAC_REG_PRETBTT                  (AR9170_MAC_REG_BASE + 0x524)
 108
 109 #define AR9170_MAC_REG_MAC_ADDR_L               (AR9170_MAC_REG_BASE + 0x610)
 110 #define AR9170_MAC_REG_MAC_ADDR_H               (AR9170_MAC_REG_BASE + 0x614)
 111 #define AR9170_MAC_REG_BSSID_L                  (AR9170_MAC_REG_BASE + 0x618)
 112 #define AR9170_MAC_REG_BSSID_H                  (AR9170_MAC_REG_BASE + 0x61c)
 113
 114 #define AR9170_MAC_REG_GROUP_HASH_TBL_L         (AR9170_MAC_REG_BASE + 0x624)
 115 #define AR9170_MAC_REG_GROUP_HASH_TBL_H         (AR9170_MAC_REG_BASE + 0x628)
 116
 117 #define AR9170_MAC_REG_RX_TIMEOUT               (AR9170_MAC_REG_BASE + 0x62C)
 118
 119 #define AR9170_MAC_REG_BASIC_RATE               (AR9170_MAC_REG_BASE + 0x630)
 120 #define AR9170_MAC_REG_MANDATORY_RATE           (AR9170_MAC_REG_BASE + 0x634)
 121 #define AR9170_MAC_REG_RTS_CTS_RATE             (AR9170_MAC_REG_BASE + 0x638)
 122 #define AR9170_MAC_REG_BACKOFF_PROTECT          (AR9170_MAC_REG_BASE + 0x63c)
 123 #define AR9170_MAC_REG_RX_THRESHOLD             (AR9170_MAC_REG_BASE + 0x640)
 124 #define AR9170_MAC_REG_RX_PE_DELAY              (AR9170_MAC_REG_BASE + 0x64C)
 125
 126 #define AR9170_MAC_REG_DYNAMIC_SIFS_ACK         (AR9170_MAC_REG_BASE + 0x658)
 127 #define AR9170_MAC_REG_SNIFFER                  (AR9170_MAC_REG_BASE + 0x674)
 128 #define         AR9170_MAC_REG_SNIFFER_ENABLE_PROMISC   BIT(0)
 129 #define         AR9170_MAC_REG_SNIFFER_DEFAULTS         0x02000000
 130 #define AR9170_MAC_REG_ENCRYPTION               (AR9170_MAC_REG_BASE + 0x678)
 131 #define         AR9170_MAC_REG_ENCRYPTION_RX_SOFTWARE   BIT(3)
 132 #define         AR9170_MAC_REG_ENCRYPTION_DEFAULTS      0x70
 133
 134 #define AR9170_MAC_REG_MISC_680                 (AR9170_MAC_REG_BASE + 0x680)
 135 #define AR9170_MAC_REG_TX_UNDERRUN              (AR9170_MAC_REG_BASE + 0x688)
 136
 137 #define AR9170_MAC_REG_FRAMETYPE_FILTER         (AR9170_MAC_REG_BASE + 0x68c)
 138 #define         AR9170_MAC_REG_FTF_ASSOC_REQ            BIT(0)
 139 #define         AR9170_MAC_REG_FTF_ASSOC_RESP           BIT(1)
 140 #define         AR9170_MAC_REG_FTF_REASSOC_REQ          BIT(2)
 141 #define         AR9170_MAC_REG_FTF_REASSOC_RESP         BIT(3)
 142 #define         AR9170_MAC_REG_FTF_PRB_REQ              BIT(4)
 143 #define         AR9170_MAC_REG_FTF_PRB_RESP             BIT(5)
 144 #define         AR9170_MAC_REG_FTF_BIT6                 BIT(6)
 145 #define         AR9170_MAC_REG_FTF_BIT7                 BIT(7)
 146 #define         AR9170_MAC_REG_FTF_BEACON               BIT(8)
 147 #define         AR9170_MAC_REG_FTF_ATIM                 BIT(9)
 148 #define         AR9170_MAC_REG_FTF_DEASSOC              BIT(10)
 149 #define         AR9170_MAC_REG_FTF_AUTH                 BIT(11)
 150 #define         AR9170_MAC_REG_FTF_DEAUTH               BIT(12)
 151 #define         AR9170_MAC_REG_FTF_BIT13                BIT(13)
 152 #define         AR9170_MAC_REG_FTF_BIT14                BIT(14)
 153 #define         AR9170_MAC_REG_FTF_BIT15                BIT(15)
 154 #define         AR9170_MAC_REG_FTF_BAR                  BIT(24)
 155 #define         AR9170_MAC_REG_FTF_BA                   BIT(25)
 156 #define         AR9170_MAC_REG_FTF_PSPOLL               BIT(26)
 157 #define         AR9170_MAC_REG_FTF_RTS                  BIT(27)
 158 #define         AR9170_MAC_REG_FTF_CTS                  BIT(28)
 159 #define         AR9170_MAC_REG_FTF_ACK                  BIT(29)
 160 #define         AR9170_MAC_REG_FTF_CFE                  BIT(30)
 161 #define         AR9170_MAC_REG_FTF_CFE_ACK              BIT(31)
 162 #define         AR9170_MAC_REG_FTF_DEFAULTS             0x0700ffff
 163 #define         AR9170_MAC_REG_FTF_MONITOR              0xfd00ffff
 164
 165 #define AR9170_MAC_REG_RX_TOTAL                 (AR9170_MAC_REG_BASE + 0x6A0)
 166 #define AR9170_MAC_REG_RX_CRC32                 (AR9170_MAC_REG_BASE + 0x6A4)
 167 #define AR9170_MAC_REG_RX_CRC16                 (AR9170_MAC_REG_BASE + 0x6A8)
 168 #define AR9170_MAC_REG_RX_ERR_DECRYPTION_UNI    (AR9170_MAC_REG_BASE + 0x6AC)
 169 #define AR9170_MAC_REG_RX_OVERRUN               (AR9170_MAC_REG_BASE + 0x6B0)
 170 #define AR9170_MAC_REG_RX_ERR_DECRYPTION_MUL    (AR9170_MAC_REG_BASE + 0x6BC)
 171 #define AR9170_MAC_REG_TX_RETRY                 (AR9170_MAC_REG_BASE + 0x6CC)
 172 #define AR9170_MAC_REG_TX_TOTAL                 (AR9170_MAC_REG_BASE + 0x6F4)
 173
 174
 175 #define AR9170_MAC_REG_ACK_EXTENSION            (AR9170_MAC_REG_BASE + 0x690)
 176 #define AR9170_MAC_REG_EIFS_AND_SIFS            (AR9170_MAC_REG_BASE + 0x698)
 177
 178 #define AR9170_MAC_REG_SLOT_TIME                (AR9170_MAC_REG_BASE + 0x6F0)
 179
 180 #define AR9170_MAC_REG_POWERMANAGEMENT          (AR9170_MAC_REG_BASE + 0x700)
 181 #define         AR9170_MAC_REG_POWERMGT_IBSS            0xe0
 182 #define         AR9170_MAC_REG_POWERMGT_AP              0xa1
 183 #define         AR9170_MAC_REG_POWERMGT_STA             0x2
 184 #define         AR9170_MAC_REG_POWERMGT_AP_WDS          0x3
 185 #define         AR9170_MAC_REG_POWERMGT_DEFAULTS        (0xf << 24)
 186
 187 #define AR9170_MAC_REG_ROLL_CALL_TBL_L          (AR9170_MAC_REG_BASE + 0x704)
 188 #define AR9170_MAC_REG_ROLL_CALL_TBL_H          (AR9170_MAC_REG_BASE + 0x708)
 189
 190 #define AR9170_MAC_REG_AC0_CW                   (AR9170_MAC_REG_BASE + 0xB00)
 191 #define AR9170_MAC_REG_AC1_CW                   (AR9170_MAC_REG_BASE + 0xB04)
 192 #define AR9170_MAC_REG_AC2_CW                   (AR9170_MAC_REG_BASE + 0xB08)
 193 #define AR9170_MAC_REG_AC3_CW                   (AR9170_MAC_REG_BASE + 0xB0C)
 194 #define AR9170_MAC_REG_AC4_CW                   (AR9170_MAC_REG_BASE + 0xB10)
 195 #define AR9170_MAC_REG_AC1_AC0_AIFS             (AR9170_MAC_REG_BASE + 0xB14)
 196 #define AR9170_MAC_REG_AC3_AC2_AIFS             (AR9170_MAC_REG_BASE + 0xB18)
 197
 198 #define AR9170_MAC_REG_RETRY_MAX                (AR9170_MAC_REG_BASE + 0xB28)
 199
 200 #define AR9170_MAC_REG_FCS_SELECT               (AR9170_MAC_REG_BASE + 0xBB0)
 201 #define         AR9170_MAC_FCS_SWFCS            0x1
 202 #define         AR9170_MAC_FCS_FIFO_PROT        0x4
 203
 204
 205 #define AR9170_MAC_REG_TXOP_NOT_ENOUGH_IND      (AR9170_MAC_REG_BASE + 0xB30)
 206
 207 #define AR9170_MAC_REG_AC1_AC0_TXOP             (AR9170_MAC_REG_BASE + 0xB44)
 208 #define AR9170_MAC_REG_AC3_AC2_TXOP             (AR9170_MAC_REG_BASE + 0xB48)
 209
 210 #define AR9170_MAC_REG_AMPDU_FACTOR             (AR9170_MAC_REG_BASE + 0xB9C)
 211 #define AR9170_MAC_REG_AMPDU_DENSITY            (AR9170_MAC_REG_BASE + 0xBA0)
 212
 213 #define AR9170_MAC_REG_ACK_TABLE                (AR9170_MAC_REG_BASE + 0xC00)
 214 #define AR9170_MAC_REG_AMPDU_RX_THRESH          (AR9170_MAC_REG_BASE + 0xC50)
 215
 216 #define AR9170_MAC_REG_TXRX_MPI                 (AR9170_MAC_REG_BASE + 0xD7C)
 217 #define         AR9170_MAC_TXRX_MPI_TX_MPI_MASK 0x0000000f
 218 #define         AR9170_MAC_TXRX_MPI_TX_TO_MASK  0x0000fff0
 219 #define         AR9170_MAC_TXRX_MPI_RX_MPI_MASK 0x000f0000
 220 #define         AR9170_MAC_TXRX_MPI_RX_TO_MASK  0xfff00000
 221
 222 #define AR9170_MAC_REG_BCN_ADDR                 (AR9170_MAC_REG_BASE + 0xD84)
 223 #define AR9170_MAC_REG_BCN_LENGTH               (AR9170_MAC_REG_BASE + 0xD88)
 224 #define AR9170_MAC_REG_BCN_PLCP                 (AR9170_MAC_REG_BASE + 0xD90)
 225 #define AR9170_MAC_REG_BCN_CTRL                 (AR9170_MAC_REG_BASE + 0xD94)
 226 #define AR9170_MAC_REG_BCN_HT1                  (AR9170_MAC_REG_BASE + 0xDA0)
 227 #define AR9170_MAC_REG_BCN_HT2                  (AR9170_MAC_REG_BASE + 0xDA4)
 228
 229
 230 #define AR9170_PWR_REG_BASE                     0x1D4000
 231
 232 #define AR9170_PWR_REG_CLOCK_SEL                (AR9170_PWR_REG_BASE + 0x008)
 233 #define         AR9170_PWR_CLK_AHB_40MHZ        0
 234 #define         AR9170_PWR_CLK_AHB_20_22MHZ     1
 235 #define         AR9170_PWR_CLK_AHB_40_44MHZ     2
 236 #define         AR9170_PWR_CLK_AHB_80_88MHZ     3
 237 #define         AR9170_PWR_CLK_DAC_160_INV_DLY  0x70
 238
 239
 240 /* put beacon here in memory */
 241 #define AR9170_BEACON_BUFFER_ADDRESS            0x117900
 242
 243
 244 struct ar9170_tx_control {
 245         __le16 length;
 246         __le16 mac_control;
 247         __le32 phy_control;
 248         u8 frame_data[0];
 249 } __packed;
 250
 251 /* these are either-or */
 252 #define AR9170_TX_MAC_PROT_RTS                  0x0001
 253 #define AR9170_TX_MAC_PROT_CTS                  0x0002
 254
 255 #define AR9170_TX_MAC_NO_ACK                    0x0004
 256 /* if unset, MAC will only do SIFS space before frame */
 257 #define AR9170_TX_MAC_BACKOFF                   0x0008
 258 #define AR9170_TX_MAC_BURST                     0x0010
 259 #define AR9170_TX_MAC_AGGR                      0x0020
 260
 261 /* encryption is a two-bit field */
 262 #define AR9170_TX_MAC_ENCR_NONE                 0x0000
 263 #define AR9170_TX_MAC_ENCR_RC4                  0x0040
 264 #define AR9170_TX_MAC_ENCR_CENC                 0x0080
 265 #define AR9170_TX_MAC_ENCR_AES                  0x00c0
 266
 267 #define AR9170_TX_MAC_MMIC                      0x0100
 268 #define AR9170_TX_MAC_HW_DURATION               0x0200
 269 #define AR9170_TX_MAC_QOS_SHIFT                 10
 270 #define AR9170_TX_MAC_QOS_MASK                  (3 << AR9170_TX_MAC_QOS_SHIFT)
 271 #define AR9170_TX_MAC_AGGR_QOS_BIT1             0x0400
 272 #define AR9170_TX_MAC_AGGR_QOS_BIT2             0x0800
 273 #define AR9170_TX_MAC_DISABLE_TXOP              0x1000
 274 #define AR9170_TX_MAC_TXOP_RIFS                 0x2000
 275 #define AR9170_TX_MAC_IMM_AMPDU                 0x4000
 276 #define AR9170_TX_MAC_RATE_PROBE                0x8000
 277
 278 /* either-or */
 279 #define AR9170_TX_PHY_MOD_MASK                  0x00000003
 280 #define AR9170_TX_PHY_MOD_CCK                   0x00000000
 281 #define AR9170_TX_PHY_MOD_OFDM                  0x00000001
 282 #define AR9170_TX_PHY_MOD_HT                    0x00000002
 283
 284 /* depends on modulation */
 285 #define AR9170_TX_PHY_SHORT_PREAMBLE            0x00000004
 286 #define AR9170_TX_PHY_GREENFIELD                0x00000004
 287
 288 #define AR9170_TX_PHY_BW_SHIFT                  3
 289 #define AR9170_TX_PHY_BW_MASK                   (3 << AR9170_TX_PHY_BW_SHIFT)
 290 #define AR9170_TX_PHY_BW_20MHZ                  0
 291 #define AR9170_TX_PHY_BW_40MHZ                  2
 292 #define AR9170_TX_PHY_BW_40MHZ_DUP              3
 293
 294 #define AR9170_TX_PHY_TX_HEAVY_CLIP_SHIFT       6
 295 #define AR9170_TX_PHY_TX_HEAVY_CLIP_MASK        (7 << AR9170_TX_PHY_TX_HEAVY_CLIP_SHIFT)
 296
 297 #define AR9170_TX_PHY_TX_PWR_SHIFT              9
 298 #define AR9170_TX_PHY_TX_PWR_MASK               (0x3f << AR9170_TX_PHY_TX_PWR_SHIFT)
 299
 300 /* not part of the hw-spec */
 301 #define AR9170_TX_PHY_QOS_SHIFT                 25
 302 #define AR9170_TX_PHY_QOS_MASK                  (3 << AR9170_TX_PHY_QOS_SHIFT)
 303
 304 #define AR9170_TX_PHY_TXCHAIN_SHIFT             15
 305 #define AR9170_TX_PHY_TXCHAIN_MASK              (7 << AR9170_TX_PHY_TXCHAIN_SHIFT)
 306 #define AR9170_TX_PHY_TXCHAIN_1                 1
 307 /* use for cck, ofdm 6/9/12/18/24 and HT if capable */
 308 #define AR9170_TX_PHY_TXCHAIN_2                 5
 309
 310 #define AR9170_TX_PHY_MCS_SHIFT                 18
 311 #define AR9170_TX_PHY_MCS_MASK                  (0x7f << AR9170_TX_PHY_MCS_SHIFT)
 312
 313 #define AR9170_TX_PHY_SHORT_GI                  0x80000000
 314
 315 #define AR5416_MAX_RATE_POWER                   63
 316
 317 struct ar9170_rx_head {
 318         u8 plcp[12];
 319 } __packed;
 320
 321 struct ar9170_rx_phystatus {
 322         union {
 323                 struct {
 324                         u8 rssi_ant0, rssi_ant1, rssi_ant2,
 325                            rssi_ant0x, rssi_ant1x, rssi_ant2x,
 326                            rssi_combined;
 327                 } __packed;
 328                 u8 rssi[7];
 329         } __packed;
 330
 331         u8 evm_stream0[6], evm_stream1[6];
 332         u8 phy_err;
 333 } __packed;
 334
 335 struct ar9170_rx_macstatus {
 336         u8 SAidx, DAidx;
 337         u8 error;
 338         u8 status;
 339 } __packed;
 340
 341 #define AR9170_ENC_ALG_NONE                     0x0
 342 #define AR9170_ENC_ALG_WEP64                    0x1
 343 #define AR9170_ENC_ALG_TKIP                     0x2
 344 #define AR9170_ENC_ALG_AESCCMP                  0x4
 345 #define AR9170_ENC_ALG_WEP128                   0x5
 346 #define AR9170_ENC_ALG_WEP256                   0x6
 347 #define AR9170_ENC_ALG_CENC                     0x7
 348
 349 #define AR9170_RX_ENC_SOFTWARE                  0x8
 350
 351 static inline u8 ar9170_get_decrypt_type(struct ar9170_rx_macstatus *t)
 352 {
 353         return (t->SAidx & 0xc0) >> 4 |
 354                (t->DAidx & 0xc0) >> 6;
 355 }
 356
 357 #define AR9170_RX_STATUS_MODULATION_MASK        0x03
 358 #define AR9170_RX_STATUS_MODULATION_CCK         0x00
 359 #define AR9170_RX_STATUS_MODULATION_OFDM        0x01
 360 #define AR9170_RX_STATUS_MODULATION_HT          0x02
 361 #define AR9170_RX_STATUS_MODULATION_DUPOFDM     0x03
 362
 363 /* depends on modulation */
 364 #define AR9170_RX_STATUS_SHORT_PREAMBLE         0x08
 365 #define AR9170_RX_STATUS_GREENFIELD             0x08
 366
 367 #define AR9170_RX_STATUS_MPDU_MASK              0x30
 368 #define AR9170_RX_STATUS_MPDU_SINGLE            0x00
 369 #define AR9170_RX_STATUS_MPDU_FIRST             0x20
 370 #define AR9170_RX_STATUS_MPDU_MIDDLE            0x30
 371 #define AR9170_RX_STATUS_MPDU_LAST              0x10
 372
 373 #define AR9170_RX_ERROR_RXTO                    0x01
 374 #define AR9170_RX_ERROR_OVERRUN                 0x02
 375 #define AR9170_RX_ERROR_DECRYPT                 0x04
 376 #define AR9170_RX_ERROR_FCS                     0x08
 377 #define AR9170_RX_ERROR_WRONG_RA                0x10
 378 #define AR9170_RX_ERROR_PLCP                    0x20
 379 #define AR9170_RX_ERROR_MMIC                    0x40
 380 #define AR9170_RX_ERROR_FATAL                   0x80
 381
 382 struct ar9170_cmd_tx_status {
 383         u8 dst[ETH_ALEN];
 384         __le32 rate;
 385         __le16 status;
 386 } __packed;
 387
 388 #define AR9170_TX_STATUS_COMPLETE               0x00
 389 #define AR9170_TX_STATUS_RETRY                  0x01
 390 #define AR9170_TX_STATUS_FAILED                 0x02
 391
 392 struct ar9170_cmd_ba_failed_count {
 393         __le16 failed;
 394         __le16 rate;
 395 } __packed;
 396
 397 struct ar9170_cmd_response {
 398         u8 flag;
 399         u8 type;
 400         __le16 padding;
 401
 402         union {
 403                 struct ar9170_cmd_tx_status             tx_status;
 404                 struct ar9170_cmd_ba_failed_count       ba_fail_cnt;
 405                 u8 data[0];
 406         };
 407 } __packed;
 408
 409 /* QoS */
 410
 411 /* mac80211 queue to HW/FW map */
 412 static const u8 ar9170_qos_hwmap[4] = { 3, 2, 0, 1 };
 413
 414 /* HW/FW queue to mac80211 map */
 415 static const u8 ar9170_qos_mac80211map[4] = { 2, 3, 1, 0 };
 416
 417 enum ar9170_txq {
 418         AR9170_TXQ_BE,
 419         AR9170_TXQ_BK,
 420         AR9170_TXQ_VI,
 421         AR9170_TXQ_VO,
 422
 423         __AR9170_NUM_TXQ,
 424 };
 425
 426 #define AR9170_TXQ_DEPTH        32
 427 #define AR9170_TX_MAX_PENDING   128
 428 #define AR9170_RX_STREAM_MAX_SIZE 65535
 429
 430 #endif /* __AR9170_HW_H */