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proc: use seq_puts()/seq_putc() where possible
[linux-2.6/next.git] / drivers / net / wireless / ath / ath5k / reset.c
blob84206898f77d89daa5821a9afeece34b275f3f67
1 /*
2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
5 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
7 *
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 *
20 */
21
22 /*****************************\
23 Reset functions and helpers
24 \*****************************/
25
26 #include <asm/unaligned.h>
27
28 #include <linux/pci.h> /* To determine if a card is pci-e */
29 #include <linux/log2.h>
30 #include <linux/platform_device.h>
31 #include "ath5k.h"
32 #include "reg.h"
33 #include "base.h"
34 #include "debug.h"
35
36
37 /******************\
38 * Helper functions *
39 \******************/
40
41 /*
42 * Check if a register write has been completed
43 */
44 int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
45 bool is_set)
46 {
47 int i;
48 u32 data;
49
50 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
51 data = ath5k_hw_reg_read(ah, reg);
52 if (is_set && (data & flag))
53 break;
54 else if ((data & flag) == val)
55 break;
56 udelay(15);
57 }
58
59 return (i <= 0) ? -EAGAIN : 0;
60 }
61
62
63 /*************************\
64 * Clock related functions *
65 \*************************/
66
67 /**
68 * ath5k_hw_htoclock - Translate usec to hw clock units
69 *
70 * @ah: The &struct ath5k_hw
71 * @usec: value in microseconds
72 */
73 unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec)
74 {
75 struct ath_common *common = ath5k_hw_common(ah);
76 return usec * common->clockrate;
77 }
78
79 /**
80 * ath5k_hw_clocktoh - Translate hw clock units to usec
81 * @clock: value in hw clock units
82 */
83 unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock)
84 {
85 struct ath_common *common = ath5k_hw_common(ah);
86 return clock / common->clockrate;
87 }
88
89 /**
90 * ath5k_hw_init_core_clock - Initialize core clock
91 *
92 * @ah The &struct ath5k_hw
93 *
94 * Initialize core clock parameters (usec, usec32, latencies etc).
95 */
96 static void ath5k_hw_init_core_clock(struct ath5k_hw *ah)
97 {
98 struct ieee80211_channel *channel = ah->ah_current_channel;
99 struct ath_common *common = ath5k_hw_common(ah);
100 u32 usec_reg, txlat, rxlat, usec, clock, sclock, txf2txs;
101
102 /*
103 * Set core clock frequency
104 */
105 if (channel->hw_value & CHANNEL_5GHZ)
106 clock = 40; /* 802.11a */
107 else if (channel->hw_value & CHANNEL_CCK)
108 clock = 22; /* 802.11b */
109 else
110 clock = 44; /* 802.11g */
111
112 /* Use clock multiplier for non-default
113 * bwmode */
114 switch (ah->ah_bwmode) {
115 case AR5K_BWMODE_40MHZ:
116 clock *= 2;
117 break;
118 case AR5K_BWMODE_10MHZ:
119 clock /= 2;
120 break;
121 case AR5K_BWMODE_5MHZ:
122 clock /= 4;
123 break;
124 default:
125 break;
126 }
127
128 common->clockrate = clock;
129
130 /*
131 * Set USEC parameters
132 */
133 /* Set USEC counter on PCU*/
134 usec = clock - 1;
135 usec = AR5K_REG_SM(usec, AR5K_USEC_1);
136
137 /* Set usec duration on DCU */
138 if (ah->ah_version != AR5K_AR5210)
139 AR5K_REG_WRITE_BITS(ah, AR5K_DCU_GBL_IFS_MISC,
140 AR5K_DCU_GBL_IFS_MISC_USEC_DUR,
141 clock);
142
143 /* Set 32MHz USEC counter */
144 if ((ah->ah_radio == AR5K_RF5112) ||
145 (ah->ah_radio == AR5K_RF5413) ||
146 (ah->ah_radio == AR5K_RF2316) ||
147 (ah->ah_radio == AR5K_RF2317))
148 /* Remain on 40MHz clock ? */
149 sclock = 40 - 1;
150 else
151 sclock = 32 - 1;
152 sclock = AR5K_REG_SM(sclock, AR5K_USEC_32);
153
154 /*
155 * Set tx/rx latencies
156 */
157 usec_reg = ath5k_hw_reg_read(ah, AR5K_USEC_5211);
158 txlat = AR5K_REG_MS(usec_reg, AR5K_USEC_TX_LATENCY_5211);
159 rxlat = AR5K_REG_MS(usec_reg, AR5K_USEC_RX_LATENCY_5211);
160
161 /*
162 * 5210 initvals don't include usec settings
163 * so we need to use magic values here for
164 * tx/rx latencies
165 */
166 if (ah->ah_version == AR5K_AR5210) {
167 /* same for turbo */
168 txlat = AR5K_INIT_TX_LATENCY_5210;
169 rxlat = AR5K_INIT_RX_LATENCY_5210;
170 }
171
172 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
173 /* 5311 has different tx/rx latency masks
174 * from 5211, since we deal 5311 the same
175 * as 5211 when setting initvals, shift
176 * values here to their proper locations
177 *
178 * Note: Initvals indicate tx/rx/ latencies
179 * are the same for turbo mode */
180 txlat = AR5K_REG_SM(txlat, AR5K_USEC_TX_LATENCY_5210);
181 rxlat = AR5K_REG_SM(rxlat, AR5K_USEC_RX_LATENCY_5210);
182 } else
183 switch (ah->ah_bwmode) {
184 case AR5K_BWMODE_10MHZ:
185 txlat = AR5K_REG_SM(txlat * 2,
186 AR5K_USEC_TX_LATENCY_5211);
187 rxlat = AR5K_REG_SM(AR5K_INIT_RX_LAT_MAX,
188 AR5K_USEC_RX_LATENCY_5211);
189 txf2txs = AR5K_INIT_TXF2TXD_START_DELAY_10MHZ;
190 break;
191 case AR5K_BWMODE_5MHZ:
192 txlat = AR5K_REG_SM(txlat * 4,
193 AR5K_USEC_TX_LATENCY_5211);
194 rxlat = AR5K_REG_SM(AR5K_INIT_RX_LAT_MAX,
195 AR5K_USEC_RX_LATENCY_5211);
196 txf2txs = AR5K_INIT_TXF2TXD_START_DELAY_5MHZ;
197 break;
198 case AR5K_BWMODE_40MHZ:
199 txlat = AR5K_INIT_TX_LAT_MIN;
200 rxlat = AR5K_REG_SM(rxlat / 2,
201 AR5K_USEC_RX_LATENCY_5211);
202 txf2txs = AR5K_INIT_TXF2TXD_START_DEFAULT;
203 break;
204 default:
205 break;
206 }
207
208 usec_reg = (usec | sclock | txlat | rxlat);
209 ath5k_hw_reg_write(ah, usec_reg, AR5K_USEC);
210
211 /* On 5112 set tx frane to tx data start delay */
212 if (ah->ah_radio == AR5K_RF5112) {
213 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL2,
214 AR5K_PHY_RF_CTL2_TXF2TXD_START,
215 txf2txs);
216 }
217 }
218
219 /*
220 * If there is an external 32KHz crystal available, use it
221 * as ref. clock instead of 32/40MHz clock and baseband clocks
222 * to save power during sleep or restore normal 32/40MHz
223 * operation.
224 *
225 * XXX: When operating on 32KHz certain PHY registers (27 - 31,
226 * 123 - 127) require delay on access.
227 */
228 static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable)
229 {
230 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
231 u32 scal, spending;
232
233 /* Only set 32KHz settings if we have an external
234 * 32KHz crystal present */
235 if ((AR5K_EEPROM_HAS32KHZCRYSTAL(ee->ee_misc1) ||
236 AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(ee->ee_misc1)) &&
237 enable) {
238
239 /* 1 usec/cycle */
240 AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, 1);
241 /* Set up tsf increment on each cycle */
242 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 61);
243
244 /* Set baseband sleep control registers
245 * and sleep control rate */
246 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
247
248 if ((ah->ah_radio == AR5K_RF5112) ||
249 (ah->ah_radio == AR5K_RF5413) ||
250 (ah->ah_radio == AR5K_RF2316) ||
251 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
252 spending = 0x14;
253 else
254 spending = 0x18;
255 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
256
257 if ((ah->ah_radio == AR5K_RF5112) ||
258 (ah->ah_radio == AR5K_RF5413) ||
259 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
260 ath5k_hw_reg_write(ah, 0x26, AR5K_PHY_SLMT);
261 ath5k_hw_reg_write(ah, 0x0d, AR5K_PHY_SCAL);
262 ath5k_hw_reg_write(ah, 0x07, AR5K_PHY_SCLOCK);
263 ath5k_hw_reg_write(ah, 0x3f, AR5K_PHY_SDELAY);
264 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
265 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x02);
266 } else {
267 ath5k_hw_reg_write(ah, 0x0a, AR5K_PHY_SLMT);
268 ath5k_hw_reg_write(ah, 0x0c, AR5K_PHY_SCAL);
269 ath5k_hw_reg_write(ah, 0x03, AR5K_PHY_SCLOCK);
270 ath5k_hw_reg_write(ah, 0x20, AR5K_PHY_SDELAY);
271 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
272 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x03);
273 }
274
275 /* Enable sleep clock operation */
276 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG,
277 AR5K_PCICFG_SLEEP_CLOCK_EN);
278
279 } else {
280
281 /* Disable sleep clock operation and
282 * restore default parameters */
283 AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG,
284 AR5K_PCICFG_SLEEP_CLOCK_EN);
285
286 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
287 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0);
288
289 /* Set DAC/ADC delays */
290 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
291 ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT);
292
293 if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))
294 scal = AR5K_PHY_SCAL_32MHZ_2417;
295 else if (ee->ee_is_hb63)
296 scal = AR5K_PHY_SCAL_32MHZ_HB63;
297 else
298 scal = AR5K_PHY_SCAL_32MHZ;
299 ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL);
300
301 ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK);
302 ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY);
303
304 if ((ah->ah_radio == AR5K_RF5112) ||
305 (ah->ah_radio == AR5K_RF5413) ||
306 (ah->ah_radio == AR5K_RF2316) ||
307 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
308 spending = 0x14;
309 else
310 spending = 0x18;
311 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
312
313 /* Set up tsf increment on each cycle */
314 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 1);
315 }
316 }
317
318
319 /*********************\
320 * Reset/Sleep control *
321 \*********************/
322
323 /*
324 * Reset chipset
325 */
326 static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
327 {
328 int ret;
329 u32 mask = val ? val : ~0U;
330
331 /* Read-and-clear RX Descriptor Pointer*/
332 ath5k_hw_reg_read(ah, AR5K_RXDP);
333
334 /*
335 * Reset the device and wait until success
336 */
337 ath5k_hw_reg_write(ah, val, AR5K_RESET_CTL);
338
339 /* Wait at least 128 PCI clocks */
340 udelay(15);
341
342 if (ah->ah_version == AR5K_AR5210) {
343 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
344 | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
345 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
346 | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
347 } else {
348 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
349 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
350 }
351
352 ret = ath5k_hw_register_timeout(ah, AR5K_RESET_CTL, mask, val, false);
353
354 /*
355 * Reset configuration register (for hw byte-swap). Note that this
356 * is only set for big endian. We do the necessary magic in
357 * AR5K_INIT_CFG.
358 */
359 if ((val & AR5K_RESET_CTL_PCU) == 0)
360 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
361
362 return ret;
363 }
364
365 /*
366 * Reset AHB chipset
367 * AR5K_RESET_CTL_PCU flag resets WMAC
368 * AR5K_RESET_CTL_BASEBAND flag resets WBB
369 */
370 static int ath5k_hw_wisoc_reset(struct ath5k_hw *ah, u32 flags)
371 {
372 u32 mask = flags ? flags : ~0U;
373 volatile u32 *reg;
374 u32 regval;
375 u32 val = 0;
376
377 /* ah->ah_mac_srev is not available at this point yet */
378 if (ah->ah_sc->devid >= AR5K_SREV_AR2315_R6) {
379 reg = (u32 *) AR5K_AR2315_RESET;
380 if (mask & AR5K_RESET_CTL_PCU)
381 val |= AR5K_AR2315_RESET_WMAC;
382 if (mask & AR5K_RESET_CTL_BASEBAND)
383 val |= AR5K_AR2315_RESET_BB_WARM;
384 } else {
385 reg = (u32 *) AR5K_AR5312_RESET;
386 if (to_platform_device(ah->ah_sc->dev)->id == 0) {
387 if (mask & AR5K_RESET_CTL_PCU)
388 val |= AR5K_AR5312_RESET_WMAC0;
389 if (mask & AR5K_RESET_CTL_BASEBAND)
390 val |= AR5K_AR5312_RESET_BB0_COLD |
391 AR5K_AR5312_RESET_BB0_WARM;
392 } else {
393 if (mask & AR5K_RESET_CTL_PCU)
394 val |= AR5K_AR5312_RESET_WMAC1;
395 if (mask & AR5K_RESET_CTL_BASEBAND)
396 val |= AR5K_AR5312_RESET_BB1_COLD |
397 AR5K_AR5312_RESET_BB1_WARM;
398 }
399 }
400
401 /* Put BB/MAC into reset */
402 regval = __raw_readl(reg);
403 __raw_writel(regval | val, reg);
404 regval = __raw_readl(reg);
405 udelay(100);
406
407 /* Bring BB/MAC out of reset */
408 __raw_writel(regval & ~val, reg);
409 regval = __raw_readl(reg);
410
411 /*
412 * Reset configuration register (for hw byte-swap). Note that this
413 * is only set for big endian. We do the necessary magic in
414 * AR5K_INIT_CFG.
415 */
416 if ((flags & AR5K_RESET_CTL_PCU) == 0)
417 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
418
419 return 0;
420 }
421
422
423 /*
424 * Sleep control
425 */
426 static int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
427 bool set_chip, u16 sleep_duration)
428 {
429 unsigned int i;
430 u32 staid, data;
431
432 staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1);
433
434 switch (mode) {
435 case AR5K_PM_AUTO:
436 staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA;
437 /* fallthrough */
438 case AR5K_PM_NETWORK_SLEEP:
439 if (set_chip)
440 ath5k_hw_reg_write(ah,
441 AR5K_SLEEP_CTL_SLE_ALLOW |
442 sleep_duration,
443 AR5K_SLEEP_CTL);
444
445 staid |= AR5K_STA_ID1_PWR_SV;
446 break;
447
448 case AR5K_PM_FULL_SLEEP:
449 if (set_chip)
450 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_SLP,
451 AR5K_SLEEP_CTL);
452
453 staid |= AR5K_STA_ID1_PWR_SV;
454 break;
455
456 case AR5K_PM_AWAKE:
457
458 staid &= ~AR5K_STA_ID1_PWR_SV;
459
460 if (!set_chip)
461 goto commit;
462
463 data = ath5k_hw_reg_read(ah, AR5K_SLEEP_CTL);
464
465 /* If card is down we 'll get 0xffff... so we
466 * need to clean this up before we write the register
467 */
468 if (data & 0xffc00000)
469 data = 0;
470 else
471 /* Preserve sleep duration etc */
472 data = data & ~AR5K_SLEEP_CTL_SLE;
473
474 ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,
475 AR5K_SLEEP_CTL);
476 udelay(15);
477
478 for (i = 200; i > 0; i--) {
479 /* Check if the chip did wake up */
480 if ((ath5k_hw_reg_read(ah, AR5K_PCICFG) &
481 AR5K_PCICFG_SPWR_DN) == 0)
482 break;
483
484 /* Wait a bit and retry */
485 udelay(50);
486 ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,
487 AR5K_SLEEP_CTL);
488 }
489
490 /* Fail if the chip didn't wake up */
491 if (i == 0)
492 return -EIO;
493
494 break;
495
496 default:
497 return -EINVAL;
498 }
499
500 commit:
501 ath5k_hw_reg_write(ah, staid, AR5K_STA_ID1);
502
503 return 0;
504 }
505
506 /*
507 * Put device on hold
508 *
509 * Put MAC and Baseband on warm reset and
510 * keep that state (don't clean sleep control
511 * register). After this MAC and Baseband are
512 * disabled and a full reset is needed to come
513 * back. This way we save as much power as possible
514 * without putting the card on full sleep.
515 */
516 int ath5k_hw_on_hold(struct ath5k_hw *ah)
517 {
518 struct pci_dev *pdev = ah->ah_sc->pdev;
519 u32 bus_flags;
520 int ret;
521
522 if (ath5k_get_bus_type(ah) == ATH_AHB)
523 return 0;
524
525 /* Make sure device is awake */
526 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
527 if (ret) {
528 ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n");
529 return ret;
530 }
531
532 /*
533 * Put chipset on warm reset...
534 *
535 * Note: putting PCI core on warm reset on PCI-E cards
536 * results card to hang and always return 0xffff... so
537 * we ingore that flag for PCI-E cards. On PCI cards
538 * this flag gets cleared after 64 PCI clocks.
539 */
540 bus_flags = (pdev && pci_is_pcie(pdev)) ? 0 : AR5K_RESET_CTL_PCI;
541
542 if (ah->ah_version == AR5K_AR5210) {
543 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
544 AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
545 AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
546 mdelay(2);
547 } else {
548 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
549 AR5K_RESET_CTL_BASEBAND | bus_flags);
550 }
551
552 if (ret) {
553 ATH5K_ERR(ah->ah_sc, "failed to put device on warm reset\n");
554 return -EIO;
555 }
556
557 /* ...wakeup again!*/
558 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
559 if (ret) {
560 ATH5K_ERR(ah->ah_sc, "failed to put device on hold\n");
561 return ret;
562 }
563
564 return ret;
565 }
566
567 /*
568 * Bring up MAC + PHY Chips and program PLL
569 */
570 int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
571 {
572 struct pci_dev *pdev = ah->ah_sc->pdev;
573 u32 turbo, mode, clock, bus_flags;
574 int ret;
575
576 turbo = 0;
577 mode = 0;
578 clock = 0;
579
580 if ((ath5k_get_bus_type(ah) != ATH_AHB) || !initial) {
581 /* Wakeup the device */
582 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
583 if (ret) {
584 ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n");
585 return ret;
586 }
587 }
588
589 /*
590 * Put chipset on warm reset...
591 *
592 * Note: putting PCI core on warm reset on PCI-E cards
593 * results card to hang and always return 0xffff... so
594 * we ingore that flag for PCI-E cards. On PCI cards
595 * this flag gets cleared after 64 PCI clocks.
596 */
597 bus_flags = (pdev && pci_is_pcie(pdev)) ? 0 : AR5K_RESET_CTL_PCI;
598
599 if (ah->ah_version == AR5K_AR5210) {
600 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
601 AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
602 AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
603 mdelay(2);
604 } else {
605 if (ath5k_get_bus_type(ah) == ATH_AHB)
606 ret = ath5k_hw_wisoc_reset(ah, AR5K_RESET_CTL_PCU |
607 AR5K_RESET_CTL_BASEBAND);
608 else
609 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
610 AR5K_RESET_CTL_BASEBAND | bus_flags);
611 }
612
613 if (ret) {
614 ATH5K_ERR(ah->ah_sc, "failed to reset the MAC Chip\n");
615 return -EIO;
616 }
617
618 /* ...wakeup again!...*/
619 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
620 if (ret) {
621 ATH5K_ERR(ah->ah_sc, "failed to resume the MAC Chip\n");
622 return ret;
623 }
624
625 /* ...reset configuration regiter on Wisoc ...
626 * ...clear reset control register and pull device out of
627 * warm reset on others */
628 if (ath5k_get_bus_type(ah) == ATH_AHB)
629 ret = ath5k_hw_wisoc_reset(ah, 0);
630 else
631 ret = ath5k_hw_nic_reset(ah, 0);
632
633 if (ret) {
634 ATH5K_ERR(ah->ah_sc, "failed to warm reset the MAC Chip\n");
635 return -EIO;
636 }
637
638 /* On initialization skip PLL programming since we don't have
639 * a channel / mode set yet */
640 if (initial)
641 return 0;
642
643 if (ah->ah_version != AR5K_AR5210) {
644 /*
645 * Get channel mode flags
646 */
647
648 if (ah->ah_radio >= AR5K_RF5112) {
649 mode = AR5K_PHY_MODE_RAD_RF5112;
650 clock = AR5K_PHY_PLL_RF5112;
651 } else {
652 mode = AR5K_PHY_MODE_RAD_RF5111; /*Zero*/
653 clock = AR5K_PHY_PLL_RF5111; /*Zero*/
654 }
655
656 if (flags & CHANNEL_2GHZ) {
657 mode |= AR5K_PHY_MODE_FREQ_2GHZ;
658 clock |= AR5K_PHY_PLL_44MHZ;
659
660 if (flags & CHANNEL_CCK) {
661 mode |= AR5K_PHY_MODE_MOD_CCK;
662 } else if (flags & CHANNEL_OFDM) {
663 /* XXX Dynamic OFDM/CCK is not supported by the
664 * AR5211 so we set MOD_OFDM for plain g (no
665 * CCK headers) operation. We need to test
666 * this, 5211 might support ofdm-only g after
667 * all, there are also initial register values
668 * in the code for g mode (see initvals.c).
669 */
670 if (ah->ah_version == AR5K_AR5211)
671 mode |= AR5K_PHY_MODE_MOD_OFDM;
672 else
673 mode |= AR5K_PHY_MODE_MOD_DYN;
674 } else {
675 ATH5K_ERR(ah->ah_sc,
676 "invalid radio modulation mode\n");
677 return -EINVAL;
678 }
679 } else if (flags & CHANNEL_5GHZ) {
680 mode |= AR5K_PHY_MODE_FREQ_5GHZ;
681
682 /* Different PLL setting for 5413 */
683 if (ah->ah_radio == AR5K_RF5413)
684 clock = AR5K_PHY_PLL_40MHZ_5413;
685 else
686 clock |= AR5K_PHY_PLL_40MHZ;
687
688 if (flags & CHANNEL_OFDM)
689 mode |= AR5K_PHY_MODE_MOD_OFDM;
690 else {
691 ATH5K_ERR(ah->ah_sc,
692 "invalid radio modulation mode\n");
693 return -EINVAL;
694 }
695 } else {
696 ATH5K_ERR(ah->ah_sc, "invalid radio frequency mode\n");
697 return -EINVAL;
698 }
699
700 /*XXX: Can bwmode be used with dynamic mode ?
701 * (I don't think it supports 44MHz) */
702 /* On 2425 initvals TURBO_SHORT is not pressent */
703 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) {
704 turbo = AR5K_PHY_TURBO_MODE |
705 (ah->ah_radio == AR5K_RF2425) ? 0 :
706 AR5K_PHY_TURBO_SHORT;
707 } else if (ah->ah_bwmode != AR5K_BWMODE_DEFAULT) {
708 if (ah->ah_radio == AR5K_RF5413) {
709 mode |= (ah->ah_bwmode == AR5K_BWMODE_10MHZ) ?
710 AR5K_PHY_MODE_HALF_RATE :
711 AR5K_PHY_MODE_QUARTER_RATE;
712 } else if (ah->ah_version == AR5K_AR5212) {
713 clock |= (ah->ah_bwmode == AR5K_BWMODE_10MHZ) ?
714 AR5K_PHY_PLL_HALF_RATE :
715 AR5K_PHY_PLL_QUARTER_RATE;
716 }
717 }
718
719 } else { /* Reset the device */
720
721 /* ...enable Atheros turbo mode if requested */
722 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
723 ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE,
724 AR5K_PHY_TURBO);
725 }
726
727 if (ah->ah_version != AR5K_AR5210) {
728
729 /* ...update PLL if needed */
730 if (ath5k_hw_reg_read(ah, AR5K_PHY_PLL) != clock) {
731 ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL);
732 udelay(300);
733 }
734
735 /* ...set the PHY operating mode */
736 ath5k_hw_reg_write(ah, mode, AR5K_PHY_MODE);
737 ath5k_hw_reg_write(ah, turbo, AR5K_PHY_TURBO);
738 }
739
740 return 0;
741 }
742
743
744 /**************************************\
745 * Post-initvals register modifications *
746 \**************************************/
747
748 /* TODO: Half/Quarter rate */
749 static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
750 struct ieee80211_channel *channel)
751 {
752 if (ah->ah_version == AR5K_AR5212 &&
753 ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
754
755 /* Setup ADC control */
756 ath5k_hw_reg_write(ah,
757 (AR5K_REG_SM(2,
758 AR5K_PHY_ADC_CTL_INBUFGAIN_OFF) |
759 AR5K_REG_SM(2,
760 AR5K_PHY_ADC_CTL_INBUFGAIN_ON) |
761 AR5K_PHY_ADC_CTL_PWD_DAC_OFF |
762 AR5K_PHY_ADC_CTL_PWD_ADC_OFF),
763 AR5K_PHY_ADC_CTL);
764
765
766
767 /* Disable barker RSSI threshold */
768 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_DAG_CCK_CTL,
769 AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR);
770
771 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DAG_CCK_CTL,
772 AR5K_PHY_DAG_CCK_CTL_RSSI_THR, 2);
773
774 /* Set the mute mask */
775 ath5k_hw_reg_write(ah, 0x0000000f, AR5K_SEQ_MASK);
776 }
777
778 /* Clear PHY_BLUETOOTH to allow RX_CLEAR line debug */
779 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212B)
780 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BLUETOOTH);
781
782 /* Enable DCU double buffering */
783 if (ah->ah_phy_revision > AR5K_SREV_PHY_5212B)
784 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
785 AR5K_TXCFG_DCU_DBL_BUF_DIS);
786
787 /* Set fast ADC */
788 if ((ah->ah_radio == AR5K_RF5413) ||
789 (ah->ah_radio == AR5K_RF2317) ||
790 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
791 u32 fast_adc = true;
792
793 if (channel->center_freq == 2462 ||
794 channel->center_freq == 2467)
795 fast_adc = 0;
796
797 /* Only update if needed */
798 if (ath5k_hw_reg_read(ah, AR5K_PHY_FAST_ADC) != fast_adc)
799 ath5k_hw_reg_write(ah, fast_adc,
800 AR5K_PHY_FAST_ADC);
801 }
802
803 /* Fix for first revision of the RF5112 RF chipset */
804 if (ah->ah_radio == AR5K_RF5112 &&
805 ah->ah_radio_5ghz_revision <
806 AR5K_SREV_RAD_5112A) {
807 u32 data;
808 ath5k_hw_reg_write(ah, AR5K_PHY_CCKTXCTL_WORLD,
809 AR5K_PHY_CCKTXCTL);
810 if (channel->hw_value & CHANNEL_5GHZ)
811 data = 0xffb81020;
812 else
813 data = 0xffb80d20;
814 ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL);
815 }
816
817 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
818 /* Clear QCU/DCU clock gating register */
819 ath5k_hw_reg_write(ah, 0, AR5K_QCUDCU_CLKGT);
820 /* Set DAC/ADC delays */
821 ath5k_hw_reg_write(ah, AR5K_PHY_SCAL_32MHZ_5311,
822 AR5K_PHY_SCAL);
823 /* Enable PCU FIFO corruption ECO */
824 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211,
825 AR5K_DIAG_SW_ECO_ENABLE);
826 }
827
828 if (ah->ah_bwmode) {
829 /* Increase PHY switch and AGC settling time
830 * on turbo mode (ath5k_hw_commit_eeprom_settings
831 * will override settling time if available) */
832 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) {
833
834 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
835 AR5K_PHY_SETTLING_AGC,
836 AR5K_AGC_SETTLING_TURBO);
837
838 /* XXX: Initvals indicate we only increase
839 * switch time on AR5212, 5211 and 5210
840 * only change agc time (bug?) */
841 if (ah->ah_version == AR5K_AR5212)
842 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
843 AR5K_PHY_SETTLING_SWITCH,
844 AR5K_SWITCH_SETTLING_TURBO);
845
846 if (ah->ah_version == AR5K_AR5210) {
847 /* Set Frame Control Register */
848 ath5k_hw_reg_write(ah,
849 (AR5K_PHY_FRAME_CTL_INI |
850 AR5K_PHY_TURBO_MODE |
851 AR5K_PHY_TURBO_SHORT | 0x2020),
852 AR5K_PHY_FRAME_CTL_5210);
853 }
854 /* On 5413 PHY force window length for half/quarter rate*/
855 } else if ((ah->ah_mac_srev >= AR5K_SREV_AR5424) &&
856 (ah->ah_mac_srev <= AR5K_SREV_AR5414)) {
857 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL_5211,
858 AR5K_PHY_FRAME_CTL_WIN_LEN,
859 3);
860 }
861 } else if (ah->ah_version == AR5K_AR5210) {
862 /* Set Frame Control Register for normal operation */
863 ath5k_hw_reg_write(ah, (AR5K_PHY_FRAME_CTL_INI | 0x1020),
864 AR5K_PHY_FRAME_CTL_5210);
865 }
866 }
867
868 static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah,
869 struct ieee80211_channel *channel)
870 {
871 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
872 s16 cck_ofdm_pwr_delta;
873 u8 ee_mode;
874
875 /* TODO: Add support for AR5210 EEPROM */
876 if (ah->ah_version == AR5K_AR5210)
877 return;
878
879 ee_mode = ath5k_eeprom_mode_from_channel(channel);
880
881 /* Adjust power delta for channel 14 */
882 if (channel->center_freq == 2484)
883 cck_ofdm_pwr_delta =
884 ((ee->ee_cck_ofdm_power_delta -
885 ee->ee_scaled_cck_delta) * 2) / 10;
886 else
887 cck_ofdm_pwr_delta =
888 (ee->ee_cck_ofdm_power_delta * 2) / 10;
889
890 /* Set CCK to OFDM power delta on tx power
891 * adjustment register */
892 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
893 if (channel->hw_value == CHANNEL_G)
894 ath5k_hw_reg_write(ah,
895 AR5K_REG_SM((ee->ee_cck_ofdm_gain_delta * -1),
896 AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA) |
897 AR5K_REG_SM((cck_ofdm_pwr_delta * -1),
898 AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX),
899 AR5K_PHY_TX_PWR_ADJ);
900 else
901 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TX_PWR_ADJ);
902 } else {
903 /* For older revs we scale power on sw during tx power
904 * setup */
905 ah->ah_txpower.txp_cck_ofdm_pwr_delta = cck_ofdm_pwr_delta;
906 ah->ah_txpower.txp_cck_ofdm_gainf_delta =
907 ee->ee_cck_ofdm_gain_delta;
908 }
909
910 /* XXX: necessary here? is called from ath5k_hw_set_antenna_mode()
911 * too */
912 ath5k_hw_set_antenna_switch(ah, ee_mode);
913
914 /* Noise floor threshold */
915 ath5k_hw_reg_write(ah,
916 AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]),
917 AR5K_PHY_NFTHRES);
918
919 if ((ah->ah_bwmode == AR5K_BWMODE_40MHZ) &&
920 (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0)) {
921 /* Switch settling time (Turbo) */
922 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
923 AR5K_PHY_SETTLING_SWITCH,
924 ee->ee_switch_settling_turbo[ee_mode]);
925
926 /* Tx/Rx attenuation (Turbo) */
927 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN,
928 AR5K_PHY_GAIN_TXRX_ATTEN,
929 ee->ee_atn_tx_rx_turbo[ee_mode]);
930
931 /* ADC/PGA desired size (Turbo) */
932 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
933 AR5K_PHY_DESIRED_SIZE_ADC,
934 ee->ee_adc_desired_size_turbo[ee_mode]);
935
936 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
937 AR5K_PHY_DESIRED_SIZE_PGA,
938 ee->ee_pga_desired_size_turbo[ee_mode]);
939
940 /* Tx/Rx margin (Turbo) */
941 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
942 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
943 ee->ee_margin_tx_rx_turbo[ee_mode]);
944
945 } else {
946 /* Switch settling time */
947 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
948 AR5K_PHY_SETTLING_SWITCH,
949 ee->ee_switch_settling[ee_mode]);
950
951 /* Tx/Rx attenuation */
952 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN,
953 AR5K_PHY_GAIN_TXRX_ATTEN,
954 ee->ee_atn_tx_rx[ee_mode]);
955
956 /* ADC/PGA desired size */
957 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
958 AR5K_PHY_DESIRED_SIZE_ADC,
959 ee->ee_adc_desired_size[ee_mode]);
960
961 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
962 AR5K_PHY_DESIRED_SIZE_PGA,
963 ee->ee_pga_desired_size[ee_mode]);
964
965 /* Tx/Rx margin */
966 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
967 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
968 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
969 ee->ee_margin_tx_rx[ee_mode]);
970 }
971
972 /* XPA delays */
973 ath5k_hw_reg_write(ah,
974 (ee->ee_tx_end2xpa_disable[ee_mode] << 24) |
975 (ee->ee_tx_end2xpa_disable[ee_mode] << 16) |
976 (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) |
977 (ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY_RF_CTL4);
978
979 /* XLNA delay */
980 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL3,
981 AR5K_PHY_RF_CTL3_TXE2XLNA_ON,
982 ee->ee_tx_end2xlna_enable[ee_mode]);
983
984 /* Thresh64 (ANI) */
985 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_NF,
986 AR5K_PHY_NF_THRESH62,
987 ee->ee_thr_62[ee_mode]);
988
989 /* False detect backoff for channels
990 * that have spur noise. Write the new
991 * cyclic power RSSI threshold. */
992 if (ath5k_hw_chan_has_spur_noise(ah, channel))
993 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
994 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1,
995 AR5K_INIT_CYCRSSI_THR1 +
996 ee->ee_false_detect[ee_mode]);
997 else
998 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
999 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1,
1000 AR5K_INIT_CYCRSSI_THR1);
1001
1002 /* I/Q correction (set enable bit last to match HAL sources) */
1003 /* TODO: Per channel i/q infos ? */
1004 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
1005 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF,
1006 ee->ee_i_cal[ee_mode]);
1007 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF,
1008 ee->ee_q_cal[ee_mode]);
1009 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE);
1010 }
1011
1012 /* Heavy clipping -disable for now */
1013 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_1)
1014 ath5k_hw_reg_write(ah, 0, AR5K_PHY_HEAVY_CLIP_ENABLE);
1015 }
1016
1017
1018 /*********************\
1019 * Main reset function *
1020 \*********************/
1021
1022 int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1023 struct ieee80211_channel *channel, bool fast, bool skip_pcu)
1024 {
1025 u32 s_seq[10], s_led[3], tsf_up, tsf_lo;
1026 u8 mode;
1027 int i, ret;
1028
1029 tsf_up = 0;
1030 tsf_lo = 0;
1031 mode = 0;
1032
1033 /*
1034 * Sanity check for fast flag
1035 * Fast channel change only available
1036 * on AR2413/AR5413.
1037 */
1038 if (fast && (ah->ah_radio != AR5K_RF2413) &&
1039 (ah->ah_radio != AR5K_RF5413))
1040 fast = 0;
1041
1042 /* Disable sleep clock operation
1043 * to avoid register access delay on certain
1044 * PHY registers */
1045 if (ah->ah_version == AR5K_AR5212)
1046 ath5k_hw_set_sleep_clock(ah, false);
1047
1048 /*
1049 * Stop PCU
1050 */
1051 ath5k_hw_stop_rx_pcu(ah);
1052
1053 /*
1054 * Stop DMA
1055 *
1056 * Note: If DMA didn't stop continue
1057 * since only a reset will fix it.
1058 */
1059 ret = ath5k_hw_dma_stop(ah);
1060
1061 /* RF Bus grant won't work if we have pending
1062 * frames */
1063 if (ret && fast) {
1064 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_RESET,
1065 "DMA didn't stop, falling back to normal reset\n");
1066 fast = 0;
1067 /* Non fatal, just continue with
1068 * normal reset */
1069 ret = 0;
1070 }
1071
1072 switch (channel->hw_value & CHANNEL_MODES) {
1073 case CHANNEL_A:
1074 mode = AR5K_MODE_11A;
1075 break;
1076 case CHANNEL_G:
1077
1078 if (ah->ah_version <= AR5K_AR5211) {
1079 ATH5K_ERR(ah->ah_sc,
1080 "G mode not available on 5210/5211");
1081 return -EINVAL;
1082 }
1083
1084 mode = AR5K_MODE_11G;
1085 break;
1086 case CHANNEL_B:
1087
1088 if (ah->ah_version < AR5K_AR5211) {
1089 ATH5K_ERR(ah->ah_sc,
1090 "B mode not available on 5210");
1091 return -EINVAL;
1092 }
1093
1094 mode = AR5K_MODE_11B;
1095 break;
1096 case CHANNEL_XR:
1097 if (ah->ah_version == AR5K_AR5211) {
1098 ATH5K_ERR(ah->ah_sc,
1099 "XR mode not available on 5211");
1100 return -EINVAL;
1101 }
1102 mode = AR5K_MODE_XR;
1103 break;
1104 default:
1105 ATH5K_ERR(ah->ah_sc,
1106 "invalid channel: %d\n", channel->center_freq);
1107 return -EINVAL;
1108 }
1109
1110 /*
1111 * If driver requested fast channel change and DMA has stopped
1112 * go on. If it fails continue with a normal reset.
1113 */
1114 if (fast) {
1115 ret = ath5k_hw_phy_init(ah, channel, mode, true);
1116 if (ret) {
1117 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_RESET,
1118 "fast chan change failed, falling back to normal reset\n");
1119 /* Non fatal, can happen eg.
1120 * on mode change */
1121 ret = 0;
1122 } else
1123 return 0;
1124 }
1125
1126 /*
1127 * Save some registers before a reset
1128 */
1129 if (ah->ah_version != AR5K_AR5210) {
1130 /*
1131 * Save frame sequence count
1132 * For revs. after Oahu, only save
1133 * seq num for DCU 0 (Global seq num)
1134 */
1135 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
1136
1137 for (i = 0; i < 10; i++)
1138 s_seq[i] = ath5k_hw_reg_read(ah,
1139 AR5K_QUEUE_DCU_SEQNUM(i));
1140
1141 } else {
1142 s_seq[0] = ath5k_hw_reg_read(ah,
1143 AR5K_QUEUE_DCU_SEQNUM(0));
1144 }
1145
1146 /* TSF accelerates on AR5211 during reset
1147 * As a workaround save it here and restore
1148 * it later so that it's back in time after
1149 * reset. This way it'll get re-synced on the
1150 * next beacon without breaking ad-hoc.
1151 *
1152 * On AR5212 TSF is almost preserved across a
1153 * reset so it stays back in time anyway and
1154 * we don't have to save/restore it.
1155 *
1156 * XXX: Since this breaks power saving we have
1157 * to disable power saving until we receive the
1158 * next beacon, so we can resync beacon timers */
1159 if (ah->ah_version == AR5K_AR5211) {
1160 tsf_up = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
1161 tsf_lo = ath5k_hw_reg_read(ah, AR5K_TSF_L32);
1162 }
1163 }
1164
1165
1166 /*GPIOs*/
1167 s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) &
1168 AR5K_PCICFG_LEDSTATE;
1169 s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR);
1170 s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO);
1171
1172
1173 /*
1174 * Since we are going to write rf buffer
1175 * check if we have any pending gain_F
1176 * optimization settings
1177 */
1178 if (ah->ah_version == AR5K_AR5212 &&
1179 (ah->ah_radio <= AR5K_RF5112)) {
1180 if (!fast && ah->ah_rf_banks != NULL)
1181 ath5k_hw_gainf_calibrate(ah);
1182 }
1183
1184 /* Wakeup the device */
1185 ret = ath5k_hw_nic_wakeup(ah, channel->hw_value, false);
1186 if (ret)
1187 return ret;
1188
1189 /* PHY access enable */
1190 if (ah->ah_mac_srev >= AR5K_SREV_AR5211)
1191 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
1192 else
1193 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ | 0x40,
1194 AR5K_PHY(0));
1195
1196 /* Write initial settings */
1197 ret = ath5k_hw_write_initvals(ah, mode, skip_pcu);
1198 if (ret)
1199 return ret;
1200
1201 /* Initialize core clock settings */
1202 ath5k_hw_init_core_clock(ah);
1203
1204 /*
1205 * Tweak initval settings for revised
1206 * chipsets and add some more config
1207 * bits
1208 */
1209 ath5k_hw_tweak_initval_settings(ah, channel);
1210
1211 /* Commit values from EEPROM */
1212 ath5k_hw_commit_eeprom_settings(ah, channel);
1213
1214
1215 /*
1216 * Restore saved values
1217 */
1218
1219 /* Seqnum, TSF */
1220 if (ah->ah_version != AR5K_AR5210) {
1221 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
1222 for (i = 0; i < 10; i++)
1223 ath5k_hw_reg_write(ah, s_seq[i],
1224 AR5K_QUEUE_DCU_SEQNUM(i));
1225 } else {
1226 ath5k_hw_reg_write(ah, s_seq[0],
1227 AR5K_QUEUE_DCU_SEQNUM(0));
1228 }
1229
1230 if (ah->ah_version == AR5K_AR5211) {
1231 ath5k_hw_reg_write(ah, tsf_up, AR5K_TSF_U32);
1232 ath5k_hw_reg_write(ah, tsf_lo, AR5K_TSF_L32);
1233 }
1234 }
1235
1236 /* Ledstate */
1237 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, s_led[0]);
1238
1239 /* Gpio settings */
1240 ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR);
1241 ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO);
1242
1243 /*
1244 * Initialize PCU
1245 */
1246 ath5k_hw_pcu_init(ah, op_mode, mode);
1247
1248 /*
1249 * Initialize PHY
1250 */
1251 ret = ath5k_hw_phy_init(ah, channel, mode, false);
1252 if (ret) {
1253 ATH5K_ERR(ah->ah_sc,
1254 "failed to initialize PHY (%i) !\n", ret);
1255 return ret;
1256 }
1257
1258 /*
1259 * Configure QCUs/DCUs
1260 */
1261 ret = ath5k_hw_init_queues(ah);
1262 if (ret)
1263 return ret;
1264
1265
1266 /*
1267 * Initialize DMA/Interrupts
1268 */
1269 ath5k_hw_dma_init(ah);
1270
1271
1272 /* Enable 32KHz clock function for AR5212+ chips
1273 * Set clocks to 32KHz operation and use an
1274 * external 32KHz crystal when sleeping if one
1275 * exists */
1276 if (ah->ah_version == AR5K_AR5212 &&
1277 op_mode != NL80211_IFTYPE_AP)
1278 ath5k_hw_set_sleep_clock(ah, true);
1279
1280 /*
1281 * Disable beacons and reset the TSF
1282 */
1283 AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE);
1284 ath5k_hw_reset_tsf(ah);
1285 return 0;
1286 }
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