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Add linux-next specific files for 20110831
[linux-2.6/next.git] / arch / arm / mach-ixp2000 / core.c
blob24f0fe35f4adfca63249cf5a099db5234298087b
1 /*
2 * arch/arm/mach-ixp2000/core.c
3 *
4 * Common routines used by all IXP2400/2800 based platforms.
5 *
6 * Author: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2004 (C) MontaVista Software, Inc.
9 *
10 * Based on work Copyright (C) 2002-2003 Intel Corporation
11 *
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
15 */
16 #include <linux/gpio.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/spinlock.h>
20 #include <linux/sched.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
23 #include <linux/serial.h>
24 #include <linux/tty.h>
25 #include <linux/bitops.h>
26 #include <linux/serial_8250.h>
27 #include <linux/mm.h>
28 #include <linux/export.h>
29
30 #include <asm/types.h>
31 #include <asm/setup.h>
32 #include <asm/memory.h>
33 #include <mach/hardware.h>
34 #include <asm/irq.h>
35 #include <asm/system.h>
36 #include <asm/tlbflush.h>
37 #include <asm/pgtable.h>
38
39 #include <asm/mach/map.h>
40 #include <asm/mach/time.h>
41 #include <asm/mach/irq.h>
42
43 #include <mach/gpio-ixp2000.h>
44
45 static DEFINE_SPINLOCK(ixp2000_slowport_lock);
46 static unsigned long ixp2000_slowport_irq_flags;
47
48 /*************************************************************************
49 * Slowport access routines
50 *************************************************************************/
51 void ixp2000_acquire_slowport(struct slowport_cfg *new_cfg, struct slowport_cfg *old_cfg)
52 {
53 spin_lock_irqsave(&ixp2000_slowport_lock, ixp2000_slowport_irq_flags);
54
55 old_cfg->CCR = *IXP2000_SLOWPORT_CCR;
56 old_cfg->WTC = *IXP2000_SLOWPORT_WTC2;
57 old_cfg->RTC = *IXP2000_SLOWPORT_RTC2;
58 old_cfg->PCR = *IXP2000_SLOWPORT_PCR;
59 old_cfg->ADC = *IXP2000_SLOWPORT_ADC;
60
61 ixp2000_reg_write(IXP2000_SLOWPORT_CCR, new_cfg->CCR);
62 ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, new_cfg->WTC);
63 ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, new_cfg->RTC);
64 ixp2000_reg_write(IXP2000_SLOWPORT_PCR, new_cfg->PCR);
65 ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, new_cfg->ADC);
66 }
67
68 void ixp2000_release_slowport(struct slowport_cfg *old_cfg)
69 {
70 ixp2000_reg_write(IXP2000_SLOWPORT_CCR, old_cfg->CCR);
71 ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, old_cfg->WTC);
72 ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, old_cfg->RTC);
73 ixp2000_reg_write(IXP2000_SLOWPORT_PCR, old_cfg->PCR);
74 ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, old_cfg->ADC);
75
76 spin_unlock_irqrestore(&ixp2000_slowport_lock,
77 ixp2000_slowport_irq_flags);
78 }
79
80 /*************************************************************************
81 * Chip specific mappings shared by all IXP2000 systems
82 *************************************************************************/
83 static struct map_desc ixp2000_io_desc[] __initdata = {
84 {
85 .virtual = IXP2000_CAP_VIRT_BASE,
86 .pfn = __phys_to_pfn(IXP2000_CAP_PHYS_BASE),
87 .length = IXP2000_CAP_SIZE,
88 .type = MT_DEVICE,
89 }, {
90 .virtual = IXP2000_INTCTL_VIRT_BASE,
91 .pfn = __phys_to_pfn(IXP2000_INTCTL_PHYS_BASE),
92 .length = IXP2000_INTCTL_SIZE,
93 .type = MT_DEVICE,
94 }, {
95 .virtual = IXP2000_PCI_CREG_VIRT_BASE,
96 .pfn = __phys_to_pfn(IXP2000_PCI_CREG_PHYS_BASE),
97 .length = IXP2000_PCI_CREG_SIZE,
98 .type = MT_DEVICE,
99 }, {
100 .virtual = IXP2000_PCI_CSR_VIRT_BASE,
101 .pfn = __phys_to_pfn(IXP2000_PCI_CSR_PHYS_BASE),
102 .length = IXP2000_PCI_CSR_SIZE,
103 .type = MT_DEVICE,
104 }, {
105 .virtual = IXP2000_MSF_VIRT_BASE,
106 .pfn = __phys_to_pfn(IXP2000_MSF_PHYS_BASE),
107 .length = IXP2000_MSF_SIZE,
108 .type = MT_DEVICE,
109 }, {
110 .virtual = IXP2000_SCRATCH_RING_VIRT_BASE,
111 .pfn = __phys_to_pfn(IXP2000_SCRATCH_RING_PHYS_BASE),
112 .length = IXP2000_SCRATCH_RING_SIZE,
113 .type = MT_DEVICE,
114 }, {
115 .virtual = IXP2000_SRAM0_VIRT_BASE,
116 .pfn = __phys_to_pfn(IXP2000_SRAM0_PHYS_BASE),
117 .length = IXP2000_SRAM0_SIZE,
118 .type = MT_DEVICE,
119 }, {
120 .virtual = IXP2000_PCI_IO_VIRT_BASE,
121 .pfn = __phys_to_pfn(IXP2000_PCI_IO_PHYS_BASE),
122 .length = IXP2000_PCI_IO_SIZE,
123 .type = MT_DEVICE,
124 }, {
125 .virtual = IXP2000_PCI_CFG0_VIRT_BASE,
126 .pfn = __phys_to_pfn(IXP2000_PCI_CFG0_PHYS_BASE),
127 .length = IXP2000_PCI_CFG0_SIZE,
128 .type = MT_DEVICE,
129 }, {
130 .virtual = IXP2000_PCI_CFG1_VIRT_BASE,
131 .pfn = __phys_to_pfn(IXP2000_PCI_CFG1_PHYS_BASE),
132 .length = IXP2000_PCI_CFG1_SIZE,
133 .type = MT_DEVICE,
134 }
135 };
136
137 void __init ixp2000_map_io(void)
138 {
139 iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc));
140
141 /* Set slowport to 8-bit mode. */
142 ixp2000_reg_wrb(IXP2000_SLOWPORT_FRM, 1);
143 }
144
145
146 /*************************************************************************
147 * Serial port support for IXP2000
148 *************************************************************************/
149 static struct plat_serial8250_port ixp2000_serial_port[] = {
150 {
151 .mapbase = IXP2000_UART_PHYS_BASE,
152 .membase = (char *)(IXP2000_UART_VIRT_BASE + 3),
153 .irq = IRQ_IXP2000_UART,
154 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
155 .iotype = UPIO_MEM,
156 .regshift = 2,
157 .uartclk = 50000000,
158 },
159 { },
160 };
161
162 static struct resource ixp2000_uart_resource = {
163 .start = IXP2000_UART_PHYS_BASE,
164 .end = IXP2000_UART_PHYS_BASE + 0x1f,
165 .flags = IORESOURCE_MEM,
166 };
167
168 static struct platform_device ixp2000_serial_device = {
169 .name = "serial8250",
170 .id = PLAT8250_DEV_PLATFORM,
171 .dev = {
172 .platform_data = ixp2000_serial_port,
173 },
174 .num_resources = 1,
175 .resource = &ixp2000_uart_resource,
176 };
177
178 void __init ixp2000_uart_init(void)
179 {
180 platform_device_register(&ixp2000_serial_device);
181 }
182
183
184 /*************************************************************************
185 * Timer-tick functions for IXP2000
186 *************************************************************************/
187 static unsigned ticks_per_jiffy;
188 static unsigned ticks_per_usec;
189 static unsigned next_jiffy_time;
190 static volatile unsigned long *missing_jiffy_timer_csr;
191
192 unsigned long ixp2000_gettimeoffset (void)
193 {
194 unsigned long offset;
195
196 offset = next_jiffy_time - *missing_jiffy_timer_csr;
197
198 return offset / ticks_per_usec;
199 }
200
201 static irqreturn_t ixp2000_timer_interrupt(int irq, void *dev_id)
202 {
203 /* clear timer 1 */
204 ixp2000_reg_wrb(IXP2000_T1_CLR, 1);
205
206 while ((signed long)(next_jiffy_time - *missing_jiffy_timer_csr)
207 >= ticks_per_jiffy) {
208 timer_tick();
209 next_jiffy_time -= ticks_per_jiffy;
210 }
211
212 return IRQ_HANDLED;
213 }
214
215 static struct irqaction ixp2000_timer_irq = {
216 .name = "IXP2000 Timer Tick",
217 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
218 .handler = ixp2000_timer_interrupt,
219 };
220
221 void __init ixp2000_init_time(unsigned long tick_rate)
222 {
223 ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
224 ticks_per_usec = tick_rate / 1000000;
225
226 /*
227 * We use timer 1 as our timer interrupt.
228 */
229 ixp2000_reg_write(IXP2000_T1_CLR, 0);
230 ixp2000_reg_write(IXP2000_T1_CLD, ticks_per_jiffy - 1);
231 ixp2000_reg_write(IXP2000_T1_CTL, (1 << 7));
232
233 /*
234 * We use a second timer as a monotonic counter for tracking
235 * missed jiffies. The IXP2000 has four timers, but if we're
236 * on an A-step IXP2800, timer 2 and 3 don't work, so on those
237 * chips we use timer 4. Timer 4 is the only timer that can
238 * be used for the watchdog, so we use timer 2 if we're on a
239 * non-buggy chip.
240 */
241 if ((*IXP2000_PRODUCT_ID & 0x001ffef0) == 0x00000000) {
242 printk(KERN_INFO "Enabling IXP2800 erratum #25 workaround\n");
243
244 ixp2000_reg_write(IXP2000_T4_CLR, 0);
245 ixp2000_reg_write(IXP2000_T4_CLD, -1);
246 ixp2000_reg_wrb(IXP2000_T4_CTL, (1 << 7));
247 missing_jiffy_timer_csr = IXP2000_T4_CSR;
248 } else {
249 ixp2000_reg_write(IXP2000_T2_CLR, 0);
250 ixp2000_reg_write(IXP2000_T2_CLD, -1);
251 ixp2000_reg_wrb(IXP2000_T2_CTL, (1 << 7));
252 missing_jiffy_timer_csr = IXP2000_T2_CSR;
253 }
254 next_jiffy_time = 0xffffffff;
255
256 /* register for interrupt */
257 setup_irq(IRQ_IXP2000_TIMER1, &ixp2000_timer_irq);
258 }
259
260 /*************************************************************************
261 * GPIO helpers
262 *************************************************************************/
263 static unsigned long GPIO_IRQ_falling_edge;
264 static unsigned long GPIO_IRQ_rising_edge;
265 static unsigned long GPIO_IRQ_level_low;
266 static unsigned long GPIO_IRQ_level_high;
267
268 static void update_gpio_int_csrs(void)
269 {
270 ixp2000_reg_write(IXP2000_GPIO_FEDR, GPIO_IRQ_falling_edge);
271 ixp2000_reg_write(IXP2000_GPIO_REDR, GPIO_IRQ_rising_edge);
272 ixp2000_reg_write(IXP2000_GPIO_LSLR, GPIO_IRQ_level_low);
273 ixp2000_reg_wrb(IXP2000_GPIO_LSHR, GPIO_IRQ_level_high);
274 }
275
276 void gpio_line_config(int line, int direction)
277 {
278 unsigned long flags;
279
280 local_irq_save(flags);
281 if (direction == GPIO_OUT) {
282 /* if it's an output, it ain't an interrupt anymore */
283 GPIO_IRQ_falling_edge &= ~(1 << line);
284 GPIO_IRQ_rising_edge &= ~(1 << line);
285 GPIO_IRQ_level_low &= ~(1 << line);
286 GPIO_IRQ_level_high &= ~(1 << line);
287 update_gpio_int_csrs();
288
289 ixp2000_reg_wrb(IXP2000_GPIO_PDSR, 1 << line);
290 } else if (direction == GPIO_IN) {
291 ixp2000_reg_wrb(IXP2000_GPIO_PDCR, 1 << line);
292 }
293 local_irq_restore(flags);
294 }
295 EXPORT_SYMBOL(gpio_line_config);
296
297
298 /*************************************************************************
299 * IRQ handling IXP2000
300 *************************************************************************/
301 static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irq_desc *desc)
302 {
303 int i;
304 unsigned long status = *IXP2000_GPIO_INST;
305
306 for (i = 0; i <= 7; i++) {
307 if (status & (1<<i)) {
308 generic_handle_irq(i + IRQ_IXP2000_GPIO0);
309 }
310 }
311 }
312
313 static int ixp2000_GPIO_irq_type(struct irq_data *d, unsigned int type)
314 {
315 int line = d->irq - IRQ_IXP2000_GPIO0;
316
317 /*
318 * First, configure this GPIO line as an input.
319 */
320 ixp2000_reg_write(IXP2000_GPIO_PDCR, 1 << line);
321
322 /*
323 * Then, set the proper trigger type.
324 */
325 if (type & IRQ_TYPE_EDGE_FALLING)
326 GPIO_IRQ_falling_edge |= 1 << line;
327 else
328 GPIO_IRQ_falling_edge &= ~(1 << line);
329 if (type & IRQ_TYPE_EDGE_RISING)
330 GPIO_IRQ_rising_edge |= 1 << line;
331 else
332 GPIO_IRQ_rising_edge &= ~(1 << line);
333 if (type & IRQ_TYPE_LEVEL_LOW)
334 GPIO_IRQ_level_low |= 1 << line;
335 else
336 GPIO_IRQ_level_low &= ~(1 << line);
337 if (type & IRQ_TYPE_LEVEL_HIGH)
338 GPIO_IRQ_level_high |= 1 << line;
339 else
340 GPIO_IRQ_level_high &= ~(1 << line);
341 update_gpio_int_csrs();
342
343 return 0;
344 }
345
346 static void ixp2000_GPIO_irq_mask_ack(struct irq_data *d)
347 {
348 unsigned int irq = d->irq;
349
350 ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
351
352 ixp2000_reg_write(IXP2000_GPIO_EDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
353 ixp2000_reg_write(IXP2000_GPIO_LDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
354 ixp2000_reg_wrb(IXP2000_GPIO_INST, (1 << (irq - IRQ_IXP2000_GPIO0)));
355 }
356
357 static void ixp2000_GPIO_irq_mask(struct irq_data *d)
358 {
359 unsigned int irq = d->irq;
360
361 ixp2000_reg_wrb(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
362 }
363
364 static void ixp2000_GPIO_irq_unmask(struct irq_data *d)
365 {
366 unsigned int irq = d->irq;
367
368 ixp2000_reg_write(IXP2000_GPIO_INSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
369 }
370
371 static struct irq_chip ixp2000_GPIO_irq_chip = {
372 .irq_ack = ixp2000_GPIO_irq_mask_ack,
373 .irq_mask = ixp2000_GPIO_irq_mask,
374 .irq_unmask = ixp2000_GPIO_irq_unmask,
375 .irq_set_type = ixp2000_GPIO_irq_type,
376 };
377
378 static void ixp2000_pci_irq_mask(struct irq_data *d)
379 {
380 unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
381 if (d->irq == IRQ_IXP2000_PCIA)
382 ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 26)));
383 else if (d->irq == IRQ_IXP2000_PCIB)
384 ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 27)));
385 }
386
387 static void ixp2000_pci_irq_unmask(struct irq_data *d)
388 {
389 unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
390 if (d->irq == IRQ_IXP2000_PCIA)
391 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 26)));
392 else if (d->irq == IRQ_IXP2000_PCIB)
393 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 27)));
394 }
395
396 /*
397 * Error interrupts. These are used extensively by the microengine drivers
398 */
399 static void ixp2000_err_irq_handler(unsigned int irq, struct irq_desc *desc)
400 {
401 int i;
402 unsigned long status = *IXP2000_IRQ_ERR_STATUS;
403
404 for(i = 31; i >= 0; i--) {
405 if(status & (1 << i)) {
406 generic_handle_irq(IRQ_IXP2000_DRAM0_MIN_ERR + i);
407 }
408 }
409 }
410
411 static void ixp2000_err_irq_mask(struct irq_data *d)
412 {
413 ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_CLR,
414 (1 << (d->irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
415 }
416
417 static void ixp2000_err_irq_unmask(struct irq_data *d)
418 {
419 ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_SET,
420 (1 << (d->irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
421 }
422
423 static struct irq_chip ixp2000_err_irq_chip = {
424 .irq_ack = ixp2000_err_irq_mask,
425 .irq_mask = ixp2000_err_irq_mask,
426 .irq_unmask = ixp2000_err_irq_unmask
427 };
428
429 static struct irq_chip ixp2000_pci_irq_chip = {
430 .irq_ack = ixp2000_pci_irq_mask,
431 .irq_mask = ixp2000_pci_irq_mask,
432 .irq_unmask = ixp2000_pci_irq_unmask
433 };
434
435 static void ixp2000_irq_mask(struct irq_data *d)
436 {
437 ixp2000_reg_wrb(IXP2000_IRQ_ENABLE_CLR, (1 << d->irq));
438 }
439
440 static void ixp2000_irq_unmask(struct irq_data *d)
441 {
442 ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << d->irq));
443 }
444
445 static struct irq_chip ixp2000_irq_chip = {
446 .irq_ack = ixp2000_irq_mask,
447 .irq_mask = ixp2000_irq_mask,
448 .irq_unmask = ixp2000_irq_unmask
449 };
450
451 void __init ixp2000_init_irq(void)
452 {
453 int irq;
454
455 /*
456 * Mask all sources
457 */
458 ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, 0xffffffff);
459 ixp2000_reg_write(IXP2000_FIQ_ENABLE_CLR, 0xffffffff);
460
461 /* clear all GPIO edge/level detects */
462 ixp2000_reg_write(IXP2000_GPIO_REDR, 0);
463 ixp2000_reg_write(IXP2000_GPIO_FEDR, 0);
464 ixp2000_reg_write(IXP2000_GPIO_LSHR, 0);
465 ixp2000_reg_write(IXP2000_GPIO_LSLR, 0);
466 ixp2000_reg_write(IXP2000_GPIO_INCR, -1);
467
468 /* clear PCI interrupt sources */
469 ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, 0);
470
471 /*
472 * Certain bits in the IRQ status register of the
473 * IXP2000 are reserved. Instead of trying to map
474 * things non 1:1 from bit position to IRQ number,
475 * we mark the reserved IRQs as invalid. This makes
476 * our mask/unmask code much simpler.
477 */
478 for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) {
479 if ((1 << irq) & IXP2000_VALID_IRQ_MASK) {
480 irq_set_chip_and_handler(irq, &ixp2000_irq_chip,
481 handle_level_irq);
482 set_irq_flags(irq, IRQF_VALID);
483 } else set_irq_flags(irq, 0);
484 }
485
486 for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) {
487 if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) &
488 IXP2000_VALID_ERR_IRQ_MASK) {
489 irq_set_chip_and_handler(irq, &ixp2000_err_irq_chip,
490 handle_level_irq);
491 set_irq_flags(irq, IRQF_VALID);
492 }
493 else
494 set_irq_flags(irq, 0);
495 }
496 irq_set_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler);
497
498 for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) {
499 irq_set_chip_and_handler(irq, &ixp2000_GPIO_irq_chip,
500 handle_level_irq);
501 set_irq_flags(irq, IRQF_VALID);
502 }
503 irq_set_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);
504
505 /*
506 * Enable PCI irqs. The actual PCI[AB] decoding is done in
507 * entry-macro.S, so we don't need a chained handler for the
508 * PCI interrupt source.
509 */
510 ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI));
511 for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {
512 irq_set_chip_and_handler(irq, &ixp2000_pci_irq_chip,
513 handle_level_irq);
514 set_irq_flags(irq, IRQF_VALID);
515 }
516 }
517
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