2 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
14 #include <linux/delay.h>
15 #include <linux/clk.h>
17 #include <linux/clkdev.h>
19 #include <asm/div64.h>
21 #include <mach/hardware.h>
22 #include <mach/common.h>
23 #include <mach/clock.h>
27 /* External clock values passed-in by the board code */
28 static unsigned long external_high_reference
, external_low_reference
;
29 static unsigned long oscillator_reference
, ckih2_reference
;
31 static struct clk osc_clk
;
32 static struct clk pll1_main_clk
;
33 static struct clk pll1_sw_clk
;
34 static struct clk pll2_sw_clk
;
35 static struct clk pll3_sw_clk
;
36 static struct clk mx53_pll4_sw_clk
;
37 static struct clk lp_apm_clk
;
38 static struct clk periph_apm_clk
;
39 static struct clk ahb_clk
;
40 static struct clk ipg_clk
;
41 static struct clk usboh3_clk
;
42 static struct clk emi_fast_clk
;
43 static struct clk ipu_clk
;
44 static struct clk mipi_hsc1_clk
;
45 static struct clk esdhc1_clk
;
46 static struct clk esdhc2_clk
;
47 static struct clk esdhc3_mx53_clk
;
49 #define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */
51 /* calculate best pre and post dividers to get the required divider */
52 static void __calc_pre_post_dividers(u32 div
, u32
*pre
, u32
*post
,
53 u32 max_pre
, u32 max_post
)
55 if (div
>= max_pre
* max_post
) {
58 } else if (div
>= max_pre
) {
59 u32 min_pre
, temp_pre
, old_err
, err
;
60 min_pre
= DIV_ROUND_UP(div
, max_post
);
62 for (temp_pre
= max_pre
; temp_pre
>= min_pre
; temp_pre
--) {
74 *post
= DIV_ROUND_UP(div
, *pre
);
81 static void _clk_ccgr_setclk(struct clk
*clk
, unsigned mode
)
83 u32 reg
= __raw_readl(clk
->enable_reg
);
85 reg
&= ~(MXC_CCM_CCGRx_CG_MASK
<< clk
->enable_shift
);
86 reg
|= mode
<< clk
->enable_shift
;
88 __raw_writel(reg
, clk
->enable_reg
);
91 static int _clk_ccgr_enable(struct clk
*clk
)
93 _clk_ccgr_setclk(clk
, MXC_CCM_CCGRx_MOD_ON
);
97 static void _clk_ccgr_disable(struct clk
*clk
)
99 _clk_ccgr_setclk(clk
, MXC_CCM_CCGRx_MOD_OFF
);
102 static int _clk_ccgr_enable_inrun(struct clk
*clk
)
104 _clk_ccgr_setclk(clk
, MXC_CCM_CCGRx_MOD_IDLE
);
108 static void _clk_ccgr_disable_inwait(struct clk
*clk
)
110 _clk_ccgr_setclk(clk
, MXC_CCM_CCGRx_MOD_IDLE
);
114 * For the 4-to-1 muxed input clock
116 static inline u32
_get_mux(struct clk
*parent
, struct clk
*m0
,
117 struct clk
*m1
, struct clk
*m2
, struct clk
*m3
)
121 else if (parent
== m1
)
123 else if (parent
== m2
)
125 else if (parent
== m3
)
133 static inline void __iomem
*_mx51_get_pll_base(struct clk
*pll
)
135 if (pll
== &pll1_main_clk
)
136 return MX51_DPLL1_BASE
;
137 else if (pll
== &pll2_sw_clk
)
138 return MX51_DPLL2_BASE
;
139 else if (pll
== &pll3_sw_clk
)
140 return MX51_DPLL3_BASE
;
147 static inline void __iomem
*_mx53_get_pll_base(struct clk
*pll
)
149 if (pll
== &pll1_main_clk
)
150 return MX53_DPLL1_BASE
;
151 else if (pll
== &pll2_sw_clk
)
152 return MX53_DPLL2_BASE
;
153 else if (pll
== &pll3_sw_clk
)
154 return MX53_DPLL3_BASE
;
155 else if (pll
== &mx53_pll4_sw_clk
)
156 return MX53_DPLL4_BASE
;
163 static inline void __iomem
*_get_pll_base(struct clk
*pll
)
166 return _mx51_get_pll_base(pll
);
168 return _mx53_get_pll_base(pll
);
171 static unsigned long clk_pll_get_rate(struct clk
*clk
)
173 long mfi
, mfn
, mfd
, pdf
, ref_clk
, mfn_abs
;
174 unsigned long dp_op
, dp_mfd
, dp_mfn
, dp_ctl
, pll_hfsm
, dbl
;
175 void __iomem
*pllbase
;
177 unsigned long parent_rate
;
179 parent_rate
= clk_get_rate(clk
->parent
);
181 pllbase
= _get_pll_base(clk
);
183 dp_ctl
= __raw_readl(pllbase
+ MXC_PLL_DP_CTL
);
184 pll_hfsm
= dp_ctl
& MXC_PLL_DP_CTL_HFSM
;
185 dbl
= dp_ctl
& MXC_PLL_DP_CTL_DPDCK0_2_EN
;
188 dp_op
= __raw_readl(pllbase
+ MXC_PLL_DP_OP
);
189 dp_mfd
= __raw_readl(pllbase
+ MXC_PLL_DP_MFD
);
190 dp_mfn
= __raw_readl(pllbase
+ MXC_PLL_DP_MFN
);
192 dp_op
= __raw_readl(pllbase
+ MXC_PLL_DP_HFS_OP
);
193 dp_mfd
= __raw_readl(pllbase
+ MXC_PLL_DP_HFS_MFD
);
194 dp_mfn
= __raw_readl(pllbase
+ MXC_PLL_DP_HFS_MFN
);
196 pdf
= dp_op
& MXC_PLL_DP_OP_PDF_MASK
;
197 mfi
= (dp_op
& MXC_PLL_DP_OP_MFI_MASK
) >> MXC_PLL_DP_OP_MFI_OFFSET
;
198 mfi
= (mfi
<= 5) ? 5 : mfi
;
199 mfd
= dp_mfd
& MXC_PLL_DP_MFD_MASK
;
200 mfn
= mfn_abs
= dp_mfn
& MXC_PLL_DP_MFN_MASK
;
201 /* Sign extend to 32-bits */
202 if (mfn
>= 0x04000000) {
207 ref_clk
= 2 * parent_rate
;
211 ref_clk
/= (pdf
+ 1);
212 temp
= (u64
) ref_clk
* mfn_abs
;
213 do_div(temp
, mfd
+ 1);
216 temp
= (ref_clk
* mfi
) + temp
;
221 static int _clk_pll_set_rate(struct clk
*clk
, unsigned long rate
)
224 void __iomem
*pllbase
;
226 long mfi
, pdf
, mfn
, mfd
= 999999;
228 unsigned long quad_parent_rate
;
229 unsigned long pll_hfsm
, dp_ctl
;
230 unsigned long parent_rate
;
232 parent_rate
= clk_get_rate(clk
->parent
);
234 pllbase
= _get_pll_base(clk
);
236 quad_parent_rate
= 4 * parent_rate
;
238 while (++pdf
< 16 && mfi
< 5)
239 mfi
= rate
* (pdf
+1) / quad_parent_rate
;
244 temp64
= rate
* (pdf
+1) - quad_parent_rate
* mfi
;
245 do_div(temp64
, quad_parent_rate
/1000000);
248 dp_ctl
= __raw_readl(pllbase
+ MXC_PLL_DP_CTL
);
250 __raw_writel(dp_ctl
| 0x1000L
, pllbase
+ MXC_PLL_DP_CTL
);
251 pll_hfsm
= dp_ctl
& MXC_PLL_DP_CTL_HFSM
;
253 reg
= mfi
<< 4 | pdf
;
254 __raw_writel(reg
, pllbase
+ MXC_PLL_DP_OP
);
255 __raw_writel(mfd
, pllbase
+ MXC_PLL_DP_MFD
);
256 __raw_writel(mfn
, pllbase
+ MXC_PLL_DP_MFN
);
258 reg
= mfi
<< 4 | pdf
;
259 __raw_writel(reg
, pllbase
+ MXC_PLL_DP_HFS_OP
);
260 __raw_writel(mfd
, pllbase
+ MXC_PLL_DP_HFS_MFD
);
261 __raw_writel(mfn
, pllbase
+ MXC_PLL_DP_HFS_MFN
);
267 static int _clk_pll_enable(struct clk
*clk
)
270 void __iomem
*pllbase
;
273 pllbase
= _get_pll_base(clk
);
274 reg
= __raw_readl(pllbase
+ MXC_PLL_DP_CTL
);
275 if (reg
& MXC_PLL_DP_CTL_UPEN
)
278 reg
|= MXC_PLL_DP_CTL_UPEN
;
279 __raw_writel(reg
, pllbase
+ MXC_PLL_DP_CTL
);
283 reg
= __raw_readl(pllbase
+ MXC_PLL_DP_CTL
);
284 if (reg
& MXC_PLL_DP_CTL_LRF
)
288 } while (++i
< MAX_DPLL_WAIT_TRIES
);
290 if (i
== MAX_DPLL_WAIT_TRIES
) {
291 pr_err("MX5: pll locking failed\n");
298 static void _clk_pll_disable(struct clk
*clk
)
301 void __iomem
*pllbase
;
303 pllbase
= _get_pll_base(clk
);
304 reg
= __raw_readl(pllbase
+ MXC_PLL_DP_CTL
) & ~MXC_PLL_DP_CTL_UPEN
;
305 __raw_writel(reg
, pllbase
+ MXC_PLL_DP_CTL
);
308 static int _clk_pll1_sw_set_parent(struct clk
*clk
, struct clk
*parent
)
312 reg
= __raw_readl(MXC_CCM_CCSR
);
314 /* When switching from pll_main_clk to a bypass clock, first select a
315 * multiplexed clock in 'step_sel', then shift the glitchless mux
318 * When switching back, do it in reverse order
320 if (parent
== &pll1_main_clk
) {
321 /* Switch to pll1_main_clk */
322 reg
&= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL
;
323 __raw_writel(reg
, MXC_CCM_CCSR
);
324 /* step_clk mux switched to lp_apm, to save power. */
325 reg
= __raw_readl(MXC_CCM_CCSR
);
326 reg
&= ~MXC_CCM_CCSR_STEP_SEL_MASK
;
327 reg
|= (MXC_CCM_CCSR_STEP_SEL_LP_APM
<<
328 MXC_CCM_CCSR_STEP_SEL_OFFSET
);
330 if (parent
== &lp_apm_clk
) {
331 step
= MXC_CCM_CCSR_STEP_SEL_LP_APM
;
332 } else if (parent
== &pll2_sw_clk
) {
333 step
= MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED
;
334 } else if (parent
== &pll3_sw_clk
) {
335 step
= MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED
;
339 reg
&= ~MXC_CCM_CCSR_STEP_SEL_MASK
;
340 reg
|= (step
<< MXC_CCM_CCSR_STEP_SEL_OFFSET
);
342 __raw_writel(reg
, MXC_CCM_CCSR
);
343 /* Switch to step_clk */
344 reg
= __raw_readl(MXC_CCM_CCSR
);
345 reg
|= MXC_CCM_CCSR_PLL1_SW_CLK_SEL
;
347 __raw_writel(reg
, MXC_CCM_CCSR
);
351 static unsigned long clk_pll1_sw_get_rate(struct clk
*clk
)
354 unsigned long parent_rate
;
356 parent_rate
= clk_get_rate(clk
->parent
);
358 reg
= __raw_readl(MXC_CCM_CCSR
);
360 if (clk
->parent
== &pll2_sw_clk
) {
361 div
= ((reg
& MXC_CCM_CCSR_PLL2_PODF_MASK
) >>
362 MXC_CCM_CCSR_PLL2_PODF_OFFSET
) + 1;
363 } else if (clk
->parent
== &pll3_sw_clk
) {
364 div
= ((reg
& MXC_CCM_CCSR_PLL3_PODF_MASK
) >>
365 MXC_CCM_CCSR_PLL3_PODF_OFFSET
) + 1;
368 return parent_rate
/ div
;
371 static int _clk_pll2_sw_set_parent(struct clk
*clk
, struct clk
*parent
)
375 reg
= __raw_readl(MXC_CCM_CCSR
);
377 if (parent
== &pll2_sw_clk
)
378 reg
&= ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL
;
380 reg
|= MXC_CCM_CCSR_PLL2_SW_CLK_SEL
;
382 __raw_writel(reg
, MXC_CCM_CCSR
);
386 static int _clk_lp_apm_set_parent(struct clk
*clk
, struct clk
*parent
)
390 if (parent
== &osc_clk
)
391 reg
= __raw_readl(MXC_CCM_CCSR
) & ~MXC_CCM_CCSR_LP_APM_SEL
;
395 __raw_writel(reg
, MXC_CCM_CCSR
);
400 static unsigned long clk_cpu_get_rate(struct clk
*clk
)
403 unsigned long parent_rate
;
405 parent_rate
= clk_get_rate(clk
->parent
);
406 cacrr
= __raw_readl(MXC_CCM_CACRR
);
407 div
= (cacrr
& MXC_CCM_CACRR_ARM_PODF_MASK
) + 1;
409 return parent_rate
/ div
;
412 static int clk_cpu_set_rate(struct clk
*clk
, unsigned long rate
)
415 unsigned long parent_rate
;
417 parent_rate
= clk_get_rate(clk
->parent
);
418 cpu_podf
= parent_rate
/ rate
- 1;
419 /* use post divider to change freq */
420 reg
= __raw_readl(MXC_CCM_CACRR
);
421 reg
&= ~MXC_CCM_CACRR_ARM_PODF_MASK
;
422 reg
|= cpu_podf
<< MXC_CCM_CACRR_ARM_PODF_OFFSET
;
423 __raw_writel(reg
, MXC_CCM_CACRR
);
428 static int _clk_periph_apm_set_parent(struct clk
*clk
, struct clk
*parent
)
433 mux
= _get_mux(parent
, &pll1_sw_clk
, &pll3_sw_clk
, &lp_apm_clk
, NULL
);
435 reg
= __raw_readl(MXC_CCM_CBCMR
) & ~MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK
;
436 reg
|= mux
<< MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET
;
437 __raw_writel(reg
, MXC_CCM_CBCMR
);
441 reg
= __raw_readl(MXC_CCM_CDHIPR
);
442 if (!(reg
& MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY
))
446 } while (++i
< MAX_DPLL_WAIT_TRIES
);
448 if (i
== MAX_DPLL_WAIT_TRIES
) {
449 pr_err("MX5: Set parent for periph_apm clock failed\n");
456 static int _clk_main_bus_set_parent(struct clk
*clk
, struct clk
*parent
)
460 reg
= __raw_readl(MXC_CCM_CBCDR
);
462 if (parent
== &pll2_sw_clk
)
463 reg
&= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL
;
464 else if (parent
== &periph_apm_clk
)
465 reg
|= MXC_CCM_CBCDR_PERIPH_CLK_SEL
;
469 __raw_writel(reg
, MXC_CCM_CBCDR
);
474 static struct clk main_bus_clk
= {
475 .parent
= &pll2_sw_clk
,
476 .set_parent
= _clk_main_bus_set_parent
,
479 static unsigned long clk_ahb_get_rate(struct clk
*clk
)
482 unsigned long parent_rate
;
484 parent_rate
= clk_get_rate(clk
->parent
);
486 reg
= __raw_readl(MXC_CCM_CBCDR
);
487 div
= ((reg
& MXC_CCM_CBCDR_AHB_PODF_MASK
) >>
488 MXC_CCM_CBCDR_AHB_PODF_OFFSET
) + 1;
489 return parent_rate
/ div
;
493 static int _clk_ahb_set_rate(struct clk
*clk
, unsigned long rate
)
496 unsigned long parent_rate
;
499 parent_rate
= clk_get_rate(clk
->parent
);
501 div
= parent_rate
/ rate
;
502 if (div
> 8 || div
< 1 || ((parent_rate
/ div
) != rate
))
505 reg
= __raw_readl(MXC_CCM_CBCDR
);
506 reg
&= ~MXC_CCM_CBCDR_AHB_PODF_MASK
;
507 reg
|= (div
- 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET
;
508 __raw_writel(reg
, MXC_CCM_CBCDR
);
512 reg
= __raw_readl(MXC_CCM_CDHIPR
);
513 if (!(reg
& MXC_CCM_CDHIPR_AHB_PODF_BUSY
))
517 } while (++i
< MAX_DPLL_WAIT_TRIES
);
519 if (i
== MAX_DPLL_WAIT_TRIES
) {
520 pr_err("MX5: clk_ahb_set_rate failed\n");
527 static unsigned long _clk_ahb_round_rate(struct clk
*clk
,
531 unsigned long parent_rate
;
533 parent_rate
= clk_get_rate(clk
->parent
);
535 div
= parent_rate
/ rate
;
540 return parent_rate
/ div
;
544 static int _clk_max_enable(struct clk
*clk
)
548 _clk_ccgr_enable(clk
);
550 /* Handshake with MAX when LPM is entered. */
551 reg
= __raw_readl(MXC_CCM_CLPCR
);
553 reg
&= ~MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS
;
554 else if (cpu_is_mx53())
555 reg
&= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS
;
556 __raw_writel(reg
, MXC_CCM_CLPCR
);
561 static void _clk_max_disable(struct clk
*clk
)
565 _clk_ccgr_disable_inwait(clk
);
567 /* No Handshake with MAX when LPM is entered as its disabled. */
568 reg
= __raw_readl(MXC_CCM_CLPCR
);
570 reg
|= MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS
;
571 else if (cpu_is_mx53())
572 reg
&= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS
;
573 __raw_writel(reg
, MXC_CCM_CLPCR
);
576 static unsigned long clk_ipg_get_rate(struct clk
*clk
)
579 unsigned long parent_rate
;
581 parent_rate
= clk_get_rate(clk
->parent
);
583 reg
= __raw_readl(MXC_CCM_CBCDR
);
584 div
= ((reg
& MXC_CCM_CBCDR_IPG_PODF_MASK
) >>
585 MXC_CCM_CBCDR_IPG_PODF_OFFSET
) + 1;
587 return parent_rate
/ div
;
590 static unsigned long clk_ipg_per_get_rate(struct clk
*clk
)
592 u32 reg
, prediv1
, prediv2
, podf
;
593 unsigned long parent_rate
;
595 parent_rate
= clk_get_rate(clk
->parent
);
597 if (clk
->parent
== &main_bus_clk
|| clk
->parent
== &lp_apm_clk
) {
598 /* the main_bus_clk is the one before the DVFS engine */
599 reg
= __raw_readl(MXC_CCM_CBCDR
);
600 prediv1
= ((reg
& MXC_CCM_CBCDR_PERCLK_PRED1_MASK
) >>
601 MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET
) + 1;
602 prediv2
= ((reg
& MXC_CCM_CBCDR_PERCLK_PRED2_MASK
) >>
603 MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET
) + 1;
604 podf
= ((reg
& MXC_CCM_CBCDR_PERCLK_PODF_MASK
) >>
605 MXC_CCM_CBCDR_PERCLK_PODF_OFFSET
) + 1;
606 return parent_rate
/ (prediv1
* prediv2
* podf
);
607 } else if (clk
->parent
== &ipg_clk
)
613 static int _clk_ipg_per_set_parent(struct clk
*clk
, struct clk
*parent
)
617 reg
= __raw_readl(MXC_CCM_CBCMR
);
619 reg
&= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL
;
620 reg
&= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL
;
622 if (parent
== &ipg_clk
)
623 reg
|= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL
;
624 else if (parent
== &lp_apm_clk
)
625 reg
|= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL
;
626 else if (parent
!= &main_bus_clk
)
629 __raw_writel(reg
, MXC_CCM_CBCMR
);
634 #define clk_nfc_set_parent NULL
636 static unsigned long clk_nfc_get_rate(struct clk
*clk
)
641 reg
= __raw_readl(MXC_CCM_CBCDR
);
642 div
= ((reg
& MXC_CCM_CBCDR_NFC_PODF_MASK
) >>
643 MXC_CCM_CBCDR_NFC_PODF_OFFSET
) + 1;
644 rate
= clk_get_rate(clk
->parent
) / div
;
649 static unsigned long clk_nfc_round_rate(struct clk
*clk
,
653 unsigned long parent_rate
= clk_get_rate(clk
->parent
);
658 div
= parent_rate
/ rate
;
660 if (parent_rate
% rate
)
666 return parent_rate
/ div
;
670 static int clk_nfc_set_rate(struct clk
*clk
, unsigned long rate
)
674 div
= clk_get_rate(clk
->parent
) / rate
;
677 if (((clk_get_rate(clk
->parent
) / div
) != rate
) || (div
> 8))
680 reg
= __raw_readl(MXC_CCM_CBCDR
);
681 reg
&= ~MXC_CCM_CBCDR_NFC_PODF_MASK
;
682 reg
|= (div
- 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET
;
683 __raw_writel(reg
, MXC_CCM_CBCDR
);
685 while (__raw_readl(MXC_CCM_CDHIPR
) &
686 MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY
){
692 static unsigned long get_high_reference_clock_rate(struct clk
*clk
)
694 return external_high_reference
;
697 static unsigned long get_low_reference_clock_rate(struct clk
*clk
)
699 return external_low_reference
;
702 static unsigned long get_oscillator_reference_clock_rate(struct clk
*clk
)
704 return oscillator_reference
;
707 static unsigned long get_ckih2_reference_clock_rate(struct clk
*clk
)
709 return ckih2_reference
;
712 static unsigned long clk_emi_slow_get_rate(struct clk
*clk
)
716 reg
= __raw_readl(MXC_CCM_CBCDR
);
717 div
= ((reg
& MXC_CCM_CBCDR_EMI_PODF_MASK
) >>
718 MXC_CCM_CBCDR_EMI_PODF_OFFSET
) + 1;
720 return clk_get_rate(clk
->parent
) / div
;
723 static unsigned long _clk_ddr_hf_get_rate(struct clk
*clk
)
728 reg
= __raw_readl(MXC_CCM_CBCDR
);
729 div
= ((reg
& MXC_CCM_CBCDR_DDR_PODF_MASK
) >>
730 MXC_CCM_CBCDR_DDR_PODF_OFFSET
) + 1;
731 rate
= clk_get_rate(clk
->parent
) / div
;
736 /* External high frequency clock */
737 static struct clk ckih_clk
= {
738 .get_rate
= get_high_reference_clock_rate
,
741 static struct clk ckih2_clk
= {
742 .get_rate
= get_ckih2_reference_clock_rate
,
745 static struct clk osc_clk
= {
746 .get_rate
= get_oscillator_reference_clock_rate
,
749 /* External low frequency (32kHz) clock */
750 static struct clk ckil_clk
= {
751 .get_rate
= get_low_reference_clock_rate
,
754 static struct clk pll1_main_clk
= {
756 .get_rate
= clk_pll_get_rate
,
757 .enable
= _clk_pll_enable
,
758 .disable
= _clk_pll_disable
,
761 /* Clock tree block diagram (WIP):
762 * CCM: Clock Controller Module
765 * | CCM Switcher -> CCM_CLK_ROOT_GEN ->
770 /* PLL1 SW supplies to ARM core */
771 static struct clk pll1_sw_clk
= {
772 .parent
= &pll1_main_clk
,
773 .set_parent
= _clk_pll1_sw_set_parent
,
774 .get_rate
= clk_pll1_sw_get_rate
,
777 /* PLL2 SW supplies to AXI/AHB/IP buses */
778 static struct clk pll2_sw_clk
= {
780 .get_rate
= clk_pll_get_rate
,
781 .set_rate
= _clk_pll_set_rate
,
782 .set_parent
= _clk_pll2_sw_set_parent
,
783 .enable
= _clk_pll_enable
,
784 .disable
= _clk_pll_disable
,
787 /* PLL3 SW supplies to serial clocks like USB, SSI, etc. */
788 static struct clk pll3_sw_clk
= {
790 .set_rate
= _clk_pll_set_rate
,
791 .get_rate
= clk_pll_get_rate
,
792 .enable
= _clk_pll_enable
,
793 .disable
= _clk_pll_disable
,
796 /* PLL4 SW supplies to LVDS Display Bridge(LDB) */
797 static struct clk mx53_pll4_sw_clk
= {
799 .set_rate
= _clk_pll_set_rate
,
800 .enable
= _clk_pll_enable
,
801 .disable
= _clk_pll_disable
,
804 /* Low-power Audio Playback Mode clock */
805 static struct clk lp_apm_clk
= {
807 .set_parent
= _clk_lp_apm_set_parent
,
810 static struct clk periph_apm_clk
= {
811 .parent
= &pll1_sw_clk
,
812 .set_parent
= _clk_periph_apm_set_parent
,
815 static struct clk cpu_clk
= {
816 .parent
= &pll1_sw_clk
,
817 .get_rate
= clk_cpu_get_rate
,
818 .set_rate
= clk_cpu_set_rate
,
821 static struct clk ahb_clk
= {
822 .parent
= &main_bus_clk
,
823 .get_rate
= clk_ahb_get_rate
,
824 .set_rate
= _clk_ahb_set_rate
,
825 .round_rate
= _clk_ahb_round_rate
,
828 static struct clk iim_clk
= {
830 .enable_reg
= MXC_CCM_CCGR0
,
831 .enable_shift
= MXC_CCM_CCGRx_CG15_OFFSET
,
834 /* Main IP interface clock for access to registers */
835 static struct clk ipg_clk
= {
837 .get_rate
= clk_ipg_get_rate
,
840 static struct clk ipg_perclk
= {
841 .parent
= &lp_apm_clk
,
842 .get_rate
= clk_ipg_per_get_rate
,
843 .set_parent
= _clk_ipg_per_set_parent
,
846 static struct clk ahb_max_clk
= {
848 .enable_reg
= MXC_CCM_CCGR0
,
849 .enable_shift
= MXC_CCM_CCGRx_CG14_OFFSET
,
850 .enable
= _clk_max_enable
,
851 .disable
= _clk_max_disable
,
854 static struct clk aips_tz1_clk
= {
856 .secondary
= &ahb_max_clk
,
857 .enable_reg
= MXC_CCM_CCGR0
,
858 .enable_shift
= MXC_CCM_CCGRx_CG12_OFFSET
,
859 .enable
= _clk_ccgr_enable
,
860 .disable
= _clk_ccgr_disable_inwait
,
863 static struct clk aips_tz2_clk
= {
865 .secondary
= &ahb_max_clk
,
866 .enable_reg
= MXC_CCM_CCGR0
,
867 .enable_shift
= MXC_CCM_CCGRx_CG13_OFFSET
,
868 .enable
= _clk_ccgr_enable
,
869 .disable
= _clk_ccgr_disable_inwait
,
872 static struct clk gpc_dvfs_clk
= {
873 .enable_reg
= MXC_CCM_CCGR5
,
874 .enable_shift
= MXC_CCM_CCGRx_CG12_OFFSET
,
875 .enable
= _clk_ccgr_enable
,
876 .disable
= _clk_ccgr_disable
,
879 static struct clk gpt_32k_clk
= {
884 static struct clk dummy_clk
= {
888 static struct clk emi_slow_clk
= {
889 .parent
= &pll2_sw_clk
,
890 .enable_reg
= MXC_CCM_CCGR5
,
891 .enable_shift
= MXC_CCM_CCGRx_CG8_OFFSET
,
892 .enable
= _clk_ccgr_enable
,
893 .disable
= _clk_ccgr_disable_inwait
,
894 .get_rate
= clk_emi_slow_get_rate
,
897 static int clk_ipu_enable(struct clk
*clk
)
901 _clk_ccgr_enable(clk
);
903 /* Enable handshake with IPU when certain clock rates are changed */
904 reg
= __raw_readl(MXC_CCM_CCDR
);
905 reg
&= ~MXC_CCM_CCDR_IPU_HS_MASK
;
906 __raw_writel(reg
, MXC_CCM_CCDR
);
908 /* Enable handshake with IPU when LPM is entered */
909 reg
= __raw_readl(MXC_CCM_CLPCR
);
910 reg
&= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS
;
911 __raw_writel(reg
, MXC_CCM_CLPCR
);
916 static void clk_ipu_disable(struct clk
*clk
)
920 _clk_ccgr_disable(clk
);
922 /* Disable handshake with IPU whe dividers are changed */
923 reg
= __raw_readl(MXC_CCM_CCDR
);
924 reg
|= MXC_CCM_CCDR_IPU_HS_MASK
;
925 __raw_writel(reg
, MXC_CCM_CCDR
);
927 /* Disable handshake with IPU when LPM is entered */
928 reg
= __raw_readl(MXC_CCM_CLPCR
);
929 reg
|= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS
;
930 __raw_writel(reg
, MXC_CCM_CLPCR
);
933 static struct clk ahbmux1_clk
= {
935 .secondary
= &ahb_max_clk
,
936 .enable_reg
= MXC_CCM_CCGR0
,
937 .enable_shift
= MXC_CCM_CCGRx_CG8_OFFSET
,
938 .enable
= _clk_ccgr_enable
,
939 .disable
= _clk_ccgr_disable_inwait
,
942 static struct clk ipu_sec_clk
= {
943 .parent
= &emi_fast_clk
,
944 .secondary
= &ahbmux1_clk
,
947 static struct clk ddr_hf_clk
= {
948 .parent
= &pll1_sw_clk
,
949 .get_rate
= _clk_ddr_hf_get_rate
,
952 static struct clk ddr_clk
= {
953 .parent
= &ddr_hf_clk
,
956 /* clock definitions for MIPI HSC unit which has been removed
957 * from documentation, but not from hardware
959 static int _clk_hsc_enable(struct clk
*clk
)
963 _clk_ccgr_enable(clk
);
964 /* Handshake with IPU when certain clock rates are changed. */
965 reg
= __raw_readl(MXC_CCM_CCDR
);
966 reg
&= ~MXC_CCM_CCDR_HSC_HS_MASK
;
967 __raw_writel(reg
, MXC_CCM_CCDR
);
969 reg
= __raw_readl(MXC_CCM_CLPCR
);
970 reg
&= ~MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS
;
971 __raw_writel(reg
, MXC_CCM_CLPCR
);
976 static void _clk_hsc_disable(struct clk
*clk
)
980 _clk_ccgr_disable(clk
);
981 /* No handshake with HSC as its not enabled. */
982 reg
= __raw_readl(MXC_CCM_CCDR
);
983 reg
|= MXC_CCM_CCDR_HSC_HS_MASK
;
984 __raw_writel(reg
, MXC_CCM_CCDR
);
986 reg
= __raw_readl(MXC_CCM_CLPCR
);
987 reg
|= MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS
;
988 __raw_writel(reg
, MXC_CCM_CLPCR
);
991 static struct clk mipi_hsp_clk
= {
993 .enable_reg
= MXC_CCM_CCGR4
,
994 .enable_shift
= MXC_CCM_CCGRx_CG6_OFFSET
,
995 .enable
= _clk_hsc_enable
,
996 .disable
= _clk_hsc_disable
,
997 .secondary
= &mipi_hsc1_clk
,
1000 #define DEFINE_CLOCK_CCGR(name, i, er, es, pfx, p, s) \
1001 static struct clk name = { \
1004 .enable_shift = es, \
1005 .get_rate = pfx##_get_rate, \
1006 .set_rate = pfx##_set_rate, \
1007 .round_rate = pfx##_round_rate, \
1008 .set_parent = pfx##_set_parent, \
1009 .enable = _clk_ccgr_enable, \
1010 .disable = _clk_ccgr_disable, \
1015 #define DEFINE_CLOCK_MAX(name, i, er, es, pfx, p, s) \
1016 static struct clk name = { \
1019 .enable_shift = es, \
1020 .get_rate = pfx##_get_rate, \
1021 .set_rate = pfx##_set_rate, \
1022 .set_parent = pfx##_set_parent, \
1023 .enable = _clk_max_enable, \
1024 .disable = _clk_max_disable, \
1029 #define CLK_GET_RATE(name, nr, bitsname) \
1030 static unsigned long clk_##name##_get_rate(struct clk *clk) \
1032 u32 reg, pred, podf; \
1034 reg = __raw_readl(MXC_CCM_CSCDR##nr); \
1035 pred = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK) \
1036 >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET; \
1037 podf = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK) \
1038 >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET; \
1040 return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent), \
1041 (pred + 1) * (podf + 1)); \
1044 #define CLK_SET_PARENT(name, nr, bitsname) \
1045 static int clk_##name##_set_parent(struct clk *clk, struct clk *parent) \
1049 mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, \
1050 &pll3_sw_clk, &lp_apm_clk); \
1051 reg = __raw_readl(MXC_CCM_CSCMR##nr) & \
1052 ~MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_MASK; \
1053 reg |= mux << MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_OFFSET; \
1054 __raw_writel(reg, MXC_CCM_CSCMR##nr); \
1059 #define CLK_SET_RATE(name, nr, bitsname) \
1060 static int clk_##name##_set_rate(struct clk *clk, unsigned long rate) \
1062 u32 reg, div, parent_rate; \
1063 u32 pre = 0, post = 0; \
1065 parent_rate = clk_get_rate(clk->parent); \
1066 div = parent_rate / rate; \
1068 if ((parent_rate / div) != rate) \
1071 __calc_pre_post_dividers(div, &pre, &post, \
1072 (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK >> \
1073 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET) + 1, \
1074 (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK >> \
1075 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET) + 1);\
1077 /* Set sdhc1 clock divider */ \
1078 reg = __raw_readl(MXC_CCM_CSCDR##nr) & \
1079 ~(MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK \
1080 | MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK); \
1081 reg |= (post - 1) << \
1082 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET; \
1083 reg |= (pre - 1) << \
1084 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET; \
1085 __raw_writel(reg, MXC_CCM_CSCDR##nr); \
1091 CLK_GET_RATE(uart
, 1, UART
)
1092 CLK_SET_PARENT(uart
, 1, UART
)
1094 static struct clk uart_root_clk
= {
1095 .parent
= &pll2_sw_clk
,
1096 .get_rate
= clk_uart_get_rate
,
1097 .set_parent
= clk_uart_set_parent
,
1101 CLK_GET_RATE(usboh3
, 1, USBOH3
)
1102 CLK_SET_PARENT(usboh3
, 1, USBOH3
)
1104 static struct clk usboh3_clk
= {
1105 .parent
= &pll2_sw_clk
,
1106 .get_rate
= clk_usboh3_get_rate
,
1107 .set_parent
= clk_usboh3_set_parent
,
1108 .enable
= _clk_ccgr_enable
,
1109 .disable
= _clk_ccgr_disable
,
1110 .enable_reg
= MXC_CCM_CCGR2
,
1111 .enable_shift
= MXC_CCM_CCGRx_CG14_OFFSET
,
1114 static struct clk usb_ahb_clk
= {
1116 .enable
= _clk_ccgr_enable
,
1117 .disable
= _clk_ccgr_disable
,
1118 .enable_reg
= MXC_CCM_CCGR2
,
1119 .enable_shift
= MXC_CCM_CCGRx_CG13_OFFSET
,
1122 static int clk_usb_phy1_set_parent(struct clk
*clk
, struct clk
*parent
)
1126 reg
= __raw_readl(MXC_CCM_CSCMR1
) & ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL
;
1128 if (parent
== &pll3_sw_clk
)
1129 reg
|= 1 << MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET
;
1131 __raw_writel(reg
, MXC_CCM_CSCMR1
);
1136 static struct clk usb_phy1_clk
= {
1137 .parent
= &pll3_sw_clk
,
1138 .set_parent
= clk_usb_phy1_set_parent
,
1139 .enable
= _clk_ccgr_enable
,
1140 .enable_reg
= MXC_CCM_CCGR2
,
1141 .enable_shift
= MXC_CCM_CCGRx_CG0_OFFSET
,
1142 .disable
= _clk_ccgr_disable
,
1146 CLK_GET_RATE(ecspi
, 2, CSPI
)
1147 CLK_SET_PARENT(ecspi
, 1, CSPI
)
1149 static struct clk ecspi_main_clk
= {
1150 .parent
= &pll3_sw_clk
,
1151 .get_rate
= clk_ecspi_get_rate
,
1152 .set_parent
= clk_ecspi_set_parent
,
1156 CLK_GET_RATE(esdhc1
, 1, ESDHC1_MSHC1
)
1157 CLK_SET_PARENT(esdhc1
, 1, ESDHC1_MSHC1
)
1158 CLK_SET_RATE(esdhc1
, 1, ESDHC1_MSHC1
)
1161 CLK_GET_RATE(esdhc2
, 1, ESDHC2_MSHC2
)
1162 CLK_SET_PARENT(esdhc2
, 1, ESDHC2_MSHC2
)
1163 CLK_SET_RATE(esdhc2
, 1, ESDHC2_MSHC2
)
1165 static int clk_esdhc3_set_parent(struct clk
*clk
, struct clk
*parent
)
1169 reg
= __raw_readl(MXC_CCM_CSCMR1
);
1170 if (parent
== &esdhc1_clk
)
1171 reg
&= ~MXC_CCM_CSCMR1_ESDHC3_CLK_SEL
;
1172 else if (parent
== &esdhc2_clk
)
1173 reg
|= MXC_CCM_CSCMR1_ESDHC3_CLK_SEL
;
1176 __raw_writel(reg
, MXC_CCM_CSCMR1
);
1181 static int clk_esdhc4_set_parent(struct clk
*clk
, struct clk
*parent
)
1185 reg
= __raw_readl(MXC_CCM_CSCMR1
);
1186 if (parent
== &esdhc1_clk
)
1187 reg
&= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL
;
1188 else if (parent
== &esdhc2_clk
)
1189 reg
|= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL
;
1192 __raw_writel(reg
, MXC_CCM_CSCMR1
);
1198 static int clk_esdhc2_mx53_set_parent(struct clk
*clk
, struct clk
*parent
)
1202 reg
= __raw_readl(MXC_CCM_CSCMR1
);
1203 if (parent
== &esdhc1_clk
)
1204 reg
&= ~MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL
;
1205 else if (parent
== &esdhc3_mx53_clk
)
1206 reg
|= MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL
;
1209 __raw_writel(reg
, MXC_CCM_CSCMR1
);
1214 CLK_GET_RATE(esdhc3_mx53
, 1, ESDHC3_MX53
)
1215 CLK_SET_PARENT(esdhc3_mx53
, 1, ESDHC3_MX53
)
1216 CLK_SET_RATE(esdhc3_mx53
, 1, ESDHC3_MX53
)
1218 static int clk_esdhc4_mx53_set_parent(struct clk
*clk
, struct clk
*parent
)
1222 reg
= __raw_readl(MXC_CCM_CSCMR1
);
1223 if (parent
== &esdhc1_clk
)
1224 reg
&= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL
;
1225 else if (parent
== &esdhc3_mx53_clk
)
1226 reg
|= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL
;
1229 __raw_writel(reg
, MXC_CCM_CSCMR1
);
1234 #define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s) \
1235 static struct clk name = { \
1238 .enable_shift = es, \
1247 #define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s) \
1248 DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, _clk_ccgr_enable, _clk_ccgr_disable, p, s)
1250 /* Shared peripheral bus arbiter */
1251 DEFINE_CLOCK(spba_clk
, 0, MXC_CCM_CCGR5
, MXC_CCM_CCGRx_CG0_OFFSET
,
1252 NULL
, NULL
, &ipg_clk
, NULL
);
1255 DEFINE_CLOCK(uart1_ipg_clk
, 0, MXC_CCM_CCGR1
, MXC_CCM_CCGRx_CG3_OFFSET
,
1256 NULL
, NULL
, &ipg_clk
, &aips_tz1_clk
);
1257 DEFINE_CLOCK(uart2_ipg_clk
, 1, MXC_CCM_CCGR1
, MXC_CCM_CCGRx_CG5_OFFSET
,
1258 NULL
, NULL
, &ipg_clk
, &aips_tz1_clk
);
1259 DEFINE_CLOCK(uart3_ipg_clk
, 2, MXC_CCM_CCGR1
, MXC_CCM_CCGRx_CG7_OFFSET
,
1260 NULL
, NULL
, &ipg_clk
, &spba_clk
);
1261 DEFINE_CLOCK(uart4_ipg_clk
, 3, MXC_CCM_CCGR7
, MXC_CCM_CCGRx_CG4_OFFSET
,
1262 NULL
, NULL
, &ipg_clk
, &spba_clk
);
1263 DEFINE_CLOCK(uart5_ipg_clk
, 4, MXC_CCM_CCGR7
, MXC_CCM_CCGRx_CG6_OFFSET
,
1264 NULL
, NULL
, &ipg_clk
, &spba_clk
);
1265 DEFINE_CLOCK(uart1_clk
, 0, MXC_CCM_CCGR1
, MXC_CCM_CCGRx_CG4_OFFSET
,
1266 NULL
, NULL
, &uart_root_clk
, &uart1_ipg_clk
);
1267 DEFINE_CLOCK(uart2_clk
, 1, MXC_CCM_CCGR1
, MXC_CCM_CCGRx_CG6_OFFSET
,
1268 NULL
, NULL
, &uart_root_clk
, &uart2_ipg_clk
);
1269 DEFINE_CLOCK(uart3_clk
, 2, MXC_CCM_CCGR1
, MXC_CCM_CCGRx_CG8_OFFSET
,
1270 NULL
, NULL
, &uart_root_clk
, &uart3_ipg_clk
);
1271 DEFINE_CLOCK(uart4_clk
, 3, MXC_CCM_CCGR7
, MXC_CCM_CCGRx_CG5_OFFSET
,
1272 NULL
, NULL
, &uart_root_clk
, &uart4_ipg_clk
);
1273 DEFINE_CLOCK(uart5_clk
, 4, MXC_CCM_CCGR7
, MXC_CCM_CCGRx_CG7_OFFSET
,
1274 NULL
, NULL
, &uart_root_clk
, &uart5_ipg_clk
);
1277 DEFINE_CLOCK(gpt_ipg_clk
, 0, MXC_CCM_CCGR2
, MXC_CCM_CCGRx_CG10_OFFSET
,
1278 NULL
, NULL
, &ipg_clk
, NULL
);
1279 DEFINE_CLOCK(gpt_clk
, 0, MXC_CCM_CCGR2
, MXC_CCM_CCGRx_CG9_OFFSET
,
1280 NULL
, NULL
, &ipg_clk
, &gpt_ipg_clk
);
1282 DEFINE_CLOCK(pwm1_clk
, 0, MXC_CCM_CCGR2
, MXC_CCM_CCGRx_CG6_OFFSET
,
1283 NULL
, NULL
, &ipg_clk
, NULL
);
1284 DEFINE_CLOCK(pwm2_clk
, 0, MXC_CCM_CCGR2
, MXC_CCM_CCGRx_CG8_OFFSET
,
1285 NULL
, NULL
, &ipg_clk
, NULL
);
1288 DEFINE_CLOCK(i2c1_clk
, 0, MXC_CCM_CCGR1
, MXC_CCM_CCGRx_CG9_OFFSET
,
1289 NULL
, NULL
, &ipg_perclk
, NULL
);
1290 DEFINE_CLOCK(i2c2_clk
, 1, MXC_CCM_CCGR1
, MXC_CCM_CCGRx_CG10_OFFSET
,
1291 NULL
, NULL
, &ipg_perclk
, NULL
);
1292 DEFINE_CLOCK(hsi2c_clk
, 0, MXC_CCM_CCGR1
, MXC_CCM_CCGRx_CG11_OFFSET
,
1293 NULL
, NULL
, &ipg_clk
, NULL
);
1294 DEFINE_CLOCK(i2c3_mx53_clk
, 0, MXC_CCM_CCGR1
, MXC_CCM_CCGRx_CG11_OFFSET
,
1295 NULL
, NULL
, &ipg_perclk
, NULL
);
1298 DEFINE_CLOCK(fec_clk
, 0, MXC_CCM_CCGR2
, MXC_CCM_CCGRx_CG12_OFFSET
,
1299 NULL
, NULL
, &ipg_clk
, NULL
);
1302 DEFINE_CLOCK_CCGR(nfc_clk
, 0, MXC_CCM_CCGR5
, MXC_CCM_CCGRx_CG10_OFFSET
,
1303 clk_nfc
, &emi_slow_clk
, NULL
);
1306 DEFINE_CLOCK(ssi1_ipg_clk
, 0, MXC_CCM_CCGR3
, MXC_CCM_CCGRx_CG8_OFFSET
,
1307 NULL
, NULL
, &ipg_clk
, NULL
);
1308 DEFINE_CLOCK(ssi1_clk
, 0, MXC_CCM_CCGR3
, MXC_CCM_CCGRx_CG9_OFFSET
,
1309 NULL
, NULL
, &pll3_sw_clk
, &ssi1_ipg_clk
);
1310 DEFINE_CLOCK(ssi2_ipg_clk
, 1, MXC_CCM_CCGR3
, MXC_CCM_CCGRx_CG10_OFFSET
,
1311 NULL
, NULL
, &ipg_clk
, NULL
);
1312 DEFINE_CLOCK(ssi2_clk
, 1, MXC_CCM_CCGR3
, MXC_CCM_CCGRx_CG11_OFFSET
,
1313 NULL
, NULL
, &pll3_sw_clk
, &ssi2_ipg_clk
);
1314 DEFINE_CLOCK(ssi3_ipg_clk
, 2, MXC_CCM_CCGR3
, MXC_CCM_CCGRx_CG12_OFFSET
,
1315 NULL
, NULL
, &ipg_clk
, NULL
);
1316 DEFINE_CLOCK(ssi3_clk
, 2, MXC_CCM_CCGR3
, MXC_CCM_CCGRx_CG13_OFFSET
,
1317 NULL
, NULL
, &pll3_sw_clk
, &ssi3_ipg_clk
);
1320 DEFINE_CLOCK_FULL(ecspi1_ipg_clk
, 0, MXC_CCM_CCGR4
, MXC_CCM_CCGRx_CG9_OFFSET
,
1321 NULL
, NULL
, _clk_ccgr_enable_inrun
, _clk_ccgr_disable
,
1322 &ipg_clk
, &spba_clk
);
1323 DEFINE_CLOCK(ecspi1_clk
, 0, MXC_CCM_CCGR4
, MXC_CCM_CCGRx_CG10_OFFSET
,
1324 NULL
, NULL
, &ecspi_main_clk
, &ecspi1_ipg_clk
);
1325 DEFINE_CLOCK_FULL(ecspi2_ipg_clk
, 0, MXC_CCM_CCGR4
, MXC_CCM_CCGRx_CG11_OFFSET
,
1326 NULL
, NULL
, _clk_ccgr_enable_inrun
, _clk_ccgr_disable
,
1327 &ipg_clk
, &aips_tz2_clk
);
1328 DEFINE_CLOCK(ecspi2_clk
, 0, MXC_CCM_CCGR4
, MXC_CCM_CCGRx_CG12_OFFSET
,
1329 NULL
, NULL
, &ecspi_main_clk
, &ecspi2_ipg_clk
);
1332 DEFINE_CLOCK(cspi_ipg_clk
, 0, MXC_CCM_CCGR4
, MXC_CCM_CCGRx_CG9_OFFSET
,
1333 NULL
, NULL
, &ipg_clk
, &aips_tz2_clk
);
1334 DEFINE_CLOCK(cspi_clk
, 0, MXC_CCM_CCGR4
, MXC_CCM_CCGRx_CG13_OFFSET
,
1335 NULL
, NULL
, &ipg_clk
, &cspi_ipg_clk
);
1338 DEFINE_CLOCK(sdma_clk
, 1, MXC_CCM_CCGR4
, MXC_CCM_CCGRx_CG15_OFFSET
,
1339 NULL
, NULL
, &ahb_clk
, NULL
);
1342 DEFINE_CLOCK_FULL(esdhc1_ipg_clk
, 0, MXC_CCM_CCGR3
, MXC_CCM_CCGRx_CG0_OFFSET
,
1343 NULL
, NULL
, _clk_max_enable
, _clk_max_disable
, &ipg_clk
, NULL
);
1344 DEFINE_CLOCK_MAX(esdhc1_clk
, 0, MXC_CCM_CCGR3
, MXC_CCM_CCGRx_CG1_OFFSET
,
1345 clk_esdhc1
, &pll2_sw_clk
, &esdhc1_ipg_clk
);
1346 DEFINE_CLOCK_FULL(esdhc2_ipg_clk
, 1, MXC_CCM_CCGR3
, MXC_CCM_CCGRx_CG2_OFFSET
,
1347 NULL
, NULL
, _clk_max_enable
, _clk_max_disable
, &ipg_clk
, NULL
);
1348 DEFINE_CLOCK_FULL(esdhc3_ipg_clk
, 2, MXC_CCM_CCGR3
, MXC_CCM_CCGRx_CG4_OFFSET
,
1349 NULL
, NULL
, _clk_max_enable
, _clk_max_disable
, &ipg_clk
, NULL
);
1350 DEFINE_CLOCK_FULL(esdhc4_ipg_clk
, 3, MXC_CCM_CCGR3
, MXC_CCM_CCGRx_CG6_OFFSET
,
1351 NULL
, NULL
, _clk_max_enable
, _clk_max_disable
, &ipg_clk
, NULL
);
1354 DEFINE_CLOCK_MAX(esdhc2_clk
, 1, MXC_CCM_CCGR3
, MXC_CCM_CCGRx_CG3_OFFSET
,
1355 clk_esdhc2
, &pll2_sw_clk
, &esdhc2_ipg_clk
);
1357 static struct clk esdhc3_clk
= {
1359 .parent
= &esdhc1_clk
,
1360 .set_parent
= clk_esdhc3_set_parent
,
1361 .enable_reg
= MXC_CCM_CCGR3
,
1362 .enable_shift
= MXC_CCM_CCGRx_CG5_OFFSET
,
1363 .enable
= _clk_max_enable
,
1364 .disable
= _clk_max_disable
,
1365 .secondary
= &esdhc3_ipg_clk
,
1367 static struct clk esdhc4_clk
= {
1369 .parent
= &esdhc1_clk
,
1370 .set_parent
= clk_esdhc4_set_parent
,
1371 .enable_reg
= MXC_CCM_CCGR3
,
1372 .enable_shift
= MXC_CCM_CCGRx_CG7_OFFSET
,
1373 .enable
= _clk_max_enable
,
1374 .disable
= _clk_max_disable
,
1375 .secondary
= &esdhc4_ipg_clk
,
1379 static struct clk esdhc2_mx53_clk
= {
1381 .parent
= &esdhc1_clk
,
1382 .set_parent
= clk_esdhc2_mx53_set_parent
,
1383 .enable_reg
= MXC_CCM_CCGR3
,
1384 .enable_shift
= MXC_CCM_CCGRx_CG3_OFFSET
,
1385 .enable
= _clk_max_enable
,
1386 .disable
= _clk_max_disable
,
1387 .secondary
= &esdhc3_ipg_clk
,
1390 DEFINE_CLOCK_MAX(esdhc3_mx53_clk
, 2, MXC_CCM_CCGR3
, MXC_CCM_CCGRx_CG5_OFFSET
,
1391 clk_esdhc3_mx53
, &pll2_sw_clk
, &esdhc2_ipg_clk
);
1393 static struct clk esdhc4_mx53_clk
= {
1395 .parent
= &esdhc1_clk
,
1396 .set_parent
= clk_esdhc4_mx53_set_parent
,
1397 .enable_reg
= MXC_CCM_CCGR3
,
1398 .enable_shift
= MXC_CCM_CCGRx_CG7_OFFSET
,
1399 .enable
= _clk_max_enable
,
1400 .disable
= _clk_max_disable
,
1401 .secondary
= &esdhc4_ipg_clk
,
1404 DEFINE_CLOCK(mipi_esc_clk
, 0, MXC_CCM_CCGR4
, MXC_CCM_CCGRx_CG5_OFFSET
, NULL
, NULL
, NULL
, &pll2_sw_clk
);
1405 DEFINE_CLOCK(mipi_hsc2_clk
, 0, MXC_CCM_CCGR4
, MXC_CCM_CCGRx_CG4_OFFSET
, NULL
, NULL
, &mipi_esc_clk
, &pll2_sw_clk
);
1406 DEFINE_CLOCK(mipi_hsc1_clk
, 0, MXC_CCM_CCGR4
, MXC_CCM_CCGRx_CG3_OFFSET
, NULL
, NULL
, &mipi_hsc2_clk
, &pll2_sw_clk
);
1409 DEFINE_CLOCK_FULL(ipu_clk
, 0, MXC_CCM_CCGR5
, MXC_CCM_CCGRx_CG5_OFFSET
,
1410 NULL
, NULL
, clk_ipu_enable
, clk_ipu_disable
, &ahb_clk
, &ipu_sec_clk
);
1412 DEFINE_CLOCK_FULL(emi_fast_clk
, 0, MXC_CCM_CCGR5
, MXC_CCM_CCGRx_CG7_OFFSET
,
1413 NULL
, NULL
, _clk_ccgr_enable
, _clk_ccgr_disable_inwait
,
1416 DEFINE_CLOCK(ipu_di0_clk
, 0, MXC_CCM_CCGR6
, MXC_CCM_CCGRx_CG5_OFFSET
,
1417 NULL
, NULL
, &pll3_sw_clk
, NULL
);
1418 DEFINE_CLOCK(ipu_di1_clk
, 0, MXC_CCM_CCGR6
, MXC_CCM_CCGRx_CG6_OFFSET
,
1419 NULL
, NULL
, &pll3_sw_clk
, NULL
);
1422 DEFINE_CLOCK(pata_clk
, 0, MXC_CCM_CCGR4
, MXC_CCM_CCGRx_CG0_OFFSET
,
1423 NULL
, NULL
, &ipg_clk
, &spba_clk
);
1425 #define _REGISTER_CLOCK(d, n, c) \
1432 static struct clk_lookup mx51_lookups
[] = {
1433 /* i.mx51 has the i.mx21 type uart */
1434 _REGISTER_CLOCK("imx21-uart.0", NULL
, uart1_clk
)
1435 _REGISTER_CLOCK("imx21-uart.1", NULL
, uart2_clk
)
1436 _REGISTER_CLOCK("imx21-uart.2", NULL
, uart3_clk
)
1437 _REGISTER_CLOCK(NULL
, "gpt", gpt_clk
)
1438 /* i.mx51 has the i.mx27 type fec */
1439 _REGISTER_CLOCK("imx27-fec.0", NULL
, fec_clk
)
1440 _REGISTER_CLOCK("mxc_pwm.0", "pwm", pwm1_clk
)
1441 _REGISTER_CLOCK("mxc_pwm.1", "pwm", pwm2_clk
)
1442 _REGISTER_CLOCK("imx-i2c.0", NULL
, i2c1_clk
)
1443 _REGISTER_CLOCK("imx-i2c.1", NULL
, i2c2_clk
)
1444 _REGISTER_CLOCK("imx-i2c.2", NULL
, hsi2c_clk
)
1445 _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk
)
1446 _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_ahb_clk
)
1447 _REGISTER_CLOCK("mxc-ehci.0", "usb_phy1", usb_phy1_clk
)
1448 _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk
)
1449 _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_ahb_clk
)
1450 _REGISTER_CLOCK("mxc-ehci.2", "usb", usboh3_clk
)
1451 _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_ahb_clk
)
1452 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk
)
1453 _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk
)
1454 _REGISTER_CLOCK("imx-keypad", NULL
, dummy_clk
)
1455 _REGISTER_CLOCK("mxc_nand", NULL
, nfc_clk
)
1456 _REGISTER_CLOCK("imx-ssi.0", NULL
, ssi1_clk
)
1457 _REGISTER_CLOCK("imx-ssi.1", NULL
, ssi2_clk
)
1458 _REGISTER_CLOCK("imx-ssi.2", NULL
, ssi3_clk
)
1459 /* i.mx51 has the i.mx35 type sdma */
1460 _REGISTER_CLOCK("imx35-sdma", NULL
, sdma_clk
)
1461 _REGISTER_CLOCK(NULL
, "ckih", ckih_clk
)
1462 _REGISTER_CLOCK(NULL
, "ckih2", ckih2_clk
)
1463 _REGISTER_CLOCK(NULL
, "gpt_32k", gpt_32k_clk
)
1464 _REGISTER_CLOCK("imx51-ecspi.0", NULL
, ecspi1_clk
)
1465 _REGISTER_CLOCK("imx51-ecspi.1", NULL
, ecspi2_clk
)
1466 /* i.mx51 has the i.mx35 type cspi */
1467 _REGISTER_CLOCK("imx35-cspi.0", NULL
, cspi_clk
)
1468 _REGISTER_CLOCK("sdhci-esdhc-imx51.0", NULL
, esdhc1_clk
)
1469 _REGISTER_CLOCK("sdhci-esdhc-imx51.1", NULL
, esdhc2_clk
)
1470 _REGISTER_CLOCK("sdhci-esdhc-imx51.2", NULL
, esdhc3_clk
)
1471 _REGISTER_CLOCK("sdhci-esdhc-imx51.3", NULL
, esdhc4_clk
)
1472 _REGISTER_CLOCK(NULL
, "cpu_clk", cpu_clk
)
1473 _REGISTER_CLOCK(NULL
, "iim_clk", iim_clk
)
1474 _REGISTER_CLOCK("imx2-wdt.0", NULL
, dummy_clk
)
1475 _REGISTER_CLOCK("imx2-wdt.1", NULL
, dummy_clk
)
1476 _REGISTER_CLOCK(NULL
, "mipi_hsp", mipi_hsp_clk
)
1477 _REGISTER_CLOCK("imx-ipuv3", NULL
, ipu_clk
)
1478 _REGISTER_CLOCK("imx-ipuv3", "di0", ipu_di0_clk
)
1479 _REGISTER_CLOCK("imx-ipuv3", "di1", ipu_di1_clk
)
1480 _REGISTER_CLOCK(NULL
, "gpc_dvfs", gpc_dvfs_clk
)
1481 _REGISTER_CLOCK("pata_imx", NULL
, pata_clk
)
1484 static struct clk_lookup mx53_lookups
[] = {
1485 /* i.mx53 has the i.mx21 type uart */
1486 _REGISTER_CLOCK("imx21-uart.0", NULL
, uart1_clk
)
1487 _REGISTER_CLOCK("imx21-uart.1", NULL
, uart2_clk
)
1488 _REGISTER_CLOCK("imx21-uart.2", NULL
, uart3_clk
)
1489 _REGISTER_CLOCK("imx21-uart.3", NULL
, uart4_clk
)
1490 _REGISTER_CLOCK("imx21-uart.4", NULL
, uart5_clk
)
1491 _REGISTER_CLOCK(NULL
, "gpt", gpt_clk
)
1492 /* i.mx53 has the i.mx25 type fec */
1493 _REGISTER_CLOCK("imx25-fec.0", NULL
, fec_clk
)
1494 _REGISTER_CLOCK(NULL
, "iim_clk", iim_clk
)
1495 _REGISTER_CLOCK("imx-i2c.0", NULL
, i2c1_clk
)
1496 _REGISTER_CLOCK("imx-i2c.1", NULL
, i2c2_clk
)
1497 _REGISTER_CLOCK("imx-i2c.2", NULL
, i2c3_mx53_clk
)
1498 /* i.mx53 has the i.mx51 type ecspi */
1499 _REGISTER_CLOCK("imx51-ecspi.0", NULL
, ecspi1_clk
)
1500 _REGISTER_CLOCK("imx51-ecspi.1", NULL
, ecspi2_clk
)
1501 /* i.mx53 has the i.mx25 type cspi */
1502 _REGISTER_CLOCK("imx35-cspi.0", NULL
, cspi_clk
)
1503 _REGISTER_CLOCK("sdhci-esdhc-imx53.0", NULL
, esdhc1_clk
)
1504 _REGISTER_CLOCK("sdhci-esdhc-imx53.1", NULL
, esdhc2_mx53_clk
)
1505 _REGISTER_CLOCK("sdhci-esdhc-imx53.2", NULL
, esdhc3_mx53_clk
)
1506 _REGISTER_CLOCK("sdhci-esdhc-imx53.3", NULL
, esdhc4_mx53_clk
)
1507 _REGISTER_CLOCK("imx2-wdt.0", NULL
, dummy_clk
)
1508 _REGISTER_CLOCK("imx2-wdt.1", NULL
, dummy_clk
)
1509 /* i.mx53 has the i.mx35 type sdma */
1510 _REGISTER_CLOCK("imx35-sdma", NULL
, sdma_clk
)
1511 _REGISTER_CLOCK("imx-ssi.0", NULL
, ssi1_clk
)
1512 _REGISTER_CLOCK("imx-ssi.1", NULL
, ssi2_clk
)
1513 _REGISTER_CLOCK("imx-ssi.2", NULL
, ssi3_clk
)
1514 _REGISTER_CLOCK("imx-keypad", NULL
, dummy_clk
)
1515 _REGISTER_CLOCK("pata_imx", NULL
, pata_clk
)
1518 static void clk_tree_init(void)
1522 ipg_perclk
.set_parent(&ipg_perclk
, &lp_apm_clk
);
1525 * Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at
1526 * 8MHz, its derived from lp_apm.
1528 * FIXME: Verify if true for all boards
1530 reg
= __raw_readl(MXC_CCM_CBCDR
);
1531 reg
&= ~MXC_CCM_CBCDR_PERCLK_PRED1_MASK
;
1532 reg
&= ~MXC_CCM_CBCDR_PERCLK_PRED2_MASK
;
1533 reg
&= ~MXC_CCM_CBCDR_PERCLK_PODF_MASK
;
1534 reg
|= (2 << MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET
);
1535 __raw_writel(reg
, MXC_CCM_CBCDR
);
1538 int __init
mx51_clocks_init(unsigned long ckil
, unsigned long osc
,
1539 unsigned long ckih1
, unsigned long ckih2
)
1543 external_low_reference
= ckil
;
1544 external_high_reference
= ckih1
;
1545 ckih2_reference
= ckih2
;
1546 oscillator_reference
= osc
;
1548 for (i
= 0; i
< ARRAY_SIZE(mx51_lookups
); i
++)
1549 clkdev_add(&mx51_lookups
[i
]);
1553 clk_enable(&cpu_clk
);
1554 clk_enable(&main_bus_clk
);
1556 clk_enable(&iim_clk
);
1557 imx_print_silicon_rev("i.MX51", mx51_revision());
1558 clk_disable(&iim_clk
);
1560 /* move usb_phy_clk to 24MHz */
1561 clk_set_parent(&usb_phy1_clk
, &osc_clk
);
1563 /* set the usboh3_clk parent to pll2_sw_clk */
1564 clk_set_parent(&usboh3_clk
, &pll2_sw_clk
);
1566 /* Set SDHC parents to be PLL2 */
1567 clk_set_parent(&esdhc1_clk
, &pll2_sw_clk
);
1568 clk_set_parent(&esdhc2_clk
, &pll2_sw_clk
);
1570 /* set SDHC root clock as 166.25MHZ*/
1571 clk_set_rate(&esdhc1_clk
, 166250000);
1572 clk_set_rate(&esdhc2_clk
, 166250000);
1575 mxc_timer_init(&gpt_clk
, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR
),
1580 int __init
mx53_clocks_init(unsigned long ckil
, unsigned long osc
,
1581 unsigned long ckih1
, unsigned long ckih2
)
1585 external_low_reference
= ckil
;
1586 external_high_reference
= ckih1
;
1587 ckih2_reference
= ckih2
;
1588 oscillator_reference
= osc
;
1590 for (i
= 0; i
< ARRAY_SIZE(mx53_lookups
); i
++)
1591 clkdev_add(&mx53_lookups
[i
]);
1595 clk_set_parent(&uart_root_clk
, &pll3_sw_clk
);
1596 clk_enable(&cpu_clk
);
1597 clk_enable(&main_bus_clk
);
1599 clk_enable(&iim_clk
);
1600 imx_print_silicon_rev("i.MX53", mx53_revision());
1601 clk_disable(&iim_clk
);
1603 /* Set SDHC parents to be PLL2 */
1604 clk_set_parent(&esdhc1_clk
, &pll2_sw_clk
);
1605 clk_set_parent(&esdhc3_mx53_clk
, &pll2_sw_clk
);
1607 /* set SDHC root clock as 200MHZ*/
1608 clk_set_rate(&esdhc1_clk
, 200000000);
1609 clk_set_rate(&esdhc3_mx53_clk
, 200000000);
1612 mxc_timer_init(&gpt_clk
, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR
),