2 * arch/arm/mach-orion5x/ts78xx-setup.c
4 * Maintainer: Alexander Clouter <alex@digriz.org.uk>
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/sysfs.h>
14 #include <linux/platform_device.h>
15 #include <linux/mv643xx_eth.h>
16 #include <linux/ata_platform.h>
17 #include <linux/m48t86.h>
18 #include <linux/mtd/nand.h>
19 #include <linux/mtd/partitions.h>
20 #include <linux/timeriomem-rng.h>
21 #include <asm/mach-types.h>
22 #include <asm/mach/arch.h>
23 #include <asm/mach/map.h>
24 #include <mach/orion5x.h>
27 #include "ts78xx-fpga.h"
29 /*****************************************************************************
31 ****************************************************************************/
34 * FPGA - lives where the PCI bus would be at ORION5X_PCI_MEM_PHYS_BASE
36 #define TS78XX_FPGA_REGS_PHYS_BASE 0xe8000000
37 #define TS78XX_FPGA_REGS_VIRT_BASE 0xff900000
38 #define TS78XX_FPGA_REGS_SIZE SZ_1M
40 static struct ts78xx_fpga_data ts78xx_fpga
= {
43 /* .supports = ... - populated by ts78xx_fpga_supports() */
46 /*****************************************************************************
48 ****************************************************************************/
49 static struct map_desc ts78xx_io_desc
[] __initdata
= {
51 .virtual = TS78XX_FPGA_REGS_VIRT_BASE
,
52 .pfn
= __phys_to_pfn(TS78XX_FPGA_REGS_PHYS_BASE
),
53 .length
= TS78XX_FPGA_REGS_SIZE
,
58 void __init
ts78xx_map_io(void)
61 iotable_init(ts78xx_io_desc
, ARRAY_SIZE(ts78xx_io_desc
));
64 /*****************************************************************************
66 ****************************************************************************/
67 static struct mv643xx_eth_platform_data ts78xx_eth_data
= {
68 .phy_addr
= MV643XX_ETH_PHY_ADDR(0),
71 /*****************************************************************************
73 ****************************************************************************/
74 static struct mv_sata_platform_data ts78xx_sata_data
= {
78 /*****************************************************************************
79 * RTC M48T86 - nicked^Wborrowed from arch/arm/mach-ep93xx/ts72xx.c
80 ****************************************************************************/
81 #define TS_RTC_CTRL (TS78XX_FPGA_REGS_VIRT_BASE | 0x808)
82 #define TS_RTC_DATA (TS78XX_FPGA_REGS_VIRT_BASE | 0x80c)
84 static unsigned char ts78xx_ts_rtc_readbyte(unsigned long addr
)
86 writeb(addr
, TS_RTC_CTRL
);
87 return readb(TS_RTC_DATA
);
90 static void ts78xx_ts_rtc_writebyte(unsigned char value
, unsigned long addr
)
92 writeb(addr
, TS_RTC_CTRL
);
93 writeb(value
, TS_RTC_DATA
);
96 static struct m48t86_ops ts78xx_ts_rtc_ops
= {
97 .readbyte
= ts78xx_ts_rtc_readbyte
,
98 .writebyte
= ts78xx_ts_rtc_writebyte
,
101 static struct platform_device ts78xx_ts_rtc_device
= {
102 .name
= "rtc-m48t86",
105 .platform_data
= &ts78xx_ts_rtc_ops
,
111 * TS uses some of the user storage space on the RTC chip so see if it is
112 * present; as it's an optional feature at purchase time and not all boards
113 * will have it present
115 * I've used the method TS use in their rtc7800.c example for the detection
117 * TODO: track down a guinea pig without an RTC to see if we can work out a
118 * better RTC detection routine
120 static int ts78xx_ts_rtc_load(void)
123 unsigned char tmp_rtc0
, tmp_rtc1
;
125 tmp_rtc0
= ts78xx_ts_rtc_readbyte(126);
126 tmp_rtc1
= ts78xx_ts_rtc_readbyte(127);
128 ts78xx_ts_rtc_writebyte(0x00, 126);
129 ts78xx_ts_rtc_writebyte(0x55, 127);
130 if (ts78xx_ts_rtc_readbyte(127) == 0x55) {
131 ts78xx_ts_rtc_writebyte(0xaa, 127);
132 if (ts78xx_ts_rtc_readbyte(127) == 0xaa
133 && ts78xx_ts_rtc_readbyte(126) == 0x00) {
134 ts78xx_ts_rtc_writebyte(tmp_rtc0
, 126);
135 ts78xx_ts_rtc_writebyte(tmp_rtc1
, 127);
137 if (ts78xx_fpga
.supports
.ts_rtc
.init
== 0) {
138 rc
= platform_device_register(&ts78xx_ts_rtc_device
);
140 ts78xx_fpga
.supports
.ts_rtc
.init
= 1;
142 rc
= platform_device_add(&ts78xx_ts_rtc_device
);
151 static void ts78xx_ts_rtc_unload(void)
153 platform_device_del(&ts78xx_ts_rtc_device
);
156 /*****************************************************************************
158 ****************************************************************************/
159 #define TS_NAND_CTRL (TS78XX_FPGA_REGS_VIRT_BASE | 0x800) /* VIRT */
160 #define TS_NAND_DATA (TS78XX_FPGA_REGS_PHYS_BASE | 0x804) /* PHYS */
163 * hardware specific access to control-lines
166 * NAND_NCE: bit 0 -> bit 2
167 * NAND_CLE: bit 1 -> bit 1
168 * NAND_ALE: bit 2 -> bit 0
170 static void ts78xx_ts_nand_cmd_ctrl(struct mtd_info
*mtd
, int cmd
,
173 struct nand_chip
*this = mtd
->priv
;
175 if (ctrl
& NAND_CTRL_CHANGE
) {
178 bits
= (ctrl
& NAND_NCE
) << 2;
179 bits
|= ctrl
& NAND_CLE
;
180 bits
|= (ctrl
& NAND_ALE
) >> 2;
182 writeb((readb(TS_NAND_CTRL
) & ~0x7) | bits
, TS_NAND_CTRL
);
185 if (cmd
!= NAND_CMD_NONE
)
186 writeb(cmd
, this->IO_ADDR_W
);
189 static int ts78xx_ts_nand_dev_ready(struct mtd_info
*mtd
)
191 return readb(TS_NAND_CTRL
) & 0x20;
194 static void ts78xx_ts_nand_write_buf(struct mtd_info
*mtd
,
195 const uint8_t *buf
, int len
)
197 struct nand_chip
*chip
= mtd
->priv
;
198 void __iomem
*io_base
= chip
->IO_ADDR_W
;
199 unsigned long off
= ((unsigned long)buf
& 3);
203 sz
= min_t(int, 4 - off
, len
);
204 writesb(io_base
, buf
, sz
);
211 u32
*buf32
= (u32
*)buf
;
212 writesl(io_base
, buf32
, sz
);
218 writesb(io_base
, buf
, len
);
221 static void ts78xx_ts_nand_read_buf(struct mtd_info
*mtd
,
222 uint8_t *buf
, int len
)
224 struct nand_chip
*chip
= mtd
->priv
;
225 void __iomem
*io_base
= chip
->IO_ADDR_R
;
226 unsigned long off
= ((unsigned long)buf
& 3);
230 sz
= min_t(int, 4 - off
, len
);
231 readsb(io_base
, buf
, sz
);
238 u32
*buf32
= (u32
*)buf
;
239 readsl(io_base
, buf32
, sz
);
245 readsb(io_base
, buf
, len
);
248 const char *ts_nand_part_probes
[] = { "cmdlinepart", NULL
};
250 static struct mtd_partition ts78xx_ts_nand_parts
[] = {
255 .mask_flags
= MTD_WRITEABLE
,
258 .offset
= MTDPART_OFS_APPEND
,
262 .offset
= MTDPART_OFS_APPEND
,
266 .offset
= MTDPART_OFS_APPEND
,
267 .size
= MTDPART_SIZ_FULL
,
271 static struct platform_nand_data ts78xx_ts_nand_data
= {
274 .part_probe_types
= ts_nand_part_probes
,
275 .partitions
= ts78xx_ts_nand_parts
,
276 .nr_partitions
= ARRAY_SIZE(ts78xx_ts_nand_parts
),
278 .bbt_options
= NAND_BBT_USE_FLASH
,
282 * The HW ECC offloading functions, used to give about a 9%
283 * performance increase for 'dd if=/dev/mtdblockX' and 5% for
284 * nanddump. This all however was changed by git commit
285 * e6cf5df1838c28bb060ac45b5585e48e71bbc740 so now there is
286 * no performance advantage to be had so we no longer bother
288 .cmd_ctrl
= ts78xx_ts_nand_cmd_ctrl
,
289 .dev_ready
= ts78xx_ts_nand_dev_ready
,
290 .write_buf
= ts78xx_ts_nand_write_buf
,
291 .read_buf
= ts78xx_ts_nand_read_buf
,
295 static struct resource ts78xx_ts_nand_resources
= {
296 .start
= TS_NAND_DATA
,
297 .end
= TS_NAND_DATA
+ 4,
298 .flags
= IORESOURCE_MEM
,
301 static struct platform_device ts78xx_ts_nand_device
= {
305 .platform_data
= &ts78xx_ts_nand_data
,
307 .resource
= &ts78xx_ts_nand_resources
,
311 static int ts78xx_ts_nand_load(void)
315 if (ts78xx_fpga
.supports
.ts_nand
.init
== 0) {
316 rc
= platform_device_register(&ts78xx_ts_nand_device
);
318 ts78xx_fpga
.supports
.ts_nand
.init
= 1;
320 rc
= platform_device_add(&ts78xx_ts_nand_device
);
325 static void ts78xx_ts_nand_unload(void)
327 platform_device_del(&ts78xx_ts_nand_device
);
330 /*****************************************************************************
332 ****************************************************************************/
333 #define TS_RNG_DATA (TS78XX_FPGA_REGS_PHYS_BASE | 0x044)
335 static struct resource ts78xx_ts_rng_resource
= {
336 .flags
= IORESOURCE_MEM
,
337 .start
= TS_RNG_DATA
,
338 .end
= TS_RNG_DATA
+ 4 - 1,
341 static struct timeriomem_rng_data ts78xx_ts_rng_data
= {
342 .period
= 1000000, /* one second */
345 static struct platform_device ts78xx_ts_rng_device
= {
346 .name
= "timeriomem_rng",
349 .platform_data
= &ts78xx_ts_rng_data
,
351 .resource
= &ts78xx_ts_rng_resource
,
355 static int ts78xx_ts_rng_load(void)
359 if (ts78xx_fpga
.supports
.ts_rng
.init
== 0) {
360 rc
= platform_device_register(&ts78xx_ts_rng_device
);
362 ts78xx_fpga
.supports
.ts_rng
.init
= 1;
364 rc
= platform_device_add(&ts78xx_ts_rng_device
);
369 static void ts78xx_ts_rng_unload(void)
371 platform_device_del(&ts78xx_ts_rng_device
);
374 /*****************************************************************************
375 * FPGA 'hotplug' support code
376 ****************************************************************************/
377 static void ts78xx_fpga_devices_zero_init(void)
379 ts78xx_fpga
.supports
.ts_rtc
.init
= 0;
380 ts78xx_fpga
.supports
.ts_nand
.init
= 0;
381 ts78xx_fpga
.supports
.ts_rng
.init
= 0;
384 static void ts78xx_fpga_supports(void)
386 /* TODO: put this 'table' into ts78xx-fpga.h */
387 switch (ts78xx_fpga
.id
) {
397 ts78xx_fpga
.supports
.ts_rtc
.present
= 1;
398 ts78xx_fpga
.supports
.ts_nand
.present
= 1;
399 ts78xx_fpga
.supports
.ts_rng
.present
= 1;
402 /* enable devices if magic matches */
403 switch ((ts78xx_fpga
.id
>> 8) & 0xffffff) {
404 case TS7800_FPGA_MAGIC
:
405 pr_warning("TS-7800 FPGA: unrecognized revision 0x%.2x\n",
406 ts78xx_fpga
.id
& 0xff);
407 ts78xx_fpga
.supports
.ts_rtc
.present
= 1;
408 ts78xx_fpga
.supports
.ts_nand
.present
= 1;
409 ts78xx_fpga
.supports
.ts_rng
.present
= 1;
412 ts78xx_fpga
.supports
.ts_rtc
.present
= 0;
413 ts78xx_fpga
.supports
.ts_nand
.present
= 0;
414 ts78xx_fpga
.supports
.ts_rng
.present
= 0;
419 static int ts78xx_fpga_load_devices(void)
423 if (ts78xx_fpga
.supports
.ts_rtc
.present
== 1) {
424 tmp
= ts78xx_ts_rtc_load();
426 pr_info("TS-78xx: RTC not registered\n");
427 ts78xx_fpga
.supports
.ts_rtc
.present
= 0;
431 if (ts78xx_fpga
.supports
.ts_nand
.present
== 1) {
432 tmp
= ts78xx_ts_nand_load();
434 pr_info("TS-78xx: NAND not registered\n");
435 ts78xx_fpga
.supports
.ts_nand
.present
= 0;
439 if (ts78xx_fpga
.supports
.ts_rng
.present
== 1) {
440 tmp
= ts78xx_ts_rng_load();
442 pr_info("TS-78xx: RNG not registered\n");
443 ts78xx_fpga
.supports
.ts_rng
.present
= 0;
451 static int ts78xx_fpga_unload_devices(void)
455 if (ts78xx_fpga
.supports
.ts_rtc
.present
== 1)
456 ts78xx_ts_rtc_unload();
457 if (ts78xx_fpga
.supports
.ts_nand
.present
== 1)
458 ts78xx_ts_nand_unload();
459 if (ts78xx_fpga
.supports
.ts_rng
.present
== 1)
460 ts78xx_ts_rng_unload();
465 static int ts78xx_fpga_load(void)
467 ts78xx_fpga
.id
= readl(TS78XX_FPGA_REGS_VIRT_BASE
);
469 pr_info("TS-78xx FPGA: magic=0x%.6x, rev=0x%.2x\n",
470 (ts78xx_fpga
.id
>> 8) & 0xffffff,
471 ts78xx_fpga
.id
& 0xff);
473 ts78xx_fpga_supports();
475 if (ts78xx_fpga_load_devices()) {
476 ts78xx_fpga
.state
= -1;
483 static int ts78xx_fpga_unload(void)
485 unsigned int fpga_id
;
487 fpga_id
= readl(TS78XX_FPGA_REGS_VIRT_BASE
);
490 * There does not seem to be a feasible way to block access to the GPIO
491 * pins from userspace (/dev/mem). This if clause should hopefully warn
492 * those foolish enough not to follow 'policy' :)
494 * UrJTAG SVN since r1381 can be used to reprogram the FPGA
496 if (ts78xx_fpga
.id
!= fpga_id
) {
497 pr_err("TS-78xx FPGA: magic/rev mismatch\n"
498 "TS-78xx FPGA: was 0x%.6x/%.2x but now 0x%.6x/%.2x\n",
499 (ts78xx_fpga
.id
>> 8) & 0xffffff, ts78xx_fpga
.id
& 0xff,
500 (fpga_id
>> 8) & 0xffffff, fpga_id
& 0xff);
501 ts78xx_fpga
.state
= -1;
505 if (ts78xx_fpga_unload_devices()) {
506 ts78xx_fpga
.state
= -1;
513 static ssize_t
ts78xx_fpga_show(struct kobject
*kobj
,
514 struct kobj_attribute
*attr
, char *buf
)
516 if (ts78xx_fpga
.state
< 0)
517 return sprintf(buf
, "borked\n");
519 return sprintf(buf
, "%s\n", (ts78xx_fpga
.state
) ? "online" : "offline");
522 static ssize_t
ts78xx_fpga_store(struct kobject
*kobj
,
523 struct kobj_attribute
*attr
, const char *buf
, size_t n
)
527 if (ts78xx_fpga
.state
< 0) {
528 pr_err("TS-78xx FPGA: borked, you must powercycle asap\n");
532 if (strncmp(buf
, "online", sizeof("online") - 1) == 0)
534 else if (strncmp(buf
, "offline", sizeof("offline") - 1) == 0)
537 pr_err("ts78xx_fpga_store: Invalid value\n");
541 if (ts78xx_fpga
.state
== value
)
544 ret
= (ts78xx_fpga
.state
== 0)
546 : ts78xx_fpga_unload();
549 ts78xx_fpga
.state
= value
;
554 static struct kobj_attribute ts78xx_fpga_attr
=
555 __ATTR(ts78xx_fpga
, 0644, ts78xx_fpga_show
, ts78xx_fpga_store
);
557 /*****************************************************************************
559 ****************************************************************************/
560 static unsigned int ts78xx_mpp_modes
[] __initdata
= {
562 MPP1_GPIO
, /* JTAG Clock */
563 MPP2_GPIO
, /* JTAG Data In */
564 MPP3_GPIO
, /* Lat ECP2 256 FPGA - PB2B */
565 MPP4_GPIO
, /* JTAG Data Out */
566 MPP5_GPIO
, /* JTAG TMS */
567 MPP6_GPIO
, /* Lat ECP2 256 FPGA - PB31A_CLK4+ */
568 MPP7_GPIO
, /* Lat ECP2 256 FPGA - PB22B */
582 * MPP[20] PCI Clock Out 1
583 * MPP[21] PCI Clock Out 0
592 static void __init
ts78xx_init(void)
597 * Setup basic Orion functions. Need to be called early.
601 orion5x_mpp_conf(ts78xx_mpp_modes
);
604 * Configure peripherals.
606 orion5x_ehci0_init();
607 orion5x_ehci1_init();
608 orion5x_eth_init(&ts78xx_eth_data
);
609 orion5x_sata_init(&ts78xx_sata_data
);
610 orion5x_uart0_init();
611 orion5x_uart1_init();
615 ts78xx_fpga_devices_zero_init();
616 ret
= ts78xx_fpga_load();
617 ret
= sysfs_create_file(power_kobj
, &ts78xx_fpga_attr
.attr
);
619 pr_err("sysfs_create_file failed: %d\n", ret
);
622 MACHINE_START(TS78XX
, "Technologic Systems TS-78xx SBC")
623 /* Maintainer: Alexander Clouter <alex@digriz.org.uk> */
624 .atag_offset
= 0x100,
625 .init_machine
= ts78xx_init
,
626 .map_io
= ts78xx_map_io
,
627 .init_early
= orion5x_init_early
,
628 .init_irq
= orion5x_init_irq
,
629 .timer
= &orion5x_timer
,