arch/mips/alchemy/devboards/db1200/setup.c

   1 /*
   2  * Alchemy/AMD/RMI DB1200 board setup.
   3  *
   4  * Licensed under the terms outlined in the file COPYING in the root of
   5  * this source archive.
   6  */
   7
   8 #include <linux/init.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/io.h>
  11 #include <linux/kernel.h>
  12 #include <asm/mach-au1x00/au1000.h>
  13 #include <asm/mach-db1x00/bcsr.h>
  14 #include <asm/mach-db1x00/db1200.h>
  15
  16 const char *get_system_type(void)
  17 {
  18         return "Alchemy Db1200";
  19 }
  20
  21 void __init board_setup(void)
  22 {
  23         unsigned long freq0, clksrc, div, pfc;
  24         unsigned short whoami;
  25
  26         /* Set Config[OD] (disable overlapping bus transaction):
  27          * This gets rid of a _lot_ of spurious interrupts (especially
  28          * wrt. IDE); but incurs ~10% performance hit in some
  29          * cpu-bound applications.
  30          */
  31         set_c0_config(1 << 19);
  32
  33         bcsr_init(DB1200_BCSR_PHYS_ADDR,
  34                   DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
  35
  36         whoami = bcsr_read(BCSR_WHOAMI);
  37         printk(KERN_INFO "Alchemy/AMD/RMI DB1200 Board, CPLD Rev %d"
  38                 "  Board-ID %d  Daughtercard ID %d\n",
  39                 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
  40
  41         /* SMBus/SPI on PSC0, Audio on PSC1 */
  42         pfc = __raw_readl((void __iomem *)SYS_PINFUNC);
  43         pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
  44         pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3);
  45         pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */
  46         __raw_writel(pfc, (void __iomem *)SYS_PINFUNC);
  47         wmb();
  48
  49         /* Clock configurations: PSC0: ~50MHz via Clkgen0, derived from
  50          * CPU clock; all other clock generators off/unused.
  51          */
  52         div = (get_au1x00_speed() + 25000000) / 50000000;
  53         if (div & 1)
  54                 div++;
  55         div = ((div >> 1) - 1) & 0xff;
  56
  57         freq0 = div << SYS_FC_FRDIV0_BIT;
  58         __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);
  59         wmb();
  60         freq0 |= SYS_FC_FE0;    /* enable F0 */
  61         __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);
  62         wmb();
  63
  64         /* psc0_intclk comes 1:1 from F0 */
  65         clksrc = SYS_CS_MUX_FQ0 << SYS_CS_ME0_BIT;
  66         __raw_writel(clksrc, (void __iomem *)SYS_CLKSRC);
  67         wmb();
  68 }
  69
  70 static int __init db1200_arch_init(void)
  71 {
  72         /* GPIO7 is low-level triggered CPLD cascade */
  73         irq_set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
  74         bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT);
  75
  76         /* insert/eject pairs: one of both is always screaming.  To avoid
  77          * issues they must not be automatically enabled when initially
  78          * requested.
  79          */
  80         irq_set_status_flags(DB1200_SD0_INSERT_INT, IRQ_NOAUTOEN);
  81         irq_set_status_flags(DB1200_SD0_EJECT_INT, IRQ_NOAUTOEN);
  82         irq_set_status_flags(DB1200_PC0_INSERT_INT, IRQ_NOAUTOEN);
  83         irq_set_status_flags(DB1200_PC0_EJECT_INT, IRQ_NOAUTOEN);
  84         irq_set_status_flags(DB1200_PC1_INSERT_INT, IRQ_NOAUTOEN);
  85         irq_set_status_flags(DB1200_PC1_EJECT_INT, IRQ_NOAUTOEN);
  86         return 0;
  87 }
  88 arch_initcall(db1200_arch_init);