Add linux-next specific files for 20110831
[linux-2.6/next.git] / arch / mips / include / asm / mips-boards / piix4.h
blob2971d60f2e95c188fbd9987bfe0fa6752d6b33c3
1 /*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18 * Register definitions for Intel PIIX4 South Bridge Device.
20 #ifndef __ASM_MIPS_BOARDS_PIIX4_H
21 #define __ASM_MIPS_BOARDS_PIIX4_H
23 /************************************************************************
24 * IO register offsets
25 ************************************************************************/
26 #define PIIX4_ICTLR1_ICW1 0x20
27 #define PIIX4_ICTLR1_ICW2 0x21
28 #define PIIX4_ICTLR1_ICW3 0x21
29 #define PIIX4_ICTLR1_ICW4 0x21
30 #define PIIX4_ICTLR2_ICW1 0xa0
31 #define PIIX4_ICTLR2_ICW2 0xa1
32 #define PIIX4_ICTLR2_ICW3 0xa1
33 #define PIIX4_ICTLR2_ICW4 0xa1
34 #define PIIX4_ICTLR1_OCW1 0x21
35 #define PIIX4_ICTLR1_OCW2 0x20
36 #define PIIX4_ICTLR1_OCW3 0x20
37 #define PIIX4_ICTLR1_OCW4 0x20
38 #define PIIX4_ICTLR2_OCW1 0xa1
39 #define PIIX4_ICTLR2_OCW2 0xa0
40 #define PIIX4_ICTLR2_OCW3 0xa0
41 #define PIIX4_ICTLR2_OCW4 0xa0
44 /************************************************************************
45 * Register encodings.
46 ************************************************************************/
47 #define PIIX4_OCW2_NSEOI (0x1 << 5)
48 #define PIIX4_OCW2_SEOI (0x3 << 5)
49 #define PIIX4_OCW2_RNSEOI (0x5 << 5)
50 #define PIIX4_OCW2_RAEOIS (0x4 << 5)
51 #define PIIX4_OCW2_RAEOIC (0x0 << 5)
52 #define PIIX4_OCW2_RSEOI (0x7 << 5)
53 #define PIIX4_OCW2_SP (0x6 << 5)
54 #define PIIX4_OCW2_NOP (0x2 << 5)
56 #define PIIX4_OCW2_SEL (0x0 << 3)
58 #define PIIX4_OCW2_ILS_0 0
59 #define PIIX4_OCW2_ILS_1 1
60 #define PIIX4_OCW2_ILS_2 2
61 #define PIIX4_OCW2_ILS_3 3
62 #define PIIX4_OCW2_ILS_4 4
63 #define PIIX4_OCW2_ILS_5 5
64 #define PIIX4_OCW2_ILS_6 6
65 #define PIIX4_OCW2_ILS_7 7
66 #define PIIX4_OCW2_ILS_8 0
67 #define PIIX4_OCW2_ILS_9 1
68 #define PIIX4_OCW2_ILS_10 2
69 #define PIIX4_OCW2_ILS_11 3
70 #define PIIX4_OCW2_ILS_12 4
71 #define PIIX4_OCW2_ILS_13 5
72 #define PIIX4_OCW2_ILS_14 6
73 #define PIIX4_OCW2_ILS_15 7
75 #define PIIX4_OCW3_SEL (0x1 << 3)
77 #define PIIX4_OCW3_IRR 0x2
78 #define PIIX4_OCW3_ISR 0x3
80 #endif /* __ASM_MIPS_BOARDS_PIIX4_H */