arch/mips/include/asm/txx9/tx4939.h

   1 /*
   2  * Definitions for TX4939
   3  *
   4  * Copyright (C) 2000-2001,2005-2006 Toshiba Corporation
   5  * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
   6  * terms of the GNU General Public License version 2. This program is
   7  * licensed "as is" without any warranty of any kind, whether express
   8  * or implied.
   9  */
  10 #ifndef __ASM_TXX9_TX4939_H
  11 #define __ASM_TXX9_TX4939_H
  12
  13 /* some controllers are compatible with 4927/4938 */
  14 #include <asm/txx9/tx4938.h>
  15
  16 #ifdef CONFIG_64BIT
  17 #define TX4939_REG_BASE 0xffffffffff1f0000UL /* == TX4938_REG_BASE */
  18 #else
  19 #define TX4939_REG_BASE 0xff1f0000UL /* == TX4938_REG_BASE */
  20 #endif
  21 #define TX4939_REG_SIZE 0x00010000 /* == TX4938_REG_SIZE */
  22
  23 #define TX4939_ATA_REG(ch)      (TX4939_REG_BASE + 0x3000 + (ch) * 0x1000)
  24 #define TX4939_NDFMC_REG        (TX4939_REG_BASE + 0x5000)
  25 #define TX4939_SRAMC_REG        (TX4939_REG_BASE + 0x6000)
  26 #define TX4939_CRYPTO_REG       (TX4939_REG_BASE + 0x6800)
  27 #define TX4939_PCIC1_REG        (TX4939_REG_BASE + 0x7000)
  28 #define TX4939_DDRC_REG         (TX4939_REG_BASE + 0x8000)
  29 #define TX4939_EBUSC_REG        (TX4939_REG_BASE + 0x9000)
  30 #define TX4939_VPC_REG          (TX4939_REG_BASE + 0xa000)
  31 #define TX4939_DMA_REG(ch)      (TX4939_REG_BASE + 0xb000 + (ch) * 0x800)
  32 #define TX4939_PCIC_REG         (TX4939_REG_BASE + 0xd000)
  33 #define TX4939_CCFG_REG         (TX4939_REG_BASE + 0xe000)
  34 #define TX4939_IRC_REG          (TX4939_REG_BASE + 0xe800)
  35 #define TX4939_NR_TMR   6       /* 0xf000,0xf100,0xf200,0xfd00,0xfe00,0xff00 */
  36 #define TX4939_TMR_REG(ch)      \
  37         (TX4939_REG_BASE + 0xf000 + ((ch) + ((ch) >= 3) * 10) * 0x100)
  38 #define TX4939_NR_SIO   4       /* 0xf300, 0xf400, 0xf380, 0xf480 */
  39 #define TX4939_SIO_REG(ch)      \
  40         (TX4939_REG_BASE + 0xf300 + (((ch) & 1) << 8) + (((ch) & 2) << 6))
  41 #define TX4939_ACLC_REG         (TX4939_REG_BASE + 0xf700)
  42 #define TX4939_SPI_REG          (TX4939_REG_BASE + 0xf800)
  43 #define TX4939_I2C_REG          (TX4939_REG_BASE + 0xf900)
  44 #define TX4939_I2S_REG          (TX4939_REG_BASE + 0xfa00)
  45 #define TX4939_RTC_REG          (TX4939_REG_BASE + 0xfb00)
  46 #define TX4939_CIR_REG          (TX4939_REG_BASE + 0xfc00)
  47
  48 #define TX4939_RNG_REG          (TX4939_CRYPTO_REG + 0xb0)
  49
  50 struct tx4939_le_reg {
  51         __u32 r;
  52         __u32 unused;
  53 };
  54
  55 struct tx4939_ddrc_reg {
  56         struct tx4939_le_reg ctl[47];
  57         __u64 unused0[17];
  58         __u64 winen;
  59         __u64 win[4];
  60 };
  61
  62 struct tx4939_ccfg_reg {
  63         __u64 ccfg;
  64         __u64 crir;
  65         __u64 pcfg;
  66         __u64 toea;
  67         __u64 clkctr;
  68         __u64 unused0;
  69         __u64 garbc;
  70         __u64 unused1[2];
  71         __u64 ramp;
  72         __u64 unused2[2];
  73         __u64 dskwctrl;
  74         __u64 mclkosc;
  75         __u64 mclkctl;
  76         __u64 unused3[17];
  77         struct {
  78                 __u64 mr;
  79                 __u64 dr;
  80         } gpio[2];
  81 };
  82
  83 struct tx4939_irc_reg {
  84         struct tx4939_le_reg den;
  85         struct tx4939_le_reg scipb;
  86         struct tx4939_le_reg dm[2];
  87         struct tx4939_le_reg lvl[16];
  88         struct tx4939_le_reg msk;
  89         struct tx4939_le_reg edc;
  90         struct tx4939_le_reg pnd0;
  91         struct tx4939_le_reg cs;
  92         struct tx4939_le_reg pnd1;
  93         struct tx4939_le_reg dm2[2];
  94         struct tx4939_le_reg dbr[2];
  95         struct tx4939_le_reg dben;
  96         struct tx4939_le_reg unused0[2];
  97         struct tx4939_le_reg flag[2];
  98         struct tx4939_le_reg pol;
  99         struct tx4939_le_reg cnt;
 100         struct tx4939_le_reg maskint;
 101         struct tx4939_le_reg maskext;
 102 };
 103
 104 struct tx4939_rtc_reg {
 105         __u32 ctl;
 106         __u32 adr;
 107         __u32 dat;
 108         __u32 tbc;
 109 };
 110
 111 struct tx4939_crypto_reg {
 112         struct tx4939_le_reg csr;
 113         struct tx4939_le_reg idesptr;
 114         struct tx4939_le_reg cdesptr;
 115         struct tx4939_le_reg buserr;
 116         struct tx4939_le_reg cip_tout;
 117         struct tx4939_le_reg cir;
 118         union {
 119                 struct {
 120                         struct tx4939_le_reg data[8];
 121                         struct tx4939_le_reg ctrl;
 122                 } gen;
 123                 struct {
 124                         struct {
 125                                 struct tx4939_le_reg l;
 126                                 struct tx4939_le_reg u;
 127                         } key[3], ini;
 128                         struct tx4939_le_reg ctrl;
 129                 } des;
 130                 struct {
 131                         struct tx4939_le_reg key[4];
 132                         struct tx4939_le_reg ini[4];
 133                         struct tx4939_le_reg ctrl;
 134                 } aes;
 135                 struct {
 136                         struct {
 137                                 struct tx4939_le_reg l;
 138                                 struct tx4939_le_reg u;
 139                         } cnt;
 140                         struct tx4939_le_reg ini[5];
 141                         struct tx4939_le_reg unused;
 142                         struct tx4939_le_reg ctrl;
 143                 } hash;
 144         } cdr;
 145         struct tx4939_le_reg unused0[7];
 146         struct tx4939_le_reg rcsr;
 147         struct tx4939_le_reg rpr;
 148         __u64 rdr;
 149         __u64 ror[3];
 150         struct tx4939_le_reg unused1[2];
 151         struct tx4939_le_reg xorslr;
 152         struct tx4939_le_reg xorsur;
 153 };
 154
 155 struct tx4939_crypto_desc {
 156         __u32 src;
 157         __u32 dst;
 158         __u32 next;
 159         __u32 ctrl;
 160         __u32 index;
 161         __u32 xor;
 162 };
 163
 164 struct tx4939_vpc_reg {
 165         struct tx4939_le_reg csr;
 166         struct {
 167                 struct tx4939_le_reg ctrlA;
 168                 struct tx4939_le_reg ctrlB;
 169                 struct tx4939_le_reg idesptr;
 170                 struct tx4939_le_reg cdesptr;
 171         } port[3];
 172         struct tx4939_le_reg buserr;
 173 };
 174
 175 struct tx4939_vpc_desc {
 176         __u32 src;
 177         __u32 next;
 178         __u32 ctrl1;
 179         __u32 ctrl2;
 180 };
 181
 182 /*
 183  * IRC
 184  */
 185 #define TX4939_IR_NONE  0
 186 #define TX4939_IR_DDR   1
 187 #define TX4939_IR_WTOERR        2
 188 #define TX4939_NUM_IR_INT       3
 189 #define TX4939_IR_INT(n)        (3 + (n))
 190 #define TX4939_NUM_IR_ETH       2
 191 #define TX4939_IR_ETH(n)        ((n) ? 43 : 6)
 192 #define TX4939_IR_VIDEO 7
 193 #define TX4939_IR_CIR   8
 194 #define TX4939_NUM_IR_SIO       4
 195 #define TX4939_IR_SIO(n)        ((n) ? 43 + (n) : 9)    /* 9,44-46 */
 196 #define TX4939_NUM_IR_DMA       4
 197 #define TX4939_IR_DMA(ch, n)    (((ch) ? 22 : 10) + (n)) /* 10-13,22-25 */
 198 #define TX4939_IR_IRC   14
 199 #define TX4939_IR_PDMAC 15
 200 #define TX4939_NUM_IR_TMR       6
 201 #define TX4939_IR_TMR(n)        (((n) >= 3 ? 45 : 16) + (n)) /* 16-18,48-50 */
 202 #define TX4939_NUM_IR_ATA       2
 203 #define TX4939_IR_ATA(n)        (19 + (n))
 204 #define TX4939_IR_ACLC  21
 205 #define TX4939_IR_CIPHER        26
 206 #define TX4939_IR_INTA  27
 207 #define TX4939_IR_INTB  28
 208 #define TX4939_IR_INTC  29
 209 #define TX4939_IR_INTD  30
 210 #define TX4939_IR_I2C   33
 211 #define TX4939_IR_SPI   34
 212 #define TX4939_IR_PCIC  35
 213 #define TX4939_IR_PCIC1 36
 214 #define TX4939_IR_PCIERR        37
 215 #define TX4939_IR_PCIPME        38
 216 #define TX4939_IR_NDFMC 39
 217 #define TX4939_IR_ACLCPME       40
 218 #define TX4939_IR_RTC   41
 219 #define TX4939_IR_RND   42
 220 #define TX4939_IR_I2S   47
 221 #define TX4939_NUM_IR   64
 222
 223 #define TX4939_IRC_INT  2       /* IP[2] in Status register */
 224
 225 /*
 226  * CCFG
 227  */
 228 /* CCFG : Chip Configuration */
 229 #define TX4939_CCFG_PCIBOOT     0x0000040000000000ULL
 230 #define TX4939_CCFG_WDRST       0x0000020000000000ULL
 231 #define TX4939_CCFG_WDREXEN     0x0000010000000000ULL
 232 #define TX4939_CCFG_BCFG_MASK   0x000000ff00000000ULL
 233 #define TX4939_CCFG_GTOT_MASK   0x06000000
 234 #define TX4939_CCFG_GTOT_4096   0x06000000
 235 #define TX4939_CCFG_GTOT_2048   0x04000000
 236 #define TX4939_CCFG_GTOT_1024   0x02000000
 237 #define TX4939_CCFG_GTOT_512    0x00000000
 238 #define TX4939_CCFG_TINTDIS     0x01000000
 239 #define TX4939_CCFG_PCI66       0x00800000
 240 #define TX4939_CCFG_PCIMODE     0x00400000
 241 #define TX4939_CCFG_SSCG        0x00100000
 242 #define TX4939_CCFG_MULCLK_MASK 0x000e0000
 243 #define TX4939_CCFG_MULCLK_8    (0x7 << 17)
 244 #define TX4939_CCFG_MULCLK_9    (0x0 << 17)
 245 #define TX4939_CCFG_MULCLK_10   (0x1 << 17)
 246 #define TX4939_CCFG_MULCLK_11   (0x2 << 17)
 247 #define TX4939_CCFG_MULCLK_12   (0x3 << 17)
 248 #define TX4939_CCFG_MULCLK_13   (0x4 << 17)
 249 #define TX4939_CCFG_MULCLK_14   (0x5 << 17)
 250 #define TX4939_CCFG_MULCLK_15   (0x6 << 17)
 251 #define TX4939_CCFG_BEOW        0x00010000
 252 #define TX4939_CCFG_WR  0x00008000
 253 #define TX4939_CCFG_TOE 0x00004000
 254 #define TX4939_CCFG_PCIARB      0x00002000
 255 #define TX4939_CCFG_YDIVMODE_MASK       0x00001c00
 256 #define TX4939_CCFG_YDIVMODE_2  (0x0 << 10)
 257 #define TX4939_CCFG_YDIVMODE_3  (0x1 << 10)
 258 #define TX4939_CCFG_YDIVMODE_5  (0x6 << 10)
 259 #define TX4939_CCFG_YDIVMODE_6  (0x7 << 10)
 260 #define TX4939_CCFG_PTSEL       0x00000200
 261 #define TX4939_CCFG_BESEL       0x00000100
 262 #define TX4939_CCFG_SYSSP_MASK  0x000000c0
 263 #define TX4939_CCFG_ACKSEL      0x00000020
 264 #define TX4939_CCFG_ROMW        0x00000010
 265 #define TX4939_CCFG_ENDIAN      0x00000004
 266 #define TX4939_CCFG_ARMODE      0x00000002
 267 #define TX4939_CCFG_ACEHOLD     0x00000001
 268
 269 /* PCFG : Pin Configuration */
 270 #define TX4939_PCFG_SIO2MODE_MASK       0xc000000000000000ULL
 271 #define TX4939_PCFG_SIO2MODE_GPIO       0x8000000000000000ULL
 272 #define TX4939_PCFG_SIO2MODE_SIO2       0x4000000000000000ULL
 273 #define TX4939_PCFG_SIO2MODE_SIO0       0x0000000000000000ULL
 274 #define TX4939_PCFG_SPIMODE     0x2000000000000000ULL
 275 #define TX4939_PCFG_I2CMODE     0x1000000000000000ULL
 276 #define TX4939_PCFG_I2SMODE_MASK        0x0c00000000000000ULL
 277 #define TX4939_PCFG_I2SMODE_GPIO        0x0c00000000000000ULL
 278 #define TX4939_PCFG_I2SMODE_I2S 0x0800000000000000ULL
 279 #define TX4939_PCFG_I2SMODE_I2S_ALT     0x0400000000000000ULL
 280 #define TX4939_PCFG_I2SMODE_ACLC        0x0000000000000000ULL
 281 #define TX4939_PCFG_SIO3MODE    0x0200000000000000ULL
 282 #define TX4939_PCFG_DMASEL3     0x0004000000000000ULL
 283 #define TX4939_PCFG_DMASEL3_SIO0        0x0004000000000000ULL
 284 #define TX4939_PCFG_DMASEL3_NDFC        0x0000000000000000ULL
 285 #define TX4939_PCFG_VSSMODE     0x0000200000000000ULL
 286 #define TX4939_PCFG_VPSMODE     0x0000100000000000ULL
 287 #define TX4939_PCFG_ET1MODE     0x0000080000000000ULL
 288 #define TX4939_PCFG_ET0MODE     0x0000040000000000ULL
 289 #define TX4939_PCFG_ATA1MODE    0x0000020000000000ULL
 290 #define TX4939_PCFG_ATA0MODE    0x0000010000000000ULL
 291 #define TX4939_PCFG_BP_PLL      0x0000000100000000ULL
 292
 293 #define TX4939_PCFG_SYSCLKEN    0x08000000
 294 #define TX4939_PCFG_PCICLKEN_ALL        0x000f0000
 295 #define TX4939_PCFG_PCICLKEN(ch)        (0x00010000<<(ch))
 296 #define TX4939_PCFG_SPEED1      0x00002000
 297 #define TX4939_PCFG_SPEED0      0x00001000
 298 #define TX4939_PCFG_ITMODE      0x00000300
 299 #define TX4939_PCFG_DMASEL_ALL  (0x00000007 | TX4939_PCFG_DMASEL3)
 300 #define TX4939_PCFG_DMASEL2     0x00000004
 301 #define TX4939_PCFG_DMASEL2_DRQ2        0x00000000
 302 #define TX4939_PCFG_DMASEL2_SIO0        0x00000004
 303 #define TX4939_PCFG_DMASEL1     0x00000002
 304 #define TX4939_PCFG_DMASEL1_DRQ1        0x00000000
 305 #define TX4939_PCFG_DMASEL0     0x00000001
 306 #define TX4939_PCFG_DMASEL0_DRQ0        0x00000000
 307
 308 /* CLKCTR : Clock Control */
 309 #define TX4939_CLKCTR_IOSCKD    0x8000000000000000ULL
 310 #define TX4939_CLKCTR_SYSCKD    0x4000000000000000ULL
 311 #define TX4939_CLKCTR_TM5CKD    0x2000000000000000ULL
 312 #define TX4939_CLKCTR_TM4CKD    0x1000000000000000ULL
 313 #define TX4939_CLKCTR_TM3CKD    0x0800000000000000ULL
 314 #define TX4939_CLKCTR_CIRCKD    0x0400000000000000ULL
 315 #define TX4939_CLKCTR_SIO3CKD   0x0200000000000000ULL
 316 #define TX4939_CLKCTR_SIO2CKD   0x0100000000000000ULL
 317 #define TX4939_CLKCTR_SIO1CKD   0x0080000000000000ULL
 318 #define TX4939_CLKCTR_VPCCKD    0x0040000000000000ULL
 319 #define TX4939_CLKCTR_EPCICKD   0x0020000000000000ULL
 320 #define TX4939_CLKCTR_ETH1CKD   0x0008000000000000ULL
 321 #define TX4939_CLKCTR_ATA1CKD   0x0004000000000000ULL
 322 #define TX4939_CLKCTR_BROMCKD   0x0002000000000000ULL
 323 #define TX4939_CLKCTR_NDCCKD    0x0001000000000000ULL
 324 #define TX4939_CLKCTR_I2CCKD    0x0000800000000000ULL
 325 #define TX4939_CLKCTR_ETH0CKD   0x0000400000000000ULL
 326 #define TX4939_CLKCTR_SPICKD    0x0000200000000000ULL
 327 #define TX4939_CLKCTR_SRAMCKD   0x0000100000000000ULL
 328 #define TX4939_CLKCTR_PCI1CKD   0x0000080000000000ULL
 329 #define TX4939_CLKCTR_DMA1CKD   0x0000040000000000ULL
 330 #define TX4939_CLKCTR_ACLCKD    0x0000020000000000ULL
 331 #define TX4939_CLKCTR_ATA0CKD   0x0000010000000000ULL
 332 #define TX4939_CLKCTR_DMA0CKD   0x0000008000000000ULL
 333 #define TX4939_CLKCTR_PCICCKD   0x0000004000000000ULL
 334 #define TX4939_CLKCTR_I2SCKD    0x0000002000000000ULL
 335 #define TX4939_CLKCTR_TM0CKD    0x0000001000000000ULL
 336 #define TX4939_CLKCTR_TM1CKD    0x0000000800000000ULL
 337 #define TX4939_CLKCTR_TM2CKD    0x0000000400000000ULL
 338 #define TX4939_CLKCTR_SIO0CKD   0x0000000200000000ULL
 339 #define TX4939_CLKCTR_CYPCKD    0x0000000100000000ULL
 340 #define TX4939_CLKCTR_IOSRST    0x80000000
 341 #define TX4939_CLKCTR_SYSRST    0x40000000
 342 #define TX4939_CLKCTR_TM5RST    0x20000000
 343 #define TX4939_CLKCTR_TM4RST    0x10000000
 344 #define TX4939_CLKCTR_TM3RST    0x08000000
 345 #define TX4939_CLKCTR_CIRRST    0x04000000
 346 #define TX4939_CLKCTR_SIO3RST   0x02000000
 347 #define TX4939_CLKCTR_SIO2RST   0x01000000
 348 #define TX4939_CLKCTR_SIO1RST   0x00800000
 349 #define TX4939_CLKCTR_VPCRST    0x00400000
 350 #define TX4939_CLKCTR_EPCIRST   0x00200000
 351 #define TX4939_CLKCTR_ETH1RST   0x00080000
 352 #define TX4939_CLKCTR_ATA1RST   0x00040000
 353 #define TX4939_CLKCTR_BROMRST   0x00020000
 354 #define TX4939_CLKCTR_NDCRST    0x00010000
 355 #define TX4939_CLKCTR_I2CRST    0x00008000
 356 #define TX4939_CLKCTR_ETH0RST   0x00004000
 357 #define TX4939_CLKCTR_SPIRST    0x00002000
 358 #define TX4939_CLKCTR_SRAMRST   0x00001000
 359 #define TX4939_CLKCTR_PCI1RST   0x00000800
 360 #define TX4939_CLKCTR_DMA1RST   0x00000400
 361 #define TX4939_CLKCTR_ACLRST    0x00000200
 362 #define TX4939_CLKCTR_ATA0RST   0x00000100
 363 #define TX4939_CLKCTR_DMA0RST   0x00000080
 364 #define TX4939_CLKCTR_PCICRST   0x00000040
 365 #define TX4939_CLKCTR_I2SRST    0x00000020
 366 #define TX4939_CLKCTR_TM0RST    0x00000010
 367 #define TX4939_CLKCTR_TM1RST    0x00000008
 368 #define TX4939_CLKCTR_TM2RST    0x00000004
 369 #define TX4939_CLKCTR_SIO0RST   0x00000002
 370 #define TX4939_CLKCTR_CYPRST    0x00000001
 371
 372 /*
 373  * RTC
 374  */
 375 #define TX4939_RTCCTL_ALME      0x00000080
 376 #define TX4939_RTCCTL_ALMD      0x00000040
 377 #define TX4939_RTCCTL_BUSY      0x00000020
 378
 379 #define TX4939_RTCCTL_COMMAND   0x00000007
 380 #define TX4939_RTCCTL_COMMAND_NOP       0x00000000
 381 #define TX4939_RTCCTL_COMMAND_GETTIME   0x00000001
 382 #define TX4939_RTCCTL_COMMAND_SETTIME   0x00000002
 383 #define TX4939_RTCCTL_COMMAND_GETALARM  0x00000003
 384 #define TX4939_RTCCTL_COMMAND_SETALARM  0x00000004
 385
 386 #define TX4939_RTCTBC_PM        0x00000080
 387 #define TX4939_RTCTBC_COMP      0x0000007f
 388
 389 #define TX4939_RTC_REG_RAMSIZE  0x00000100
 390 #define TX4939_RTC_REG_RWBSIZE  0x00000006
 391
 392 /*
 393  * CRYPTO
 394  */
 395 #define TX4939_CRYPTO_CSR_SAESO 0x08000000
 396 #define TX4939_CRYPTO_CSR_SAESI 0x04000000
 397 #define TX4939_CRYPTO_CSR_SDESO 0x02000000
 398 #define TX4939_CRYPTO_CSR_SDESI 0x01000000
 399 #define TX4939_CRYPTO_CSR_INDXBST_MASK  0x00700000
 400 #define TX4939_CRYPTO_CSR_INDXBST(n)    ((n) << 20)
 401 #define TX4939_CRYPTO_CSR_TOINT 0x00080000
 402 #define TX4939_CRYPTO_CSR_DCINT 0x00040000
 403 #define TX4939_CRYPTO_CSR_GBINT 0x00010000
 404 #define TX4939_CRYPTO_CSR_INDXAST_MASK  0x0000e000
 405 #define TX4939_CRYPTO_CSR_INDXAST(n)    ((n) << 13)
 406 #define TX4939_CRYPTO_CSR_CSWAP_MASK    0x00001800
 407 #define TX4939_CRYPTO_CSR_CSWAP_NONE    0x00000000
 408 #define TX4939_CRYPTO_CSR_CSWAP_IN      0x00000800
 409 #define TX4939_CRYPTO_CSR_CSWAP_OUT     0x00001000
 410 #define TX4939_CRYPTO_CSR_CSWAP_BOTH    0x00001800
 411 #define TX4939_CRYPTO_CSR_CDIV_MASK     0x00000600
 412 #define TX4939_CRYPTO_CSR_CDIV_DIV2     0x00000000
 413 #define TX4939_CRYPTO_CSR_CDIV_DIV1     0x00000200
 414 #define TX4939_CRYPTO_CSR_CDIV_DIV2ALT  0x00000400
 415 #define TX4939_CRYPTO_CSR_CDIV_DIV1ALT  0x00000600
 416 #define TX4939_CRYPTO_CSR_PDINT_MASK    0x000000c0
 417 #define TX4939_CRYPTO_CSR_PDINT_ALL     0x00000000
 418 #define TX4939_CRYPTO_CSR_PDINT_END     0x00000040
 419 #define TX4939_CRYPTO_CSR_PDINT_NEXT    0x00000080
 420 #define TX4939_CRYPTO_CSR_PDINT_NONE    0x000000c0
 421 #define TX4939_CRYPTO_CSR_GINTE 0x00000008
 422 #define TX4939_CRYPTO_CSR_RSTD  0x00000004
 423 #define TX4939_CRYPTO_CSR_RSTC  0x00000002
 424 #define TX4939_CRYPTO_CSR_ENCR  0x00000001
 425
 426 /* bits for tx4939_crypto_reg.cdr.gen.ctrl */
 427 #define TX4939_CRYPTO_CTX_ENGINE_MASK   0x00000003
 428 #define TX4939_CRYPTO_CTX_ENGINE_DES    0x00000000
 429 #define TX4939_CRYPTO_CTX_ENGINE_AES    0x00000001
 430 #define TX4939_CRYPTO_CTX_ENGINE_MD5    0x00000002
 431 #define TX4939_CRYPTO_CTX_ENGINE_SHA1   0x00000003
 432 #define TX4939_CRYPTO_CTX_TDMS  0x00000010
 433 #define TX4939_CRYPTO_CTX_CMS   0x00000020
 434 #define TX4939_CRYPTO_CTX_DMS   0x00000040
 435 #define TX4939_CRYPTO_CTX_UPDATE        0x00000080
 436
 437 /* bits for tx4939_crypto_desc.ctrl */
 438 #define TX4939_CRYPTO_DESC_OB_CNT_MASK  0xffe00000
 439 #define TX4939_CRYPTO_DESC_OB_CNT(cnt)  ((cnt) << 21)
 440 #define TX4939_CRYPTO_DESC_IB_CNT_MASK  0x001ffc00
 441 #define TX4939_CRYPTO_DESC_IB_CNT(cnt)  ((cnt) << 10)
 442 #define TX4939_CRYPTO_DESC_START        0x00000200
 443 #define TX4939_CRYPTO_DESC_END  0x00000100
 444 #define TX4939_CRYPTO_DESC_XOR  0x00000010
 445 #define TX4939_CRYPTO_DESC_LAST 0x00000008
 446 #define TX4939_CRYPTO_DESC_ERR_MASK     0x00000006
 447 #define TX4939_CRYPTO_DESC_ERR_NONE     0x00000000
 448 #define TX4939_CRYPTO_DESC_ERR_TOUT     0x00000002
 449 #define TX4939_CRYPTO_DESC_ERR_DIGEST   0x00000004
 450 #define TX4939_CRYPTO_DESC_OWN  0x00000001
 451
 452 /* bits for tx4939_crypto_desc.index */
 453 #define TX4939_CRYPTO_DESC_HASH_IDX_MASK        0x00000070
 454 #define TX4939_CRYPTO_DESC_HASH_IDX(idx)        ((idx) << 4)
 455 #define TX4939_CRYPTO_DESC_ENCRYPT_IDX_MASK     0x00000007
 456 #define TX4939_CRYPTO_DESC_ENCRYPT_IDX(idx)     ((idx) << 0)
 457
 458 #define TX4939_CRYPTO_NR_SET    6
 459
 460 #define TX4939_CRYPTO_RCSR_INTE 0x00000008
 461 #define TX4939_CRYPTO_RCSR_RST  0x00000004
 462 #define TX4939_CRYPTO_RCSR_FIN  0x00000002
 463 #define TX4939_CRYPTO_RCSR_ST   0x00000001
 464
 465 /*
 466  * VPC
 467  */
 468 #define TX4939_VPC_CSR_GBINT    0x00010000
 469 #define TX4939_VPC_CSR_SWAPO    0x00000020
 470 #define TX4939_VPC_CSR_SWAPI    0x00000010
 471 #define TX4939_VPC_CSR_GINTE    0x00000008
 472 #define TX4939_VPC_CSR_RSTD     0x00000004
 473 #define TX4939_VPC_CSR_RSTVPC   0x00000002
 474
 475 #define TX4939_VPC_CTRLA_VDPSN  0x00000200
 476 #define TX4939_VPC_CTRLA_PBUSY  0x00000100
 477 #define TX4939_VPC_CTRLA_DCINT  0x00000080
 478 #define TX4939_VPC_CTRLA_UOINT  0x00000040
 479 #define TX4939_VPC_CTRLA_PDINT_MASK     0x00000030
 480 #define TX4939_VPC_CTRLA_PDINT_ALL      0x00000000
 481 #define TX4939_VPC_CTRLA_PDINT_NEXT     0x00000010
 482 #define TX4939_VPC_CTRLA_PDINT_NONE     0x00000030
 483 #define TX4939_VPC_CTRLA_VDVLDP 0x00000008
 484 #define TX4939_VPC_CTRLA_VDMODE 0x00000004
 485 #define TX4939_VPC_CTRLA_VDFOR  0x00000002
 486 #define TX4939_VPC_CTRLA_ENVPC  0x00000001
 487
 488 /* bits for tx4939_vpc_desc.ctrl1 */
 489 #define TX4939_VPC_DESC_CTRL1_ERR_MASK  0x00000006
 490 #define TX4939_VPC_DESC_CTRL1_OWN       0x00000001
 491
 492 #define tx4939_ddrcptr  ((struct tx4939_ddrc_reg __iomem *)TX4939_DDRC_REG)
 493 #define tx4939_ebuscptr         tx4938_ebuscptr
 494 #define tx4939_ircptr \
 495                 ((struct tx4939_irc_reg __iomem *)TX4939_IRC_REG)
 496 #define tx4939_pcicptr          tx4938_pcicptr
 497 #define tx4939_pcic1ptr         tx4938_pcic1ptr
 498 #define tx4939_ccfgptr \
 499                 ((struct tx4939_ccfg_reg __iomem *)TX4939_CCFG_REG)
 500 #define tx4939_sramcptr         tx4938_sramcptr
 501 #define tx4939_rtcptr \
 502                 ((struct tx4939_rtc_reg __iomem *)TX4939_RTC_REG)
 503 #define tx4939_cryptoptr \
 504                 ((struct tx4939_crypto_reg __iomem *)TX4939_CRYPTO_REG)
 505 #define tx4939_vpcptr   ((struct tx4939_vpc_reg __iomem *)TX4939_VPC_REG)
 506
 507 #define TX4939_REV_MAJ_MIN()    \
 508         ((__u32)__raw_readq(&tx4939_ccfgptr->crir) & 0x00ff)
 509 #define TX4939_REV_PCODE()      \
 510         ((__u32)__raw_readq(&tx4939_ccfgptr->crir) >> 16)
 511 #define TX4939_CCFG_BCFG()      \
 512         ((__u32)((__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_BCFG_MASK) \
 513                  >> 32))
 514
 515 #define tx4939_ccfg_clear(bits) tx4938_ccfg_clear(bits)
 516 #define tx4939_ccfg_set(bits)   tx4938_ccfg_set(bits)
 517 #define tx4939_ccfg_change(change, new) tx4938_ccfg_change(change, new)
 518
 519 #define TX4939_EBUSC_CR(ch)     TX4927_EBUSC_CR(ch)
 520 #define TX4939_EBUSC_BA(ch)     TX4927_EBUSC_BA(ch)
 521 #define TX4939_EBUSC_SIZE(ch)   TX4927_EBUSC_SIZE(ch)
 522 #define TX4939_EBUSC_WIDTH(ch)  \
 523         (16 >> ((__u32)(TX4939_EBUSC_CR(ch) >> 20) & 0x1))
 524
 525 /* SCLK0 = MSTCLK * 429/19 * 16/245 / 2  (14.745MHz for MST 20MHz) */
 526 #define TX4939_SCLK0(mst)       \
 527         ((((mst) + 245/2) / 245UL * 429 * 16 + 19) / 19 / 2)
 528
 529 void tx4939_wdt_init(void);
 530 void tx4939_add_memory_regions(void);
 531 void tx4939_setup(void);
 532 void tx4939_time_init(unsigned int tmrnr);
 533 void tx4939_sio_init(unsigned int sclk, unsigned int cts_mask);
 534 void tx4939_spi_init(int busid);
 535 void tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1);
 536 int tx4939_report_pciclk(void);
 537 void tx4939_report_pci1clk(void);
 538 struct pci_dev;
 539 int tx4939_pcic1_map_irq(const struct pci_dev *dev, u8 slot);
 540 int tx4939_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
 541 void tx4939_setup_pcierr_irq(void);
 542 void tx4939_irq_init(void);
 543 int tx4939_irq(void);
 544 void tx4939_mtd_init(int ch);
 545 void tx4939_ata_init(void);
 546 void tx4939_rtc_init(void);
 547 void tx4939_ndfmc_init(unsigned int hold, unsigned int spw,
 548                        unsigned char ch_mask, unsigned char wide_mask);
 549 void tx4939_dmac_init(int memcpy_chan0, int memcpy_chan1);
 550 void tx4939_aclc_init(void);
 551 void tx4939_sramc_init(void);
 552 void tx4939_rng_init(void);
 553
 554 #endif /* __ASM_TXX9_TX4939_H */