1 /* cpu.c: Dinky routines to look for the kind of Sparc cpu
4 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
7 #include <linux/seq_file.h>
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/smp.h>
11 #include <linux/export.h>
12 #include <linux/threads.h>
14 #include <asm/spitfire.h>
15 #include <asm/pgtable.h>
16 #include <asm/oplib.h>
17 #include <asm/setup.h>
22 #include <asm/cpudata.h>
26 DEFINE_PER_CPU(cpuinfo_sparc
, __cpu_data
) = { 0 };
27 EXPORT_PER_CPU_SYMBOL(__cpu_data
);
30 unsigned int fsr_storage
;
46 struct manufacturer_info
{
48 struct cpu_info cpu_info
[NOCPU
];
49 struct fpu_info fpu_info
[NOFPU
];
52 #define CPU(ver, _name) \
53 { .psr_vers = ver, .name = _name }
55 #define CPU_PMU(ver, _name, _pmu_name) \
56 { .psr_vers = ver, .name = _name, .pmu_name = _pmu_name }
58 #define FPU(ver, _name) \
59 { .fp_vers = ver, .name = _name }
61 static const struct manufacturer_info __initconst manufacturer_info
[] = {
64 /* Sun4/100, 4/200, SLC */
66 CPU(0, "Fujitsu MB86900/1A or LSI L64831 SparcKIT-40"),
67 /* borned STP1012PGA */
68 CPU(4, "Fujitsu MB86904"),
69 CPU(5, "Fujitsu TurboSparc MB86907"),
73 FPU(0, "Fujitsu MB86910 or Weitek WTL1164/5"),
74 FPU(1, "Fujitsu MB86911 or Weitek WTL1164/5 or LSI L64831"),
75 FPU(2, "LSI Logic L64802 or Texas Instruments ACT8847"),
76 /* SparcStation SLC, SparcStation1 */
77 FPU(3, "Weitek WTL3170/2"),
79 FPU(4, "Lsi Logic/Meiko L64804 or compatible"),
85 /* SparcStation2, SparcServer 490 & 690 */
86 CPU(0, "LSI Logic Corporation - L64811"),
88 CPU(1, "Cypress/ROSS CY7C601"),
89 /* Embedded controller */
90 CPU(3, "Cypress/ROSS CY7C611"),
91 /* Ross Technologies HyperSparc */
92 CPU(0xf, "ROSS HyperSparc RT620"),
93 CPU(0xe, "ROSS HyperSparc RT625 or RT626"),
97 FPU(0, "ROSS HyperSparc combined IU/FPU"),
98 FPU(1, "Lsi Logic L64814"),
99 FPU(2, "Texas Instruments TMS390-C602A"),
100 FPU(3, "Cypress CY7C602 FPU"),
106 /* ECL Implementation, CRAY S-MP Supercomputer... AIEEE! */
107 /* Someone please write the code to support this beast! ;) */
108 CPU(0, "Bipolar Integrated Technology - B5010"),
117 CPU(0, "LSI Logic Corporation - unknown-type"),
126 CPU(0, "Texas Instruments, Inc. - SuperSparc-(II)"),
127 /* SparcClassic -- borned STP1010TAB-50*/
128 CPU(1, "Texas Instruments, Inc. - MicroSparc"),
129 CPU(2, "Texas Instruments, Inc. - MicroSparc II"),
130 CPU(3, "Texas Instruments, Inc. - SuperSparc 51"),
131 CPU(4, "Texas Instruments, Inc. - SuperSparc 61"),
132 CPU(5, "Texas Instruments, Inc. - unknown"),
136 /* SuperSparc 50 module */
137 FPU(0, "SuperSparc on-chip FPU"),
139 FPU(4, "TI MicroSparc on chip FPU"),
145 CPU(0, "Matsushita - MN10501"),
149 FPU(0, "Matsushita MN10501"),
155 CPU(0, "Philips Corporation - unknown"),
164 CPU(0, "Harvest VLSI Design Center, Inc. - unknown"),
173 CPU(0, "Systems and Processes Engineering Corporation (SPEC)"),
182 /* Gallium arsenide 200MHz, BOOOOGOOOOMIPS!!! */
183 CPU(0, "Fujitsu or Weitek Power-UP"),
184 CPU(1, "Fujitsu or Weitek Power-UP"),
185 CPU(2, "Fujitsu or Weitek Power-UP"),
186 CPU(3, "Fujitsu or Weitek Power-UP"),
190 FPU(3, "Fujitsu or Weitek on-chip FPU"),
194 0xF, /* Aeroflex Gaisler */
201 FPU(3, "GRFPU-Lite"),
207 CPU_PMU(0x10, "TI UltraSparc I (SpitFire)", "ultra12"),
208 CPU_PMU(0x11, "TI UltraSparc II (BlackBird)", "ultra12"),
209 CPU_PMU(0x12, "TI UltraSparc IIi (Sabre)", "ultra12"),
210 CPU_PMU(0x13, "TI UltraSparc IIe (Hummingbird)", "ultra12"),
214 FPU(0x10, "UltraSparc I integrated FPU"),
215 FPU(0x11, "UltraSparc II integrated FPU"),
216 FPU(0x12, "UltraSparc IIi integrated FPU"),
217 FPU(0x13, "UltraSparc IIe integrated FPU"),
223 CPU_PMU(0x10, "TI UltraSparc I (SpitFire)", "ultra12"),
227 FPU(0x10, "UltraSparc I integrated FPU"),
233 CPU_PMU(0x14, "TI UltraSparc III (Cheetah)", "ultra3"),
234 CPU_PMU(0x15, "TI UltraSparc III+ (Cheetah+)", "ultra3+"),
235 CPU_PMU(0x16, "TI UltraSparc IIIi (Jalapeno)", "ultra3i"),
236 CPU_PMU(0x18, "TI UltraSparc IV (Jaguar)", "ultra3+"),
237 CPU_PMU(0x19, "TI UltraSparc IV+ (Panther)", "ultra4+"),
238 CPU_PMU(0x22, "TI UltraSparc IIIi+ (Serrano)", "ultra3i"),
242 FPU(0x14, "UltraSparc III integrated FPU"),
243 FPU(0x15, "UltraSparc III+ integrated FPU"),
244 FPU(0x16, "UltraSparc IIIi integrated FPU"),
245 FPU(0x18, "UltraSparc IV integrated FPU"),
246 FPU(0x19, "UltraSparc IV+ integrated FPU"),
247 FPU(0x22, "UltraSparc IIIi+ integrated FPU"),
252 /* In order to get the fpu type correct, you need to take the IDPROM's
253 * machine type value into consideration too. I will fix this.
256 static const char *sparc_cpu_type
;
257 static const char *sparc_fpu_type
;
258 const char *sparc_pmu_type
;
261 static void __init
set_cpu_and_fpu(int psr_impl
, int psr_vers
, int fpu_vers
)
263 const struct manufacturer_info
*manuf
;
266 sparc_cpu_type
= NULL
;
267 sparc_fpu_type
= NULL
;
268 sparc_pmu_type
= NULL
;
271 for (i
= 0; i
< ARRAY_SIZE(manufacturer_info
); i
++)
273 if (psr_impl
== manufacturer_info
[i
].psr_impl
) {
274 manuf
= &manufacturer_info
[i
];
280 const struct cpu_info
*cpu
;
281 const struct fpu_info
*fpu
;
283 cpu
= &manuf
->cpu_info
[0];
284 while (cpu
->psr_vers
!= -1)
286 if (cpu
->psr_vers
== psr_vers
) {
287 sparc_cpu_type
= cpu
->name
;
288 sparc_pmu_type
= cpu
->pmu_name
;
289 sparc_fpu_type
= "No FPU";
294 fpu
= &manuf
->fpu_info
[0];
295 while (fpu
->fp_vers
!= -1)
297 if (fpu
->fp_vers
== fpu_vers
) {
298 sparc_fpu_type
= fpu
->name
;
304 if (sparc_cpu_type
== NULL
)
306 printk(KERN_ERR
"CPU: Unknown chip, impl[0x%x] vers[0x%x]\n",
308 sparc_cpu_type
= "Unknown CPU";
310 if (sparc_fpu_type
== NULL
)
312 printk(KERN_ERR
"FPU: Unknown chip, impl[0x%x] vers[0x%x]\n",
314 sparc_fpu_type
= "Unknown FPU";
316 if (sparc_pmu_type
== NULL
)
317 sparc_pmu_type
= "Unknown PMU";
320 #ifdef CONFIG_SPARC32
321 static int show_cpuinfo(struct seq_file
*m
, void *__unused
)
326 "promlib\t\t: Version %d Revision %d\n"
329 "ncpus probed\t: %d\n"
330 "ncpus active\t: %d\n"
332 "CPU0Bogo\t: %lu.%02lu\n"
333 "CPU0ClkTck\t: %ld\n"
340 romvec
->pv_printrev
>> 16,
341 romvec
->pv_printrev
& 0xffff,
346 , cpu_data(0).udelay_val
/(500000/HZ
),
347 (cpu_data(0).udelay_val
/(5000/HZ
)) % 100,
348 cpu_data(0).clock_tick
361 #endif /* CONFIG_SPARC32 */
363 #ifdef CONFIG_SPARC64
364 unsigned int dcache_parity_tl1_occurred
;
365 unsigned int icache_parity_tl1_occurred
;
368 static int show_cpuinfo(struct seq_file
*m
, void *__unused
)
376 "ncpus probed\t: %d\n"
377 "ncpus active\t: %d\n"
378 "D$ parity tl1\t: %u\n"
379 "I$ parity tl1\t: %u\n"
381 "Cpu0ClkTck\t: %016lx\n"
388 ((tlb_type
== hypervisor
) ?
393 dcache_parity_tl1_occurred
,
394 icache_parity_tl1_occurred
396 , cpu_data(0).clock_tick
409 #endif /* CONFIG_SPARC64 */
411 static void *c_start(struct seq_file
*m
, loff_t
*pos
)
413 /* The pointer we are returning is arbitrary,
414 * it just has to be non-NULL and not IS_ERR
415 * in the success case.
417 return *pos
== 0 ? &c_start
: NULL
;
420 static void *c_next(struct seq_file
*m
, void *v
, loff_t
*pos
)
423 return c_start(m
, pos
);
426 static void c_stop(struct seq_file
*m
, void *v
)
430 const struct seq_operations cpuinfo_op
= {
434 .show
= show_cpuinfo
,
437 #ifdef CONFIG_SPARC32
438 static int __init
cpu_type_probe(void)
440 int psr_impl
, psr_vers
, fpu_vers
;
443 psr_impl
= ((get_psr() >> 28) & 0xf);
444 psr_vers
= ((get_psr() >> 24) & 0xf);
447 put_psr(psr
| PSR_EF
);
448 #ifdef CONFIG_SPARC_LEON
449 fpu_vers
= get_psr() & PSR_EF
? ((get_fsr() >> 17) & 0x7) : 7;
451 fpu_vers
= ((get_fsr() >> 17) & 0x7);
456 set_cpu_and_fpu(psr_impl
, psr_vers
, fpu_vers
);
460 #endif /* CONFIG_SPARC32 */
462 #ifdef CONFIG_SPARC64
463 static void __init
sun4v_cpu_probe(void)
465 switch (sun4v_chip_type
) {
466 case SUN4V_CHIP_NIAGARA1
:
467 sparc_cpu_type
= "UltraSparc T1 (Niagara)";
468 sparc_fpu_type
= "UltraSparc T1 integrated FPU";
469 sparc_pmu_type
= "niagara";
472 case SUN4V_CHIP_NIAGARA2
:
473 sparc_cpu_type
= "UltraSparc T2 (Niagara2)";
474 sparc_fpu_type
= "UltraSparc T2 integrated FPU";
475 sparc_pmu_type
= "niagara2";
478 case SUN4V_CHIP_NIAGARA3
:
479 sparc_cpu_type
= "UltraSparc T3 (Niagara3)";
480 sparc_fpu_type
= "UltraSparc T3 integrated FPU";
481 sparc_pmu_type
= "niagara3";
485 printk(KERN_WARNING
"CPU: Unknown sun4v cpu type [%s]\n",
486 prom_cpu_compatible
);
487 sparc_cpu_type
= "Unknown SUN4V CPU";
488 sparc_fpu_type
= "Unknown SUN4V FPU";
489 sparc_pmu_type
= "Unknown SUN4V PMU";
494 static int __init
cpu_type_probe(void)
496 if (tlb_type
== hypervisor
) {
502 __asm__
__volatile__("rdpr %%ver, %0" : "=r" (ver
));
504 manuf
= ((ver
>> 48) & 0xffff);
505 impl
= ((ver
>> 32) & 0xffff);
506 set_cpu_and_fpu(manuf
, impl
, impl
);
510 #endif /* CONFIG_SPARC64 */
512 early_initcall(cpu_type_probe
);