2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
11 * Thanks to the following companies for their support:
13 * - JMicron (hardware and technical support)
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
19 #include <linux/module.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/scatterlist.h>
23 #include <linux/regulator/consumer.h>
25 #include <linux/leds.h>
27 #include <linux/mmc/mmc.h>
28 #include <linux/mmc/host.h>
32 #define DRIVER_NAME "sdhci"
34 #define DBG(f, x...) \
35 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
37 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
38 defined(CONFIG_MMC_SDHCI_MODULE))
39 #define SDHCI_USE_LEDS_CLASS
42 #define MAX_TUNING_LOOP 40
44 static unsigned int debug_quirks
= 0;
46 static void sdhci_finish_data(struct sdhci_host
*);
48 static void sdhci_send_command(struct sdhci_host
*, struct mmc_command
*);
49 static void sdhci_finish_command(struct sdhci_host
*);
50 static int sdhci_execute_tuning(struct mmc_host
*mmc
);
51 static void sdhci_tuning_timer(unsigned long data
);
53 static void sdhci_dumpregs(struct sdhci_host
*host
)
55 printk(KERN_DEBUG DRIVER_NAME
": =========== REGISTER DUMP (%s)===========\n",
56 mmc_hostname(host
->mmc
));
58 printk(KERN_DEBUG DRIVER_NAME
": Sys addr: 0x%08x | Version: 0x%08x\n",
59 sdhci_readl(host
, SDHCI_DMA_ADDRESS
),
60 sdhci_readw(host
, SDHCI_HOST_VERSION
));
61 printk(KERN_DEBUG DRIVER_NAME
": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
62 sdhci_readw(host
, SDHCI_BLOCK_SIZE
),
63 sdhci_readw(host
, SDHCI_BLOCK_COUNT
));
64 printk(KERN_DEBUG DRIVER_NAME
": Argument: 0x%08x | Trn mode: 0x%08x\n",
65 sdhci_readl(host
, SDHCI_ARGUMENT
),
66 sdhci_readw(host
, SDHCI_TRANSFER_MODE
));
67 printk(KERN_DEBUG DRIVER_NAME
": Present: 0x%08x | Host ctl: 0x%08x\n",
68 sdhci_readl(host
, SDHCI_PRESENT_STATE
),
69 sdhci_readb(host
, SDHCI_HOST_CONTROL
));
70 printk(KERN_DEBUG DRIVER_NAME
": Power: 0x%08x | Blk gap: 0x%08x\n",
71 sdhci_readb(host
, SDHCI_POWER_CONTROL
),
72 sdhci_readb(host
, SDHCI_BLOCK_GAP_CONTROL
));
73 printk(KERN_DEBUG DRIVER_NAME
": Wake-up: 0x%08x | Clock: 0x%08x\n",
74 sdhci_readb(host
, SDHCI_WAKE_UP_CONTROL
),
75 sdhci_readw(host
, SDHCI_CLOCK_CONTROL
));
76 printk(KERN_DEBUG DRIVER_NAME
": Timeout: 0x%08x | Int stat: 0x%08x\n",
77 sdhci_readb(host
, SDHCI_TIMEOUT_CONTROL
),
78 sdhci_readl(host
, SDHCI_INT_STATUS
));
79 printk(KERN_DEBUG DRIVER_NAME
": Int enab: 0x%08x | Sig enab: 0x%08x\n",
80 sdhci_readl(host
, SDHCI_INT_ENABLE
),
81 sdhci_readl(host
, SDHCI_SIGNAL_ENABLE
));
82 printk(KERN_DEBUG DRIVER_NAME
": AC12 err: 0x%08x | Slot int: 0x%08x\n",
83 sdhci_readw(host
, SDHCI_ACMD12_ERR
),
84 sdhci_readw(host
, SDHCI_SLOT_INT_STATUS
));
85 printk(KERN_DEBUG DRIVER_NAME
": Caps: 0x%08x | Caps_1: 0x%08x\n",
86 sdhci_readl(host
, SDHCI_CAPABILITIES
),
87 sdhci_readl(host
, SDHCI_CAPABILITIES_1
));
88 printk(KERN_DEBUG DRIVER_NAME
": Cmd: 0x%08x | Max curr: 0x%08x\n",
89 sdhci_readw(host
, SDHCI_COMMAND
),
90 sdhci_readl(host
, SDHCI_MAX_CURRENT
));
91 printk(KERN_DEBUG DRIVER_NAME
": Host ctl2: 0x%08x\n",
92 sdhci_readw(host
, SDHCI_HOST_CONTROL2
));
94 if (host
->flags
& SDHCI_USE_ADMA
)
95 printk(KERN_DEBUG DRIVER_NAME
": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
96 readl(host
->ioaddr
+ SDHCI_ADMA_ERROR
),
97 readl(host
->ioaddr
+ SDHCI_ADMA_ADDRESS
));
99 printk(KERN_DEBUG DRIVER_NAME
": ===========================================\n");
102 /*****************************************************************************\
104 * Low level functions *
106 \*****************************************************************************/
108 static void sdhci_clear_set_irqs(struct sdhci_host
*host
, u32 clear
, u32 set
)
112 ier
= sdhci_readl(host
, SDHCI_INT_ENABLE
);
115 sdhci_writel(host
, ier
, SDHCI_INT_ENABLE
);
116 sdhci_writel(host
, ier
, SDHCI_SIGNAL_ENABLE
);
119 static void sdhci_unmask_irqs(struct sdhci_host
*host
, u32 irqs
)
121 sdhci_clear_set_irqs(host
, 0, irqs
);
124 static void sdhci_mask_irqs(struct sdhci_host
*host
, u32 irqs
)
126 sdhci_clear_set_irqs(host
, irqs
, 0);
129 static void sdhci_set_card_detection(struct sdhci_host
*host
, bool enable
)
133 if (host
->quirks
& SDHCI_QUIRK_BROKEN_CARD_DETECTION
)
136 present
= sdhci_readl(host
, SDHCI_PRESENT_STATE
) &
138 irqs
= present
? SDHCI_INT_CARD_REMOVE
: SDHCI_INT_CARD_INSERT
;
141 sdhci_unmask_irqs(host
, irqs
);
143 sdhci_mask_irqs(host
, irqs
);
146 static void sdhci_enable_card_detection(struct sdhci_host
*host
)
148 sdhci_set_card_detection(host
, true);
151 static void sdhci_disable_card_detection(struct sdhci_host
*host
)
153 sdhci_set_card_detection(host
, false);
156 static void sdhci_reset(struct sdhci_host
*host
, u8 mask
)
158 unsigned long timeout
;
159 u32
uninitialized_var(ier
);
161 if (host
->quirks
& SDHCI_QUIRK_NO_CARD_NO_RESET
) {
162 if (!(sdhci_readl(host
, SDHCI_PRESENT_STATE
) &
167 if (host
->quirks
& SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET
)
168 ier
= sdhci_readl(host
, SDHCI_INT_ENABLE
);
170 if (host
->ops
->platform_reset_enter
)
171 host
->ops
->platform_reset_enter(host
, mask
);
173 sdhci_writeb(host
, mask
, SDHCI_SOFTWARE_RESET
);
175 if (mask
& SDHCI_RESET_ALL
)
178 /* Wait max 100 ms */
181 /* hw clears the bit when it's done */
182 while (sdhci_readb(host
, SDHCI_SOFTWARE_RESET
) & mask
) {
184 printk(KERN_ERR
"%s: Reset 0x%x never completed.\n",
185 mmc_hostname(host
->mmc
), (int)mask
);
186 sdhci_dumpregs(host
);
193 if (host
->ops
->platform_reset_exit
)
194 host
->ops
->platform_reset_exit(host
, mask
);
196 if (host
->quirks
& SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET
)
197 sdhci_clear_set_irqs(host
, SDHCI_INT_ALL_MASK
, ier
);
200 static void sdhci_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
);
202 static void sdhci_init(struct sdhci_host
*host
, int soft
)
205 sdhci_reset(host
, SDHCI_RESET_CMD
|SDHCI_RESET_DATA
);
207 sdhci_reset(host
, SDHCI_RESET_ALL
);
209 sdhci_clear_set_irqs(host
, SDHCI_INT_ALL_MASK
,
210 SDHCI_INT_BUS_POWER
| SDHCI_INT_DATA_END_BIT
|
211 SDHCI_INT_DATA_CRC
| SDHCI_INT_DATA_TIMEOUT
| SDHCI_INT_INDEX
|
212 SDHCI_INT_END_BIT
| SDHCI_INT_CRC
| SDHCI_INT_TIMEOUT
|
213 SDHCI_INT_DATA_END
| SDHCI_INT_RESPONSE
);
216 /* force clock reconfiguration */
218 sdhci_set_ios(host
->mmc
, &host
->mmc
->ios
);
222 static void sdhci_reinit(struct sdhci_host
*host
)
225 sdhci_enable_card_detection(host
);
228 static void sdhci_activate_led(struct sdhci_host
*host
)
232 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
233 ctrl
|= SDHCI_CTRL_LED
;
234 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
237 static void sdhci_deactivate_led(struct sdhci_host
*host
)
241 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
242 ctrl
&= ~SDHCI_CTRL_LED
;
243 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
246 #ifdef SDHCI_USE_LEDS_CLASS
247 static void sdhci_led_control(struct led_classdev
*led
,
248 enum led_brightness brightness
)
250 struct sdhci_host
*host
= container_of(led
, struct sdhci_host
, led
);
253 spin_lock_irqsave(&host
->lock
, flags
);
255 if (brightness
== LED_OFF
)
256 sdhci_deactivate_led(host
);
258 sdhci_activate_led(host
);
260 spin_unlock_irqrestore(&host
->lock
, flags
);
264 /*****************************************************************************\
268 \*****************************************************************************/
270 static void sdhci_read_block_pio(struct sdhci_host
*host
)
273 size_t blksize
, len
, chunk
;
274 u32
uninitialized_var(scratch
);
277 DBG("PIO reading\n");
279 blksize
= host
->data
->blksz
;
282 local_irq_save(flags
);
285 if (!sg_miter_next(&host
->sg_miter
))
288 len
= min(host
->sg_miter
.length
, blksize
);
291 host
->sg_miter
.consumed
= len
;
293 buf
= host
->sg_miter
.addr
;
297 scratch
= sdhci_readl(host
, SDHCI_BUFFER
);
301 *buf
= scratch
& 0xFF;
310 sg_miter_stop(&host
->sg_miter
);
312 local_irq_restore(flags
);
315 static void sdhci_write_block_pio(struct sdhci_host
*host
)
318 size_t blksize
, len
, chunk
;
322 DBG("PIO writing\n");
324 blksize
= host
->data
->blksz
;
328 local_irq_save(flags
);
331 if (!sg_miter_next(&host
->sg_miter
))
334 len
= min(host
->sg_miter
.length
, blksize
);
337 host
->sg_miter
.consumed
= len
;
339 buf
= host
->sg_miter
.addr
;
342 scratch
|= (u32
)*buf
<< (chunk
* 8);
348 if ((chunk
== 4) || ((len
== 0) && (blksize
== 0))) {
349 sdhci_writel(host
, scratch
, SDHCI_BUFFER
);
356 sg_miter_stop(&host
->sg_miter
);
358 local_irq_restore(flags
);
361 static void sdhci_transfer_pio(struct sdhci_host
*host
)
367 if (host
->blocks
== 0)
370 if (host
->data
->flags
& MMC_DATA_READ
)
371 mask
= SDHCI_DATA_AVAILABLE
;
373 mask
= SDHCI_SPACE_AVAILABLE
;
376 * Some controllers (JMicron JMB38x) mess up the buffer bits
377 * for transfers < 4 bytes. As long as it is just one block,
378 * we can ignore the bits.
380 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_SMALL_PIO
) &&
381 (host
->data
->blocks
== 1))
384 while (sdhci_readl(host
, SDHCI_PRESENT_STATE
) & mask
) {
385 if (host
->quirks
& SDHCI_QUIRK_PIO_NEEDS_DELAY
)
388 if (host
->data
->flags
& MMC_DATA_READ
)
389 sdhci_read_block_pio(host
);
391 sdhci_write_block_pio(host
);
394 if (host
->blocks
== 0)
398 DBG("PIO transfer complete.\n");
401 static char *sdhci_kmap_atomic(struct scatterlist
*sg
, unsigned long *flags
)
403 local_irq_save(*flags
);
404 return kmap_atomic(sg_page(sg
), KM_BIO_SRC_IRQ
) + sg
->offset
;
407 static void sdhci_kunmap_atomic(void *buffer
, unsigned long *flags
)
409 kunmap_atomic(buffer
, KM_BIO_SRC_IRQ
);
410 local_irq_restore(*flags
);
413 static void sdhci_set_adma_desc(u8
*desc
, u32 addr
, int len
, unsigned cmd
)
415 __le32
*dataddr
= (__le32 __force
*)(desc
+ 4);
416 __le16
*cmdlen
= (__le16 __force
*)desc
;
418 /* SDHCI specification says ADMA descriptors should be 4 byte
419 * aligned, so using 16 or 32bit operations should be safe. */
421 cmdlen
[0] = cpu_to_le16(cmd
);
422 cmdlen
[1] = cpu_to_le16(len
);
424 dataddr
[0] = cpu_to_le32(addr
);
427 static int sdhci_adma_table_pre(struct sdhci_host
*host
,
428 struct mmc_data
*data
)
435 dma_addr_t align_addr
;
438 struct scatterlist
*sg
;
444 * The spec does not specify endianness of descriptor table.
445 * We currently guess that it is LE.
448 if (data
->flags
& MMC_DATA_READ
)
449 direction
= DMA_FROM_DEVICE
;
451 direction
= DMA_TO_DEVICE
;
454 * The ADMA descriptor table is mapped further down as we
455 * need to fill it with data first.
458 host
->align_addr
= dma_map_single(mmc_dev(host
->mmc
),
459 host
->align_buffer
, 128 * 4, direction
);
460 if (dma_mapping_error(mmc_dev(host
->mmc
), host
->align_addr
))
462 BUG_ON(host
->align_addr
& 0x3);
464 host
->sg_count
= dma_map_sg(mmc_dev(host
->mmc
),
465 data
->sg
, data
->sg_len
, direction
);
466 if (host
->sg_count
== 0)
469 desc
= host
->adma_desc
;
470 align
= host
->align_buffer
;
472 align_addr
= host
->align_addr
;
474 for_each_sg(data
->sg
, sg
, host
->sg_count
, i
) {
475 addr
= sg_dma_address(sg
);
476 len
= sg_dma_len(sg
);
479 * The SDHCI specification states that ADMA
480 * addresses must be 32-bit aligned. If they
481 * aren't, then we use a bounce buffer for
482 * the (up to three) bytes that screw up the
485 offset
= (4 - (addr
& 0x3)) & 0x3;
487 if (data
->flags
& MMC_DATA_WRITE
) {
488 buffer
= sdhci_kmap_atomic(sg
, &flags
);
489 WARN_ON(((long)buffer
& PAGE_MASK
) > (PAGE_SIZE
- 3));
490 memcpy(align
, buffer
, offset
);
491 sdhci_kunmap_atomic(buffer
, &flags
);
495 sdhci_set_adma_desc(desc
, align_addr
, offset
, 0x21);
497 BUG_ON(offset
> 65536);
511 sdhci_set_adma_desc(desc
, addr
, len
, 0x21);
515 * If this triggers then we have a calculation bug
518 WARN_ON((desc
- host
->adma_desc
) > (128 * 2 + 1) * 4);
521 if (host
->quirks
& SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
) {
523 * Mark the last descriptor as the terminating descriptor
525 if (desc
!= host
->adma_desc
) {
527 desc
[0] |= 0x2; /* end */
531 * Add a terminating entry.
534 /* nop, end, valid */
535 sdhci_set_adma_desc(desc
, 0, 0, 0x3);
539 * Resync align buffer as we might have changed it.
541 if (data
->flags
& MMC_DATA_WRITE
) {
542 dma_sync_single_for_device(mmc_dev(host
->mmc
),
543 host
->align_addr
, 128 * 4, direction
);
546 host
->adma_addr
= dma_map_single(mmc_dev(host
->mmc
),
547 host
->adma_desc
, (128 * 2 + 1) * 4, DMA_TO_DEVICE
);
548 if (dma_mapping_error(mmc_dev(host
->mmc
), host
->adma_addr
))
550 BUG_ON(host
->adma_addr
& 0x3);
555 dma_unmap_sg(mmc_dev(host
->mmc
), data
->sg
,
556 data
->sg_len
, direction
);
558 dma_unmap_single(mmc_dev(host
->mmc
), host
->align_addr
,
564 static void sdhci_adma_table_post(struct sdhci_host
*host
,
565 struct mmc_data
*data
)
569 struct scatterlist
*sg
;
575 if (data
->flags
& MMC_DATA_READ
)
576 direction
= DMA_FROM_DEVICE
;
578 direction
= DMA_TO_DEVICE
;
580 dma_unmap_single(mmc_dev(host
->mmc
), host
->adma_addr
,
581 (128 * 2 + 1) * 4, DMA_TO_DEVICE
);
583 dma_unmap_single(mmc_dev(host
->mmc
), host
->align_addr
,
586 if (data
->flags
& MMC_DATA_READ
) {
587 dma_sync_sg_for_cpu(mmc_dev(host
->mmc
), data
->sg
,
588 data
->sg_len
, direction
);
590 align
= host
->align_buffer
;
592 for_each_sg(data
->sg
, sg
, host
->sg_count
, i
) {
593 if (sg_dma_address(sg
) & 0x3) {
594 size
= 4 - (sg_dma_address(sg
) & 0x3);
596 buffer
= sdhci_kmap_atomic(sg
, &flags
);
597 WARN_ON(((long)buffer
& PAGE_MASK
) > (PAGE_SIZE
- 3));
598 memcpy(buffer
, align
, size
);
599 sdhci_kunmap_atomic(buffer
, &flags
);
606 dma_unmap_sg(mmc_dev(host
->mmc
), data
->sg
,
607 data
->sg_len
, direction
);
610 static u8
sdhci_calc_timeout(struct sdhci_host
*host
, struct mmc_command
*cmd
)
613 struct mmc_data
*data
= cmd
->data
;
614 unsigned target_timeout
, current_timeout
;
617 * If the host controller provides us with an incorrect timeout
618 * value, just skip the check and use 0xE. The hardware may take
619 * longer to time out, but that's much better than having a too-short
622 if (host
->quirks
& SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
)
625 /* Unspecified timeout, assume max */
626 if (!data
&& !cmd
->cmd_timeout_ms
)
631 target_timeout
= cmd
->cmd_timeout_ms
* 1000;
633 target_timeout
= data
->timeout_ns
/ 1000;
635 target_timeout
+= data
->timeout_clks
/ host
->clock
;
639 * Figure out needed cycles.
640 * We do this in steps in order to fit inside a 32 bit int.
641 * The first step is the minimum timeout, which will have a
642 * minimum resolution of 6 bits:
643 * (1) 2^13*1000 > 2^22,
644 * (2) host->timeout_clk < 2^16
649 current_timeout
= (1 << 13) * 1000 / host
->timeout_clk
;
650 while (current_timeout
< target_timeout
) {
652 current_timeout
<<= 1;
658 printk(KERN_WARNING
"%s: Too large timeout requested for CMD%d!\n",
659 mmc_hostname(host
->mmc
), cmd
->opcode
);
666 static void sdhci_set_transfer_irqs(struct sdhci_host
*host
)
668 u32 pio_irqs
= SDHCI_INT_DATA_AVAIL
| SDHCI_INT_SPACE_AVAIL
;
669 u32 dma_irqs
= SDHCI_INT_DMA_END
| SDHCI_INT_ADMA_ERROR
;
671 if (host
->flags
& SDHCI_REQ_USE_DMA
)
672 sdhci_clear_set_irqs(host
, pio_irqs
, dma_irqs
);
674 sdhci_clear_set_irqs(host
, dma_irqs
, pio_irqs
);
677 static void sdhci_prepare_data(struct sdhci_host
*host
, struct mmc_command
*cmd
)
681 struct mmc_data
*data
= cmd
->data
;
686 if (data
|| (cmd
->flags
& MMC_RSP_BUSY
)) {
687 count
= sdhci_calc_timeout(host
, cmd
);
688 sdhci_writeb(host
, count
, SDHCI_TIMEOUT_CONTROL
);
695 BUG_ON(data
->blksz
* data
->blocks
> 524288);
696 BUG_ON(data
->blksz
> host
->mmc
->max_blk_size
);
697 BUG_ON(data
->blocks
> 65535);
700 host
->data_early
= 0;
701 host
->data
->bytes_xfered
= 0;
703 if (host
->flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
))
704 host
->flags
|= SDHCI_REQ_USE_DMA
;
707 * FIXME: This doesn't account for merging when mapping the
710 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
712 struct scatterlist
*sg
;
715 if (host
->flags
& SDHCI_USE_ADMA
) {
716 if (host
->quirks
& SDHCI_QUIRK_32BIT_ADMA_SIZE
)
719 if (host
->quirks
& SDHCI_QUIRK_32BIT_DMA_SIZE
)
723 if (unlikely(broken
)) {
724 for_each_sg(data
->sg
, sg
, data
->sg_len
, i
) {
725 if (sg
->length
& 0x3) {
726 DBG("Reverting to PIO because of "
727 "transfer size (%d)\n",
729 host
->flags
&= ~SDHCI_REQ_USE_DMA
;
737 * The assumption here being that alignment is the same after
738 * translation to device address space.
740 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
742 struct scatterlist
*sg
;
745 if (host
->flags
& SDHCI_USE_ADMA
) {
747 * As we use 3 byte chunks to work around
748 * alignment problems, we need to check this
751 if (host
->quirks
& SDHCI_QUIRK_32BIT_ADMA_SIZE
)
754 if (host
->quirks
& SDHCI_QUIRK_32BIT_DMA_ADDR
)
758 if (unlikely(broken
)) {
759 for_each_sg(data
->sg
, sg
, data
->sg_len
, i
) {
760 if (sg
->offset
& 0x3) {
761 DBG("Reverting to PIO because of "
763 host
->flags
&= ~SDHCI_REQ_USE_DMA
;
770 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
771 if (host
->flags
& SDHCI_USE_ADMA
) {
772 ret
= sdhci_adma_table_pre(host
, data
);
775 * This only happens when someone fed
776 * us an invalid request.
779 host
->flags
&= ~SDHCI_REQ_USE_DMA
;
781 sdhci_writel(host
, host
->adma_addr
,
787 sg_cnt
= dma_map_sg(mmc_dev(host
->mmc
),
788 data
->sg
, data
->sg_len
,
789 (data
->flags
& MMC_DATA_READ
) ?
794 * This only happens when someone fed
795 * us an invalid request.
798 host
->flags
&= ~SDHCI_REQ_USE_DMA
;
800 WARN_ON(sg_cnt
!= 1);
801 sdhci_writel(host
, sg_dma_address(data
->sg
),
808 * Always adjust the DMA selection as some controllers
809 * (e.g. JMicron) can't do PIO properly when the selection
812 if (host
->version
>= SDHCI_SPEC_200
) {
813 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
814 ctrl
&= ~SDHCI_CTRL_DMA_MASK
;
815 if ((host
->flags
& SDHCI_REQ_USE_DMA
) &&
816 (host
->flags
& SDHCI_USE_ADMA
))
817 ctrl
|= SDHCI_CTRL_ADMA32
;
819 ctrl
|= SDHCI_CTRL_SDMA
;
820 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
823 if (!(host
->flags
& SDHCI_REQ_USE_DMA
)) {
826 flags
= SG_MITER_ATOMIC
;
827 if (host
->data
->flags
& MMC_DATA_READ
)
828 flags
|= SG_MITER_TO_SG
;
830 flags
|= SG_MITER_FROM_SG
;
831 sg_miter_start(&host
->sg_miter
, data
->sg
, data
->sg_len
, flags
);
832 host
->blocks
= data
->blocks
;
835 sdhci_set_transfer_irqs(host
);
837 /* Set the DMA boundary value and block size */
838 sdhci_writew(host
, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG
,
839 data
->blksz
), SDHCI_BLOCK_SIZE
);
840 sdhci_writew(host
, data
->blocks
, SDHCI_BLOCK_COUNT
);
843 static void sdhci_set_transfer_mode(struct sdhci_host
*host
,
844 struct mmc_command
*cmd
)
847 struct mmc_data
*data
= cmd
->data
;
852 WARN_ON(!host
->data
);
854 mode
= SDHCI_TRNS_BLK_CNT_EN
;
855 if (mmc_op_multi(cmd
->opcode
) || data
->blocks
> 1) {
856 mode
|= SDHCI_TRNS_MULTI
;
858 * If we are sending CMD23, CMD12 never gets sent
859 * on successful completion (so no Auto-CMD12).
861 if (!host
->mrq
->sbc
&& (host
->flags
& SDHCI_AUTO_CMD12
))
862 mode
|= SDHCI_TRNS_AUTO_CMD12
;
863 else if (host
->mrq
->sbc
&& (host
->flags
& SDHCI_AUTO_CMD23
)) {
864 mode
|= SDHCI_TRNS_AUTO_CMD23
;
865 sdhci_writel(host
, host
->mrq
->sbc
->arg
, SDHCI_ARGUMENT2
);
869 if (data
->flags
& MMC_DATA_READ
)
870 mode
|= SDHCI_TRNS_READ
;
871 if (host
->flags
& SDHCI_REQ_USE_DMA
)
872 mode
|= SDHCI_TRNS_DMA
;
874 sdhci_writew(host
, mode
, SDHCI_TRANSFER_MODE
);
877 static void sdhci_finish_data(struct sdhci_host
*host
)
879 struct mmc_data
*data
;
886 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
887 if (host
->flags
& SDHCI_USE_ADMA
)
888 sdhci_adma_table_post(host
, data
);
890 dma_unmap_sg(mmc_dev(host
->mmc
), data
->sg
,
891 data
->sg_len
, (data
->flags
& MMC_DATA_READ
) ?
892 DMA_FROM_DEVICE
: DMA_TO_DEVICE
);
897 * The specification states that the block count register must
898 * be updated, but it does not specify at what point in the
899 * data flow. That makes the register entirely useless to read
900 * back so we have to assume that nothing made it to the card
901 * in the event of an error.
904 data
->bytes_xfered
= 0;
906 data
->bytes_xfered
= data
->blksz
* data
->blocks
;
909 * Need to send CMD12 if -
910 * a) open-ended multiblock transfer (no CMD23)
911 * b) error in multiblock transfer
918 * The controller needs a reset of internal state machines
919 * upon error conditions.
922 sdhci_reset(host
, SDHCI_RESET_CMD
);
923 sdhci_reset(host
, SDHCI_RESET_DATA
);
926 sdhci_send_command(host
, data
->stop
);
928 tasklet_schedule(&host
->finish_tasklet
);
931 static void sdhci_send_command(struct sdhci_host
*host
, struct mmc_command
*cmd
)
935 unsigned long timeout
;
942 mask
= SDHCI_CMD_INHIBIT
;
943 if ((cmd
->data
!= NULL
) || (cmd
->flags
& MMC_RSP_BUSY
))
944 mask
|= SDHCI_DATA_INHIBIT
;
946 /* We shouldn't wait for data inihibit for stop commands, even
947 though they might use busy signaling */
948 if (host
->mrq
->data
&& (cmd
== host
->mrq
->data
->stop
))
949 mask
&= ~SDHCI_DATA_INHIBIT
;
951 while (sdhci_readl(host
, SDHCI_PRESENT_STATE
) & mask
) {
953 printk(KERN_ERR
"%s: Controller never released "
954 "inhibit bit(s).\n", mmc_hostname(host
->mmc
));
955 sdhci_dumpregs(host
);
957 tasklet_schedule(&host
->finish_tasklet
);
964 mod_timer(&host
->timer
, jiffies
+ 10 * HZ
);
968 sdhci_prepare_data(host
, cmd
);
970 sdhci_writel(host
, cmd
->arg
, SDHCI_ARGUMENT
);
972 sdhci_set_transfer_mode(host
, cmd
);
974 if ((cmd
->flags
& MMC_RSP_136
) && (cmd
->flags
& MMC_RSP_BUSY
)) {
975 printk(KERN_ERR
"%s: Unsupported response type!\n",
976 mmc_hostname(host
->mmc
));
977 cmd
->error
= -EINVAL
;
978 tasklet_schedule(&host
->finish_tasklet
);
982 if (!(cmd
->flags
& MMC_RSP_PRESENT
))
983 flags
= SDHCI_CMD_RESP_NONE
;
984 else if (cmd
->flags
& MMC_RSP_136
)
985 flags
= SDHCI_CMD_RESP_LONG
;
986 else if (cmd
->flags
& MMC_RSP_BUSY
)
987 flags
= SDHCI_CMD_RESP_SHORT_BUSY
;
989 flags
= SDHCI_CMD_RESP_SHORT
;
991 if (cmd
->flags
& MMC_RSP_CRC
)
992 flags
|= SDHCI_CMD_CRC
;
993 if (cmd
->flags
& MMC_RSP_OPCODE
)
994 flags
|= SDHCI_CMD_INDEX
;
996 /* CMD19 is special in that the Data Present Select should be set */
997 if (cmd
->data
|| (cmd
->opcode
== MMC_SEND_TUNING_BLOCK
))
998 flags
|= SDHCI_CMD_DATA
;
1000 sdhci_writew(host
, SDHCI_MAKE_CMD(cmd
->opcode
, flags
), SDHCI_COMMAND
);
1003 static void sdhci_finish_command(struct sdhci_host
*host
)
1007 BUG_ON(host
->cmd
== NULL
);
1009 if (host
->cmd
->flags
& MMC_RSP_PRESENT
) {
1010 if (host
->cmd
->flags
& MMC_RSP_136
) {
1011 /* CRC is stripped so we need to do some shifting. */
1012 for (i
= 0;i
< 4;i
++) {
1013 host
->cmd
->resp
[i
] = sdhci_readl(host
,
1014 SDHCI_RESPONSE
+ (3-i
)*4) << 8;
1016 host
->cmd
->resp
[i
] |=
1018 SDHCI_RESPONSE
+ (3-i
)*4-1);
1021 host
->cmd
->resp
[0] = sdhci_readl(host
, SDHCI_RESPONSE
);
1025 host
->cmd
->error
= 0;
1027 /* Finished CMD23, now send actual command. */
1028 if (host
->cmd
== host
->mrq
->sbc
) {
1030 sdhci_send_command(host
, host
->mrq
->cmd
);
1033 /* Processed actual command. */
1034 if (host
->data
&& host
->data_early
)
1035 sdhci_finish_data(host
);
1037 if (!host
->cmd
->data
)
1038 tasklet_schedule(&host
->finish_tasklet
);
1044 static void sdhci_set_clock(struct sdhci_host
*host
, unsigned int clock
)
1046 int div
= 0; /* Initialized for compiler warning */
1048 unsigned long timeout
;
1050 if (clock
== host
->clock
)
1053 if (host
->ops
->set_clock
) {
1054 host
->ops
->set_clock(host
, clock
);
1055 if (host
->quirks
& SDHCI_QUIRK_NONSTANDARD_CLOCK
)
1059 sdhci_writew(host
, 0, SDHCI_CLOCK_CONTROL
);
1064 if (host
->version
>= SDHCI_SPEC_300
) {
1066 * Check if the Host Controller supports Programmable Clock
1069 if (host
->clk_mul
) {
1073 * We need to figure out whether the Host Driver needs
1074 * to select Programmable Clock Mode, or the value can
1075 * be set automatically by the Host Controller based on
1076 * the Preset Value registers.
1078 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1079 if (!(ctrl
& SDHCI_CTRL_PRESET_VAL_ENABLE
)) {
1080 for (div
= 1; div
<= 1024; div
++) {
1081 if (((host
->max_clk
* host
->clk_mul
) /
1086 * Set Programmable Clock Mode in the Clock
1089 clk
= SDHCI_PROG_CLOCK_MODE
;
1093 /* Version 3.00 divisors must be a multiple of 2. */
1094 if (host
->max_clk
<= clock
)
1097 for (div
= 2; div
< SDHCI_MAX_DIV_SPEC_300
;
1099 if ((host
->max_clk
/ div
) <= clock
)
1106 /* Version 2.00 divisors must be a power of 2. */
1107 for (div
= 1; div
< SDHCI_MAX_DIV_SPEC_200
; div
*= 2) {
1108 if ((host
->max_clk
/ div
) <= clock
)
1114 clk
|= (div
& SDHCI_DIV_MASK
) << SDHCI_DIVIDER_SHIFT
;
1115 clk
|= ((div
& SDHCI_DIV_HI_MASK
) >> SDHCI_DIV_MASK_LEN
)
1116 << SDHCI_DIVIDER_HI_SHIFT
;
1117 clk
|= SDHCI_CLOCK_INT_EN
;
1118 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
1120 /* Wait max 20 ms */
1122 while (!((clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
))
1123 & SDHCI_CLOCK_INT_STABLE
)) {
1125 printk(KERN_ERR
"%s: Internal clock never "
1126 "stabilised.\n", mmc_hostname(host
->mmc
));
1127 sdhci_dumpregs(host
);
1134 clk
|= SDHCI_CLOCK_CARD_EN
;
1135 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
1138 host
->clock
= clock
;
1141 static void sdhci_set_power(struct sdhci_host
*host
, unsigned short power
)
1145 if (power
!= (unsigned short)-1) {
1146 switch (1 << power
) {
1147 case MMC_VDD_165_195
:
1148 pwr
= SDHCI_POWER_180
;
1152 pwr
= SDHCI_POWER_300
;
1156 pwr
= SDHCI_POWER_330
;
1163 if (host
->pwr
== pwr
)
1169 sdhci_writeb(host
, 0, SDHCI_POWER_CONTROL
);
1174 * Spec says that we should clear the power reg before setting
1175 * a new value. Some controllers don't seem to like this though.
1177 if (!(host
->quirks
& SDHCI_QUIRK_SINGLE_POWER_WRITE
))
1178 sdhci_writeb(host
, 0, SDHCI_POWER_CONTROL
);
1181 * At least the Marvell CaFe chip gets confused if we set the voltage
1182 * and set turn on power at the same time, so set the voltage first.
1184 if (host
->quirks
& SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER
)
1185 sdhci_writeb(host
, pwr
, SDHCI_POWER_CONTROL
);
1187 pwr
|= SDHCI_POWER_ON
;
1189 sdhci_writeb(host
, pwr
, SDHCI_POWER_CONTROL
);
1192 * Some controllers need an extra 10ms delay of 10ms before they
1193 * can apply clock after applying power
1195 if (host
->quirks
& SDHCI_QUIRK_DELAY_AFTER_POWER
)
1199 /*****************************************************************************\
1203 \*****************************************************************************/
1205 static void sdhci_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
1207 struct sdhci_host
*host
;
1209 unsigned long flags
;
1211 host
= mmc_priv(mmc
);
1213 spin_lock_irqsave(&host
->lock
, flags
);
1215 WARN_ON(host
->mrq
!= NULL
);
1217 #ifndef SDHCI_USE_LEDS_CLASS
1218 sdhci_activate_led(host
);
1222 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1223 * requests if Auto-CMD12 is enabled.
1225 if (!mrq
->sbc
&& (host
->flags
& SDHCI_AUTO_CMD12
)) {
1227 mrq
->data
->stop
= NULL
;
1234 /* If polling, assume that the card is always present. */
1235 if (host
->quirks
& SDHCI_QUIRK_BROKEN_CARD_DETECTION
)
1238 present
= sdhci_readl(host
, SDHCI_PRESENT_STATE
) &
1241 if (!present
|| host
->flags
& SDHCI_DEVICE_DEAD
) {
1242 host
->mrq
->cmd
->error
= -ENOMEDIUM
;
1243 tasklet_schedule(&host
->finish_tasklet
);
1247 present_state
= sdhci_readl(host
, SDHCI_PRESENT_STATE
);
1249 * Check if the re-tuning timer has already expired and there
1250 * is no on-going data transfer. If so, we need to execute
1251 * tuning procedure before sending command.
1253 if ((host
->flags
& SDHCI_NEEDS_RETUNING
) &&
1254 !(present_state
& (SDHCI_DOING_WRITE
| SDHCI_DOING_READ
))) {
1255 spin_unlock_irqrestore(&host
->lock
, flags
);
1256 sdhci_execute_tuning(mmc
);
1257 spin_lock_irqsave(&host
->lock
, flags
);
1259 /* Restore original mmc_request structure */
1263 if (mrq
->sbc
&& !(host
->flags
& SDHCI_AUTO_CMD23
))
1264 sdhci_send_command(host
, mrq
->sbc
);
1266 sdhci_send_command(host
, mrq
->cmd
);
1270 spin_unlock_irqrestore(&host
->lock
, flags
);
1273 static void sdhci_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
1275 struct sdhci_host
*host
;
1276 unsigned long flags
;
1279 host
= mmc_priv(mmc
);
1281 spin_lock_irqsave(&host
->lock
, flags
);
1283 if (host
->flags
& SDHCI_DEVICE_DEAD
)
1287 * Reset the chip on each power off.
1288 * Should clear out any weird states.
1290 if (ios
->power_mode
== MMC_POWER_OFF
) {
1291 sdhci_writel(host
, 0, SDHCI_SIGNAL_ENABLE
);
1295 sdhci_set_clock(host
, ios
->clock
);
1297 if (ios
->power_mode
== MMC_POWER_OFF
)
1298 sdhci_set_power(host
, -1);
1300 sdhci_set_power(host
, ios
->vdd
);
1302 if (host
->ops
->platform_send_init_74_clocks
)
1303 host
->ops
->platform_send_init_74_clocks(host
, ios
->power_mode
);
1306 * If your platform has 8-bit width support but is not a v3 controller,
1307 * or if it requires special setup code, you should implement that in
1308 * platform_8bit_width().
1310 if (host
->ops
->platform_8bit_width
)
1311 host
->ops
->platform_8bit_width(host
, ios
->bus_width
);
1313 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
1314 if (ios
->bus_width
== MMC_BUS_WIDTH_8
) {
1315 ctrl
&= ~SDHCI_CTRL_4BITBUS
;
1316 if (host
->version
>= SDHCI_SPEC_300
)
1317 ctrl
|= SDHCI_CTRL_8BITBUS
;
1319 if (host
->version
>= SDHCI_SPEC_300
)
1320 ctrl
&= ~SDHCI_CTRL_8BITBUS
;
1321 if (ios
->bus_width
== MMC_BUS_WIDTH_4
)
1322 ctrl
|= SDHCI_CTRL_4BITBUS
;
1324 ctrl
&= ~SDHCI_CTRL_4BITBUS
;
1326 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
1329 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
1331 if ((ios
->timing
== MMC_TIMING_SD_HS
||
1332 ios
->timing
== MMC_TIMING_MMC_HS
)
1333 && !(host
->quirks
& SDHCI_QUIRK_NO_HISPD_BIT
))
1334 ctrl
|= SDHCI_CTRL_HISPD
;
1336 ctrl
&= ~SDHCI_CTRL_HISPD
;
1338 if (host
->version
>= SDHCI_SPEC_300
) {
1342 /* In case of UHS-I modes, set High Speed Enable */
1343 if ((ios
->timing
== MMC_TIMING_UHS_SDR50
) ||
1344 (ios
->timing
== MMC_TIMING_UHS_SDR104
) ||
1345 (ios
->timing
== MMC_TIMING_UHS_DDR50
) ||
1346 (ios
->timing
== MMC_TIMING_UHS_SDR25
) ||
1347 (ios
->timing
== MMC_TIMING_UHS_SDR12
))
1348 ctrl
|= SDHCI_CTRL_HISPD
;
1350 ctrl_2
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1351 if (!(ctrl_2
& SDHCI_CTRL_PRESET_VAL_ENABLE
)) {
1352 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
1354 * We only need to set Driver Strength if the
1355 * preset value enable is not set.
1357 ctrl_2
&= ~SDHCI_CTRL_DRV_TYPE_MASK
;
1358 if (ios
->drv_type
== MMC_SET_DRIVER_TYPE_A
)
1359 ctrl_2
|= SDHCI_CTRL_DRV_TYPE_A
;
1360 else if (ios
->drv_type
== MMC_SET_DRIVER_TYPE_C
)
1361 ctrl_2
|= SDHCI_CTRL_DRV_TYPE_C
;
1363 sdhci_writew(host
, ctrl_2
, SDHCI_HOST_CONTROL2
);
1366 * According to SDHC Spec v3.00, if the Preset Value
1367 * Enable in the Host Control 2 register is set, we
1368 * need to reset SD Clock Enable before changing High
1369 * Speed Enable to avoid generating clock gliches.
1372 /* Reset SD Clock Enable */
1373 clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
);
1374 clk
&= ~SDHCI_CLOCK_CARD_EN
;
1375 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
1377 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
1379 /* Re-enable SD Clock */
1380 clock
= host
->clock
;
1382 sdhci_set_clock(host
, clock
);
1386 /* Reset SD Clock Enable */
1387 clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
);
1388 clk
&= ~SDHCI_CLOCK_CARD_EN
;
1389 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
1391 if (host
->ops
->set_uhs_signaling
)
1392 host
->ops
->set_uhs_signaling(host
, ios
->timing
);
1394 ctrl_2
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1395 /* Select Bus Speed Mode for host */
1396 ctrl_2
&= ~SDHCI_CTRL_UHS_MASK
;
1397 if (ios
->timing
== MMC_TIMING_UHS_SDR12
)
1398 ctrl_2
|= SDHCI_CTRL_UHS_SDR12
;
1399 else if (ios
->timing
== MMC_TIMING_UHS_SDR25
)
1400 ctrl_2
|= SDHCI_CTRL_UHS_SDR25
;
1401 else if (ios
->timing
== MMC_TIMING_UHS_SDR50
)
1402 ctrl_2
|= SDHCI_CTRL_UHS_SDR50
;
1403 else if (ios
->timing
== MMC_TIMING_UHS_SDR104
)
1404 ctrl_2
|= SDHCI_CTRL_UHS_SDR104
;
1405 else if (ios
->timing
== MMC_TIMING_UHS_DDR50
)
1406 ctrl_2
|= SDHCI_CTRL_UHS_DDR50
;
1407 sdhci_writew(host
, ctrl_2
, SDHCI_HOST_CONTROL2
);
1410 /* Re-enable SD Clock */
1411 clock
= host
->clock
;
1413 sdhci_set_clock(host
, clock
);
1415 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
1418 * Some (ENE) controllers go apeshit on some ios operation,
1419 * signalling timeout and CRC errors even on CMD0. Resetting
1420 * it on each ios seems to solve the problem.
1422 if(host
->quirks
& SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS
)
1423 sdhci_reset(host
, SDHCI_RESET_CMD
| SDHCI_RESET_DATA
);
1427 spin_unlock_irqrestore(&host
->lock
, flags
);
1430 static int check_ro(struct sdhci_host
*host
)
1432 unsigned long flags
;
1435 spin_lock_irqsave(&host
->lock
, flags
);
1437 if (host
->flags
& SDHCI_DEVICE_DEAD
)
1439 else if (host
->ops
->get_ro
)
1440 is_readonly
= host
->ops
->get_ro(host
);
1442 is_readonly
= !(sdhci_readl(host
, SDHCI_PRESENT_STATE
)
1443 & SDHCI_WRITE_PROTECT
);
1445 spin_unlock_irqrestore(&host
->lock
, flags
);
1447 /* This quirk needs to be replaced by a callback-function later */
1448 return host
->quirks
& SDHCI_QUIRK_INVERTED_WRITE_PROTECT
?
1449 !is_readonly
: is_readonly
;
1452 #define SAMPLE_COUNT 5
1454 static int sdhci_get_ro(struct mmc_host
*mmc
)
1456 struct sdhci_host
*host
;
1459 host
= mmc_priv(mmc
);
1461 if (!(host
->quirks
& SDHCI_QUIRK_UNSTABLE_RO_DETECT
))
1462 return check_ro(host
);
1465 for (i
= 0; i
< SAMPLE_COUNT
; i
++) {
1466 if (check_ro(host
)) {
1467 if (++ro_count
> SAMPLE_COUNT
/ 2)
1475 static void sdhci_enable_sdio_irq(struct mmc_host
*mmc
, int enable
)
1477 struct sdhci_host
*host
;
1478 unsigned long flags
;
1480 host
= mmc_priv(mmc
);
1482 spin_lock_irqsave(&host
->lock
, flags
);
1484 if (host
->flags
& SDHCI_DEVICE_DEAD
)
1488 sdhci_unmask_irqs(host
, SDHCI_INT_CARD_INT
);
1490 sdhci_mask_irqs(host
, SDHCI_INT_CARD_INT
);
1494 spin_unlock_irqrestore(&host
->lock
, flags
);
1497 static int sdhci_start_signal_voltage_switch(struct mmc_host
*mmc
,
1498 struct mmc_ios
*ios
)
1500 struct sdhci_host
*host
;
1505 host
= mmc_priv(mmc
);
1508 * Signal Voltage Switching is only applicable for Host Controllers
1511 if (host
->version
< SDHCI_SPEC_300
)
1515 * We first check whether the request is to set signalling voltage
1516 * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
1518 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1519 if (ios
->signal_voltage
== MMC_SIGNAL_VOLTAGE_330
) {
1520 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1521 ctrl
&= ~SDHCI_CTRL_VDD_180
;
1522 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
1525 usleep_range(5000, 5500);
1527 /* 3.3V regulator output should be stable within 5 ms */
1528 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1529 if (!(ctrl
& SDHCI_CTRL_VDD_180
))
1532 printk(KERN_INFO DRIVER_NAME
": Switching to 3.3V "
1533 "signalling voltage failed\n");
1536 } else if (!(ctrl
& SDHCI_CTRL_VDD_180
) &&
1537 (ios
->signal_voltage
== MMC_SIGNAL_VOLTAGE_180
)) {
1539 clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
);
1540 clk
&= ~SDHCI_CLOCK_CARD_EN
;
1541 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
1543 /* Check whether DAT[3:0] is 0000 */
1544 present_state
= sdhci_readl(host
, SDHCI_PRESENT_STATE
);
1545 if (!((present_state
& SDHCI_DATA_LVL_MASK
) >>
1546 SDHCI_DATA_LVL_SHIFT
)) {
1548 * Enable 1.8V Signal Enable in the Host Control2
1551 ctrl
|= SDHCI_CTRL_VDD_180
;
1552 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
1555 usleep_range(5000, 5500);
1557 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1558 if (ctrl
& SDHCI_CTRL_VDD_180
) {
1559 /* Provide SDCLK again and wait for 1ms*/
1560 clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
);
1561 clk
|= SDHCI_CLOCK_CARD_EN
;
1562 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
1563 usleep_range(1000, 1500);
1566 * If DAT[3:0] level is 1111b, then the card
1567 * was successfully switched to 1.8V signaling.
1569 present_state
= sdhci_readl(host
,
1570 SDHCI_PRESENT_STATE
);
1571 if ((present_state
& SDHCI_DATA_LVL_MASK
) ==
1572 SDHCI_DATA_LVL_MASK
)
1578 * If we are here, that means the switch to 1.8V signaling
1579 * failed. We power cycle the card, and retry initialization
1580 * sequence by setting S18R to 0.
1582 pwr
= sdhci_readb(host
, SDHCI_POWER_CONTROL
);
1583 pwr
&= ~SDHCI_POWER_ON
;
1584 sdhci_writeb(host
, pwr
, SDHCI_POWER_CONTROL
);
1586 /* Wait for 1ms as per the spec */
1587 usleep_range(1000, 1500);
1588 pwr
|= SDHCI_POWER_ON
;
1589 sdhci_writeb(host
, pwr
, SDHCI_POWER_CONTROL
);
1591 printk(KERN_INFO DRIVER_NAME
": Switching to 1.8V signalling "
1592 "voltage failed, retrying with S18R set to 0\n");
1595 /* No signal voltage switch required */
1599 static int sdhci_execute_tuning(struct mmc_host
*mmc
)
1601 struct sdhci_host
*host
;
1604 int tuning_loop_counter
= MAX_TUNING_LOOP
;
1605 unsigned long timeout
;
1608 host
= mmc_priv(mmc
);
1610 disable_irq(host
->irq
);
1611 spin_lock(&host
->lock
);
1613 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1616 * Host Controller needs tuning only in case of SDR104 mode
1617 * and for SDR50 mode when Use Tuning for SDR50 is set in
1618 * Capabilities register.
1620 if (((ctrl
& SDHCI_CTRL_UHS_MASK
) == SDHCI_CTRL_UHS_SDR104
) ||
1621 (((ctrl
& SDHCI_CTRL_UHS_MASK
) == SDHCI_CTRL_UHS_SDR50
) &&
1622 (host
->flags
& SDHCI_SDR50_NEEDS_TUNING
)))
1623 ctrl
|= SDHCI_CTRL_EXEC_TUNING
;
1625 spin_unlock(&host
->lock
);
1626 enable_irq(host
->irq
);
1630 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
1633 * As per the Host Controller spec v3.00, tuning command
1634 * generates Buffer Read Ready interrupt, so enable that.
1636 * Note: The spec clearly says that when tuning sequence
1637 * is being performed, the controller does not generate
1638 * interrupts other than Buffer Read Ready interrupt. But
1639 * to make sure we don't hit a controller bug, we _only_
1640 * enable Buffer Read Ready interrupt here.
1642 ier
= sdhci_readl(host
, SDHCI_INT_ENABLE
);
1643 sdhci_clear_set_irqs(host
, ier
, SDHCI_INT_DATA_AVAIL
);
1646 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1647 * of loops reaches 40 times or a timeout of 150ms occurs.
1651 struct mmc_command cmd
= {0};
1652 struct mmc_request mrq
= {0};
1654 if (!tuning_loop_counter
&& !timeout
)
1657 cmd
.opcode
= MMC_SEND_TUNING_BLOCK
;
1659 cmd
.flags
= MMC_RSP_R1
| MMC_CMD_ADTC
;
1668 * In response to CMD19, the card sends 64 bytes of tuning
1669 * block to the Host Controller. So we set the block size
1672 sdhci_writew(host
, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE
);
1675 * The tuning block is sent by the card to the host controller.
1676 * So we set the TRNS_READ bit in the Transfer Mode register.
1677 * This also takes care of setting DMA Enable and Multi Block
1678 * Select in the same register to 0.
1680 sdhci_writew(host
, SDHCI_TRNS_READ
, SDHCI_TRANSFER_MODE
);
1682 sdhci_send_command(host
, &cmd
);
1687 spin_unlock(&host
->lock
);
1688 enable_irq(host
->irq
);
1690 /* Wait for Buffer Read Ready interrupt */
1691 wait_event_interruptible_timeout(host
->buf_ready_int
,
1692 (host
->tuning_done
== 1),
1693 msecs_to_jiffies(50));
1694 disable_irq(host
->irq
);
1695 spin_lock(&host
->lock
);
1697 if (!host
->tuning_done
) {
1698 printk(KERN_INFO DRIVER_NAME
": Timeout waiting for "
1699 "Buffer Read Ready interrupt during tuning "
1700 "procedure, falling back to fixed sampling "
1702 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1703 ctrl
&= ~SDHCI_CTRL_TUNED_CLK
;
1704 ctrl
&= ~SDHCI_CTRL_EXEC_TUNING
;
1705 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
1711 host
->tuning_done
= 0;
1713 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1714 tuning_loop_counter
--;
1717 } while (ctrl
& SDHCI_CTRL_EXEC_TUNING
);
1720 * The Host Driver has exhausted the maximum number of loops allowed,
1721 * so use fixed sampling frequency.
1723 if (!tuning_loop_counter
|| !timeout
) {
1724 ctrl
&= ~SDHCI_CTRL_TUNED_CLK
;
1725 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
1727 if (!(ctrl
& SDHCI_CTRL_TUNED_CLK
)) {
1728 printk(KERN_INFO DRIVER_NAME
": Tuning procedure"
1729 " failed, falling back to fixed sampling"
1737 * If this is the very first time we are here, we start the retuning
1738 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1739 * flag won't be set, we check this condition before actually starting
1742 if (!(host
->flags
& SDHCI_NEEDS_RETUNING
) && host
->tuning_count
&&
1743 (host
->tuning_mode
== SDHCI_TUNING_MODE_1
)) {
1744 mod_timer(&host
->tuning_timer
, jiffies
+
1745 host
->tuning_count
* HZ
);
1746 /* Tuning mode 1 limits the maximum data length to 4MB */
1747 mmc
->max_blk_count
= (4 * 1024 * 1024) / mmc
->max_blk_size
;
1749 host
->flags
&= ~SDHCI_NEEDS_RETUNING
;
1750 /* Reload the new initial value for timer */
1751 if (host
->tuning_mode
== SDHCI_TUNING_MODE_1
)
1752 mod_timer(&host
->tuning_timer
, jiffies
+
1753 host
->tuning_count
* HZ
);
1757 * In case tuning fails, host controllers which support re-tuning can
1758 * try tuning again at a later time, when the re-tuning timer expires.
1759 * So for these controllers, we return 0. Since there might be other
1760 * controllers who do not have this capability, we return error for
1763 if (err
&& host
->tuning_count
&&
1764 host
->tuning_mode
== SDHCI_TUNING_MODE_1
)
1767 sdhci_clear_set_irqs(host
, SDHCI_INT_DATA_AVAIL
, ier
);
1768 spin_unlock(&host
->lock
);
1769 enable_irq(host
->irq
);
1774 static void sdhci_enable_preset_value(struct mmc_host
*mmc
, bool enable
)
1776 struct sdhci_host
*host
;
1778 unsigned long flags
;
1780 host
= mmc_priv(mmc
);
1782 /* Host Controller v3.00 defines preset value registers */
1783 if (host
->version
< SDHCI_SPEC_300
)
1786 spin_lock_irqsave(&host
->lock
, flags
);
1788 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1791 * We only enable or disable Preset Value if they are not already
1792 * enabled or disabled respectively. Otherwise, we bail out.
1794 if (enable
&& !(ctrl
& SDHCI_CTRL_PRESET_VAL_ENABLE
)) {
1795 ctrl
|= SDHCI_CTRL_PRESET_VAL_ENABLE
;
1796 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
1797 } else if (!enable
&& (ctrl
& SDHCI_CTRL_PRESET_VAL_ENABLE
)) {
1798 ctrl
&= ~SDHCI_CTRL_PRESET_VAL_ENABLE
;
1799 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
1802 spin_unlock_irqrestore(&host
->lock
, flags
);
1805 static const struct mmc_host_ops sdhci_ops
= {
1806 .request
= sdhci_request
,
1807 .set_ios
= sdhci_set_ios
,
1808 .get_ro
= sdhci_get_ro
,
1809 .enable_sdio_irq
= sdhci_enable_sdio_irq
,
1810 .start_signal_voltage_switch
= sdhci_start_signal_voltage_switch
,
1811 .execute_tuning
= sdhci_execute_tuning
,
1812 .enable_preset_value
= sdhci_enable_preset_value
,
1815 /*****************************************************************************\
1819 \*****************************************************************************/
1821 static void sdhci_tasklet_card(unsigned long param
)
1823 struct sdhci_host
*host
;
1824 unsigned long flags
;
1826 host
= (struct sdhci_host
*)param
;
1828 spin_lock_irqsave(&host
->lock
, flags
);
1830 if (!(sdhci_readl(host
, SDHCI_PRESENT_STATE
) & SDHCI_CARD_PRESENT
)) {
1832 printk(KERN_ERR
"%s: Card removed during transfer!\n",
1833 mmc_hostname(host
->mmc
));
1834 printk(KERN_ERR
"%s: Resetting controller.\n",
1835 mmc_hostname(host
->mmc
));
1837 sdhci_reset(host
, SDHCI_RESET_CMD
);
1838 sdhci_reset(host
, SDHCI_RESET_DATA
);
1840 host
->mrq
->cmd
->error
= -ENOMEDIUM
;
1841 tasklet_schedule(&host
->finish_tasklet
);
1845 spin_unlock_irqrestore(&host
->lock
, flags
);
1847 mmc_detect_change(host
->mmc
, msecs_to_jiffies(200));
1850 static void sdhci_tasklet_finish(unsigned long param
)
1852 struct sdhci_host
*host
;
1853 unsigned long flags
;
1854 struct mmc_request
*mrq
;
1856 host
= (struct sdhci_host
*)param
;
1859 * If this tasklet gets rescheduled while running, it will
1860 * be run again afterwards but without any active request.
1865 spin_lock_irqsave(&host
->lock
, flags
);
1867 del_timer(&host
->timer
);
1872 * The controller needs a reset of internal state machines
1873 * upon error conditions.
1875 if (!(host
->flags
& SDHCI_DEVICE_DEAD
) &&
1876 ((mrq
->cmd
&& mrq
->cmd
->error
) ||
1877 (mrq
->data
&& (mrq
->data
->error
||
1878 (mrq
->data
->stop
&& mrq
->data
->stop
->error
))) ||
1879 (host
->quirks
& SDHCI_QUIRK_RESET_AFTER_REQUEST
))) {
1881 /* Some controllers need this kick or reset won't work here */
1882 if (host
->quirks
& SDHCI_QUIRK_CLOCK_BEFORE_RESET
) {
1885 /* This is to force an update */
1886 clock
= host
->clock
;
1888 sdhci_set_clock(host
, clock
);
1891 /* Spec says we should do both at the same time, but Ricoh
1892 controllers do not like that. */
1893 sdhci_reset(host
, SDHCI_RESET_CMD
);
1894 sdhci_reset(host
, SDHCI_RESET_DATA
);
1901 #ifndef SDHCI_USE_LEDS_CLASS
1902 sdhci_deactivate_led(host
);
1906 spin_unlock_irqrestore(&host
->lock
, flags
);
1908 mmc_request_done(host
->mmc
, mrq
);
1911 static void sdhci_timeout_timer(unsigned long data
)
1913 struct sdhci_host
*host
;
1914 unsigned long flags
;
1916 host
= (struct sdhci_host
*)data
;
1918 spin_lock_irqsave(&host
->lock
, flags
);
1921 printk(KERN_ERR
"%s: Timeout waiting for hardware "
1922 "interrupt.\n", mmc_hostname(host
->mmc
));
1923 sdhci_dumpregs(host
);
1926 host
->data
->error
= -ETIMEDOUT
;
1927 sdhci_finish_data(host
);
1930 host
->cmd
->error
= -ETIMEDOUT
;
1932 host
->mrq
->cmd
->error
= -ETIMEDOUT
;
1934 tasklet_schedule(&host
->finish_tasklet
);
1939 spin_unlock_irqrestore(&host
->lock
, flags
);
1942 static void sdhci_tuning_timer(unsigned long data
)
1944 struct sdhci_host
*host
;
1945 unsigned long flags
;
1947 host
= (struct sdhci_host
*)data
;
1949 spin_lock_irqsave(&host
->lock
, flags
);
1951 host
->flags
|= SDHCI_NEEDS_RETUNING
;
1953 spin_unlock_irqrestore(&host
->lock
, flags
);
1956 /*****************************************************************************\
1958 * Interrupt handling *
1960 \*****************************************************************************/
1962 static void sdhci_cmd_irq(struct sdhci_host
*host
, u32 intmask
)
1964 BUG_ON(intmask
== 0);
1967 printk(KERN_ERR
"%s: Got command interrupt 0x%08x even "
1968 "though no command operation was in progress.\n",
1969 mmc_hostname(host
->mmc
), (unsigned)intmask
);
1970 sdhci_dumpregs(host
);
1974 if (intmask
& SDHCI_INT_TIMEOUT
)
1975 host
->cmd
->error
= -ETIMEDOUT
;
1976 else if (intmask
& (SDHCI_INT_CRC
| SDHCI_INT_END_BIT
|
1978 host
->cmd
->error
= -EILSEQ
;
1980 if (host
->cmd
->error
) {
1981 tasklet_schedule(&host
->finish_tasklet
);
1986 * The host can send and interrupt when the busy state has
1987 * ended, allowing us to wait without wasting CPU cycles.
1988 * Unfortunately this is overloaded on the "data complete"
1989 * interrupt, so we need to take some care when handling
1992 * Note: The 1.0 specification is a bit ambiguous about this
1993 * feature so there might be some problems with older
1996 if (host
->cmd
->flags
& MMC_RSP_BUSY
) {
1997 if (host
->cmd
->data
)
1998 DBG("Cannot wait for busy signal when also "
1999 "doing a data transfer");
2000 else if (!(host
->quirks
& SDHCI_QUIRK_NO_BUSY_IRQ
))
2003 /* The controller does not support the end-of-busy IRQ,
2004 * fall through and take the SDHCI_INT_RESPONSE */
2007 if (intmask
& SDHCI_INT_RESPONSE
)
2008 sdhci_finish_command(host
);
2011 #ifdef CONFIG_MMC_DEBUG
2012 static void sdhci_show_adma_error(struct sdhci_host
*host
)
2014 const char *name
= mmc_hostname(host
->mmc
);
2015 u8
*desc
= host
->adma_desc
;
2020 sdhci_dumpregs(host
);
2023 dma
= (__le32
*)(desc
+ 4);
2024 len
= (__le16
*)(desc
+ 2);
2027 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2028 name
, desc
, le32_to_cpu(*dma
), le16_to_cpu(*len
), attr
);
2037 static void sdhci_show_adma_error(struct sdhci_host
*host
) { }
2040 static void sdhci_data_irq(struct sdhci_host
*host
, u32 intmask
)
2042 BUG_ON(intmask
== 0);
2044 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2045 if (intmask
& SDHCI_INT_DATA_AVAIL
) {
2046 if (SDHCI_GET_CMD(sdhci_readw(host
, SDHCI_COMMAND
)) ==
2047 MMC_SEND_TUNING_BLOCK
) {
2048 host
->tuning_done
= 1;
2049 wake_up(&host
->buf_ready_int
);
2056 * The "data complete" interrupt is also used to
2057 * indicate that a busy state has ended. See comment
2058 * above in sdhci_cmd_irq().
2060 if (host
->cmd
&& (host
->cmd
->flags
& MMC_RSP_BUSY
)) {
2061 if (intmask
& SDHCI_INT_DATA_END
) {
2062 sdhci_finish_command(host
);
2067 printk(KERN_ERR
"%s: Got data interrupt 0x%08x even "
2068 "though no data operation was in progress.\n",
2069 mmc_hostname(host
->mmc
), (unsigned)intmask
);
2070 sdhci_dumpregs(host
);
2075 if (intmask
& SDHCI_INT_DATA_TIMEOUT
)
2076 host
->data
->error
= -ETIMEDOUT
;
2077 else if (intmask
& SDHCI_INT_DATA_END_BIT
)
2078 host
->data
->error
= -EILSEQ
;
2079 else if ((intmask
& SDHCI_INT_DATA_CRC
) &&
2080 SDHCI_GET_CMD(sdhci_readw(host
, SDHCI_COMMAND
))
2082 host
->data
->error
= -EILSEQ
;
2083 else if (intmask
& SDHCI_INT_ADMA_ERROR
) {
2084 printk(KERN_ERR
"%s: ADMA error\n", mmc_hostname(host
->mmc
));
2085 sdhci_show_adma_error(host
);
2086 host
->data
->error
= -EIO
;
2089 if (host
->data
->error
)
2090 sdhci_finish_data(host
);
2092 if (intmask
& (SDHCI_INT_DATA_AVAIL
| SDHCI_INT_SPACE_AVAIL
))
2093 sdhci_transfer_pio(host
);
2096 * We currently don't do anything fancy with DMA
2097 * boundaries, but as we can't disable the feature
2098 * we need to at least restart the transfer.
2100 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2101 * should return a valid address to continue from, but as
2102 * some controllers are faulty, don't trust them.
2104 if (intmask
& SDHCI_INT_DMA_END
) {
2105 u32 dmastart
, dmanow
;
2106 dmastart
= sg_dma_address(host
->data
->sg
);
2107 dmanow
= dmastart
+ host
->data
->bytes_xfered
;
2109 * Force update to the next DMA block boundary.
2112 ~(SDHCI_DEFAULT_BOUNDARY_SIZE
- 1)) +
2113 SDHCI_DEFAULT_BOUNDARY_SIZE
;
2114 host
->data
->bytes_xfered
= dmanow
- dmastart
;
2115 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2117 mmc_hostname(host
->mmc
), dmastart
,
2118 host
->data
->bytes_xfered
, dmanow
);
2119 sdhci_writel(host
, dmanow
, SDHCI_DMA_ADDRESS
);
2122 if (intmask
& SDHCI_INT_DATA_END
) {
2125 * Data managed to finish before the
2126 * command completed. Make sure we do
2127 * things in the proper order.
2129 host
->data_early
= 1;
2131 sdhci_finish_data(host
);
2137 static irqreturn_t
sdhci_irq(int irq
, void *dev_id
)
2140 struct sdhci_host
* host
= dev_id
;
2144 spin_lock(&host
->lock
);
2146 intmask
= sdhci_readl(host
, SDHCI_INT_STATUS
);
2148 if (!intmask
|| intmask
== 0xffffffff) {
2153 DBG("*** %s got interrupt: 0x%08x\n",
2154 mmc_hostname(host
->mmc
), intmask
);
2156 if (intmask
& (SDHCI_INT_CARD_INSERT
| SDHCI_INT_CARD_REMOVE
)) {
2157 u32 present
= sdhci_readl(host
, SDHCI_PRESENT_STATE
) &
2161 * There is a observation on i.mx esdhc. INSERT bit will be
2162 * immediately set again when it gets cleared, if a card is
2163 * inserted. We have to mask the irq to prevent interrupt
2164 * storm which will freeze the system. And the REMOVE gets
2165 * the same situation.
2167 * More testing are needed here to ensure it works for other
2170 sdhci_mask_irqs(host
, present
? SDHCI_INT_CARD_INSERT
:
2171 SDHCI_INT_CARD_REMOVE
);
2172 sdhci_unmask_irqs(host
, present
? SDHCI_INT_CARD_REMOVE
:
2173 SDHCI_INT_CARD_INSERT
);
2175 sdhci_writel(host
, intmask
& (SDHCI_INT_CARD_INSERT
|
2176 SDHCI_INT_CARD_REMOVE
), SDHCI_INT_STATUS
);
2177 intmask
&= ~(SDHCI_INT_CARD_INSERT
| SDHCI_INT_CARD_REMOVE
);
2178 tasklet_schedule(&host
->card_tasklet
);
2181 if (intmask
& SDHCI_INT_CMD_MASK
) {
2182 sdhci_writel(host
, intmask
& SDHCI_INT_CMD_MASK
,
2184 sdhci_cmd_irq(host
, intmask
& SDHCI_INT_CMD_MASK
);
2187 if (intmask
& SDHCI_INT_DATA_MASK
) {
2188 sdhci_writel(host
, intmask
& SDHCI_INT_DATA_MASK
,
2190 sdhci_data_irq(host
, intmask
& SDHCI_INT_DATA_MASK
);
2193 intmask
&= ~(SDHCI_INT_CMD_MASK
| SDHCI_INT_DATA_MASK
);
2195 intmask
&= ~SDHCI_INT_ERROR
;
2197 if (intmask
& SDHCI_INT_BUS_POWER
) {
2198 printk(KERN_ERR
"%s: Card is consuming too much power!\n",
2199 mmc_hostname(host
->mmc
));
2200 sdhci_writel(host
, SDHCI_INT_BUS_POWER
, SDHCI_INT_STATUS
);
2203 intmask
&= ~SDHCI_INT_BUS_POWER
;
2205 if (intmask
& SDHCI_INT_CARD_INT
)
2208 intmask
&= ~SDHCI_INT_CARD_INT
;
2211 printk(KERN_ERR
"%s: Unexpected interrupt 0x%08x.\n",
2212 mmc_hostname(host
->mmc
), intmask
);
2213 sdhci_dumpregs(host
);
2215 sdhci_writel(host
, intmask
, SDHCI_INT_STATUS
);
2218 result
= IRQ_HANDLED
;
2222 spin_unlock(&host
->lock
);
2225 * We have to delay this as it calls back into the driver.
2228 mmc_signal_sdio_irq(host
->mmc
);
2233 /*****************************************************************************\
2237 \*****************************************************************************/
2241 int sdhci_suspend_host(struct sdhci_host
*host
, pm_message_t state
)
2245 sdhci_disable_card_detection(host
);
2247 /* Disable tuning since we are suspending */
2248 if (host
->version
>= SDHCI_SPEC_300
&& host
->tuning_count
&&
2249 host
->tuning_mode
== SDHCI_TUNING_MODE_1
) {
2250 host
->flags
&= ~SDHCI_NEEDS_RETUNING
;
2251 mod_timer(&host
->tuning_timer
, jiffies
+
2252 host
->tuning_count
* HZ
);
2255 ret
= mmc_suspend_host(host
->mmc
);
2259 free_irq(host
->irq
, host
);
2262 ret
= regulator_disable(host
->vmmc
);
2267 EXPORT_SYMBOL_GPL(sdhci_suspend_host
);
2269 int sdhci_resume_host(struct sdhci_host
*host
)
2274 int ret
= regulator_enable(host
->vmmc
);
2280 if (host
->flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
)) {
2281 if (host
->ops
->enable_dma
)
2282 host
->ops
->enable_dma(host
);
2285 ret
= request_irq(host
->irq
, sdhci_irq
, IRQF_SHARED
,
2286 mmc_hostname(host
->mmc
), host
);
2290 sdhci_init(host
, (host
->mmc
->pm_flags
& MMC_PM_KEEP_POWER
));
2293 ret
= mmc_resume_host(host
->mmc
);
2294 sdhci_enable_card_detection(host
);
2296 /* Set the re-tuning expiration flag */
2297 if ((host
->version
>= SDHCI_SPEC_300
) && host
->tuning_count
&&
2298 (host
->tuning_mode
== SDHCI_TUNING_MODE_1
))
2299 host
->flags
|= SDHCI_NEEDS_RETUNING
;
2304 EXPORT_SYMBOL_GPL(sdhci_resume_host
);
2306 void sdhci_enable_irq_wakeups(struct sdhci_host
*host
)
2309 val
= sdhci_readb(host
, SDHCI_WAKE_UP_CONTROL
);
2310 val
|= SDHCI_WAKE_ON_INT
;
2311 sdhci_writeb(host
, val
, SDHCI_WAKE_UP_CONTROL
);
2314 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups
);
2316 #endif /* CONFIG_PM */
2318 /*****************************************************************************\
2320 * Device allocation/registration *
2322 \*****************************************************************************/
2324 struct sdhci_host
*sdhci_alloc_host(struct device
*dev
,
2327 struct mmc_host
*mmc
;
2328 struct sdhci_host
*host
;
2330 WARN_ON(dev
== NULL
);
2332 mmc
= mmc_alloc_host(sizeof(struct sdhci_host
) + priv_size
, dev
);
2334 return ERR_PTR(-ENOMEM
);
2336 host
= mmc_priv(mmc
);
2342 EXPORT_SYMBOL_GPL(sdhci_alloc_host
);
2344 int sdhci_add_host(struct sdhci_host
*host
)
2346 struct mmc_host
*mmc
;
2348 u32 max_current_caps
;
2349 unsigned int ocr_avail
;
2352 WARN_ON(host
== NULL
);
2359 host
->quirks
= debug_quirks
;
2361 sdhci_reset(host
, SDHCI_RESET_ALL
);
2363 host
->version
= sdhci_readw(host
, SDHCI_HOST_VERSION
);
2364 host
->version
= (host
->version
& SDHCI_SPEC_VER_MASK
)
2365 >> SDHCI_SPEC_VER_SHIFT
;
2366 if (host
->version
> SDHCI_SPEC_300
) {
2367 printk(KERN_ERR
"%s: Unknown controller version (%d). "
2368 "You may experience problems.\n", mmc_hostname(mmc
),
2372 caps
[0] = (host
->quirks
& SDHCI_QUIRK_MISSING_CAPS
) ? host
->caps
:
2373 sdhci_readl(host
, SDHCI_CAPABILITIES
);
2375 caps
[1] = (host
->version
>= SDHCI_SPEC_300
) ?
2376 sdhci_readl(host
, SDHCI_CAPABILITIES_1
) : 0;
2378 if (host
->quirks
& SDHCI_QUIRK_FORCE_DMA
)
2379 host
->flags
|= SDHCI_USE_SDMA
;
2380 else if (!(caps
[0] & SDHCI_CAN_DO_SDMA
))
2381 DBG("Controller doesn't have SDMA capability\n");
2383 host
->flags
|= SDHCI_USE_SDMA
;
2385 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_DMA
) &&
2386 (host
->flags
& SDHCI_USE_SDMA
)) {
2387 DBG("Disabling DMA as it is marked broken\n");
2388 host
->flags
&= ~SDHCI_USE_SDMA
;
2391 if ((host
->version
>= SDHCI_SPEC_200
) &&
2392 (caps
[0] & SDHCI_CAN_DO_ADMA2
))
2393 host
->flags
|= SDHCI_USE_ADMA
;
2395 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_ADMA
) &&
2396 (host
->flags
& SDHCI_USE_ADMA
)) {
2397 DBG("Disabling ADMA as it is marked broken\n");
2398 host
->flags
&= ~SDHCI_USE_ADMA
;
2401 if (host
->flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
)) {
2402 if (host
->ops
->enable_dma
) {
2403 if (host
->ops
->enable_dma(host
)) {
2404 printk(KERN_WARNING
"%s: No suitable DMA "
2405 "available. Falling back to PIO.\n",
2408 ~(SDHCI_USE_SDMA
| SDHCI_USE_ADMA
);
2413 if (host
->flags
& SDHCI_USE_ADMA
) {
2415 * We need to allocate descriptors for all sg entries
2416 * (128) and potentially one alignment transfer for
2417 * each of those entries.
2419 host
->adma_desc
= kmalloc((128 * 2 + 1) * 4, GFP_KERNEL
);
2420 host
->align_buffer
= kmalloc(128 * 4, GFP_KERNEL
);
2421 if (!host
->adma_desc
|| !host
->align_buffer
) {
2422 kfree(host
->adma_desc
);
2423 kfree(host
->align_buffer
);
2424 printk(KERN_WARNING
"%s: Unable to allocate ADMA "
2425 "buffers. Falling back to standard DMA.\n",
2427 host
->flags
&= ~SDHCI_USE_ADMA
;
2432 * If we use DMA, then it's up to the caller to set the DMA
2433 * mask, but PIO does not need the hw shim so we set a new
2434 * mask here in that case.
2436 if (!(host
->flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
))) {
2437 host
->dma_mask
= DMA_BIT_MASK(64);
2438 mmc_dev(host
->mmc
)->dma_mask
= &host
->dma_mask
;
2441 if (host
->version
>= SDHCI_SPEC_300
)
2442 host
->max_clk
= (caps
[0] & SDHCI_CLOCK_V3_BASE_MASK
)
2443 >> SDHCI_CLOCK_BASE_SHIFT
;
2445 host
->max_clk
= (caps
[0] & SDHCI_CLOCK_BASE_MASK
)
2446 >> SDHCI_CLOCK_BASE_SHIFT
;
2448 host
->max_clk
*= 1000000;
2449 if (host
->max_clk
== 0 || host
->quirks
&
2450 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN
) {
2451 if (!host
->ops
->get_max_clock
) {
2453 "%s: Hardware doesn't specify base clock "
2454 "frequency.\n", mmc_hostname(mmc
));
2457 host
->max_clk
= host
->ops
->get_max_clock(host
);
2461 * In case of Host Controller v3.00, find out whether clock
2462 * multiplier is supported.
2464 host
->clk_mul
= (caps
[1] & SDHCI_CLOCK_MUL_MASK
) >>
2465 SDHCI_CLOCK_MUL_SHIFT
;
2468 * In case the value in Clock Multiplier is 0, then programmable
2469 * clock mode is not supported, otherwise the actual clock
2470 * multiplier is one more than the value of Clock Multiplier
2471 * in the Capabilities Register.
2477 * Set host parameters.
2479 mmc
->ops
= &sdhci_ops
;
2480 mmc
->f_max
= host
->max_clk
;
2481 if (host
->ops
->get_min_clock
)
2482 mmc
->f_min
= host
->ops
->get_min_clock(host
);
2483 else if (host
->version
>= SDHCI_SPEC_300
) {
2484 if (host
->clk_mul
) {
2485 mmc
->f_min
= (host
->max_clk
* host
->clk_mul
) / 1024;
2486 mmc
->f_max
= host
->max_clk
* host
->clk_mul
;
2488 mmc
->f_min
= host
->max_clk
/ SDHCI_MAX_DIV_SPEC_300
;
2490 mmc
->f_min
= host
->max_clk
/ SDHCI_MAX_DIV_SPEC_200
;
2493 (caps
[0] & SDHCI_TIMEOUT_CLK_MASK
) >> SDHCI_TIMEOUT_CLK_SHIFT
;
2494 if (host
->timeout_clk
== 0) {
2495 if (host
->ops
->get_timeout_clock
) {
2496 host
->timeout_clk
= host
->ops
->get_timeout_clock(host
);
2497 } else if (!(host
->quirks
&
2498 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
)) {
2500 "%s: Hardware doesn't specify timeout clock "
2501 "frequency.\n", mmc_hostname(mmc
));
2505 if (caps
[0] & SDHCI_TIMEOUT_CLK_UNIT
)
2506 host
->timeout_clk
*= 1000;
2508 if (host
->quirks
& SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
)
2509 host
->timeout_clk
= mmc
->f_max
/ 1000;
2511 mmc
->max_discard_to
= (1 << 27) / host
->timeout_clk
;
2513 mmc
->caps
|= MMC_CAP_SDIO_IRQ
| MMC_CAP_ERASE
| MMC_CAP_CMD23
;
2515 if (host
->quirks
& SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12
)
2516 host
->flags
|= SDHCI_AUTO_CMD12
;
2518 /* Auto-CMD23 stuff only works in ADMA or PIO. */
2519 if ((host
->version
>= SDHCI_SPEC_300
) &&
2520 ((host
->flags
& SDHCI_USE_ADMA
) ||
2521 !(host
->flags
& SDHCI_USE_SDMA
))) {
2522 host
->flags
|= SDHCI_AUTO_CMD23
;
2523 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc
));
2525 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc
));
2529 * A controller may support 8-bit width, but the board itself
2530 * might not have the pins brought out. Boards that support
2531 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2532 * their platform code before calling sdhci_add_host(), and we
2533 * won't assume 8-bit width for hosts without that CAP.
2535 if (!(host
->quirks
& SDHCI_QUIRK_FORCE_1_BIT_DATA
))
2536 mmc
->caps
|= MMC_CAP_4_BIT_DATA
;
2538 if (caps
[0] & SDHCI_CAN_DO_HISPD
)
2539 mmc
->caps
|= MMC_CAP_SD_HIGHSPEED
| MMC_CAP_MMC_HIGHSPEED
;
2541 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_CARD_DETECTION
) &&
2542 mmc_card_is_removable(mmc
))
2543 mmc
->caps
|= MMC_CAP_NEEDS_POLL
;
2545 /* UHS-I mode(s) supported by the host controller. */
2546 if (host
->version
>= SDHCI_SPEC_300
)
2547 mmc
->caps
|= MMC_CAP_UHS_SDR12
| MMC_CAP_UHS_SDR25
;
2549 /* SDR104 supports also implies SDR50 support */
2550 if (caps
[1] & SDHCI_SUPPORT_SDR104
)
2551 mmc
->caps
|= MMC_CAP_UHS_SDR104
| MMC_CAP_UHS_SDR50
;
2552 else if (caps
[1] & SDHCI_SUPPORT_SDR50
)
2553 mmc
->caps
|= MMC_CAP_UHS_SDR50
;
2555 if (caps
[1] & SDHCI_SUPPORT_DDR50
)
2556 mmc
->caps
|= MMC_CAP_UHS_DDR50
;
2558 /* Does the host needs tuning for SDR50? */
2559 if (caps
[1] & SDHCI_USE_SDR50_TUNING
)
2560 host
->flags
|= SDHCI_SDR50_NEEDS_TUNING
;
2562 /* Driver Type(s) (A, C, D) supported by the host */
2563 if (caps
[1] & SDHCI_DRIVER_TYPE_A
)
2564 mmc
->caps
|= MMC_CAP_DRIVER_TYPE_A
;
2565 if (caps
[1] & SDHCI_DRIVER_TYPE_C
)
2566 mmc
->caps
|= MMC_CAP_DRIVER_TYPE_C
;
2567 if (caps
[1] & SDHCI_DRIVER_TYPE_D
)
2568 mmc
->caps
|= MMC_CAP_DRIVER_TYPE_D
;
2570 /* Initial value for re-tuning timer count */
2571 host
->tuning_count
= (caps
[1] & SDHCI_RETUNING_TIMER_COUNT_MASK
) >>
2572 SDHCI_RETUNING_TIMER_COUNT_SHIFT
;
2575 * In case Re-tuning Timer is not disabled, the actual value of
2576 * re-tuning timer will be 2 ^ (n - 1).
2578 if (host
->tuning_count
)
2579 host
->tuning_count
= 1 << (host
->tuning_count
- 1);
2581 /* Re-tuning mode supported by the Host Controller */
2582 host
->tuning_mode
= (caps
[1] & SDHCI_RETUNING_MODE_MASK
) >>
2583 SDHCI_RETUNING_MODE_SHIFT
;
2587 * According to SD Host Controller spec v3.00, if the Host System
2588 * can afford more than 150mA, Host Driver should set XPC to 1. Also
2589 * the value is meaningful only if Voltage Support in the Capabilities
2590 * register is set. The actual current value is 4 times the register
2593 max_current_caps
= sdhci_readl(host
, SDHCI_MAX_CURRENT
);
2595 if (caps
[0] & SDHCI_CAN_VDD_330
) {
2596 int max_current_330
;
2598 ocr_avail
|= MMC_VDD_32_33
| MMC_VDD_33_34
;
2600 max_current_330
= ((max_current_caps
&
2601 SDHCI_MAX_CURRENT_330_MASK
) >>
2602 SDHCI_MAX_CURRENT_330_SHIFT
) *
2603 SDHCI_MAX_CURRENT_MULTIPLIER
;
2605 if (max_current_330
> 150)
2606 mmc
->caps
|= MMC_CAP_SET_XPC_330
;
2608 if (caps
[0] & SDHCI_CAN_VDD_300
) {
2609 int max_current_300
;
2611 ocr_avail
|= MMC_VDD_29_30
| MMC_VDD_30_31
;
2613 max_current_300
= ((max_current_caps
&
2614 SDHCI_MAX_CURRENT_300_MASK
) >>
2615 SDHCI_MAX_CURRENT_300_SHIFT
) *
2616 SDHCI_MAX_CURRENT_MULTIPLIER
;
2618 if (max_current_300
> 150)
2619 mmc
->caps
|= MMC_CAP_SET_XPC_300
;
2621 if (caps
[0] & SDHCI_CAN_VDD_180
) {
2622 int max_current_180
;
2624 ocr_avail
|= MMC_VDD_165_195
;
2626 max_current_180
= ((max_current_caps
&
2627 SDHCI_MAX_CURRENT_180_MASK
) >>
2628 SDHCI_MAX_CURRENT_180_SHIFT
) *
2629 SDHCI_MAX_CURRENT_MULTIPLIER
;
2631 if (max_current_180
> 150)
2632 mmc
->caps
|= MMC_CAP_SET_XPC_180
;
2634 /* Maximum current capabilities of the host at 1.8V */
2635 if (max_current_180
>= 800)
2636 mmc
->caps
|= MMC_CAP_MAX_CURRENT_800
;
2637 else if (max_current_180
>= 600)
2638 mmc
->caps
|= MMC_CAP_MAX_CURRENT_600
;
2639 else if (max_current_180
>= 400)
2640 mmc
->caps
|= MMC_CAP_MAX_CURRENT_400
;
2642 mmc
->caps
|= MMC_CAP_MAX_CURRENT_200
;
2645 mmc
->ocr_avail
= ocr_avail
;
2646 mmc
->ocr_avail_sdio
= ocr_avail
;
2647 if (host
->ocr_avail_sdio
)
2648 mmc
->ocr_avail_sdio
&= host
->ocr_avail_sdio
;
2649 mmc
->ocr_avail_sd
= ocr_avail
;
2650 if (host
->ocr_avail_sd
)
2651 mmc
->ocr_avail_sd
&= host
->ocr_avail_sd
;
2652 else /* normal SD controllers don't support 1.8V */
2653 mmc
->ocr_avail_sd
&= ~MMC_VDD_165_195
;
2654 mmc
->ocr_avail_mmc
= ocr_avail
;
2655 if (host
->ocr_avail_mmc
)
2656 mmc
->ocr_avail_mmc
&= host
->ocr_avail_mmc
;
2658 if (mmc
->ocr_avail
== 0) {
2659 printk(KERN_ERR
"%s: Hardware doesn't report any "
2660 "support voltages.\n", mmc_hostname(mmc
));
2664 spin_lock_init(&host
->lock
);
2667 * Maximum number of segments. Depends on if the hardware
2668 * can do scatter/gather or not.
2670 if (host
->flags
& SDHCI_USE_ADMA
)
2671 mmc
->max_segs
= 128;
2672 else if (host
->flags
& SDHCI_USE_SDMA
)
2675 mmc
->max_segs
= 128;
2678 * Maximum number of sectors in one transfer. Limited by DMA boundary
2681 mmc
->max_req_size
= 524288;
2684 * Maximum segment size. Could be one segment with the maximum number
2685 * of bytes. When doing hardware scatter/gather, each entry cannot
2686 * be larger than 64 KiB though.
2688 if (host
->flags
& SDHCI_USE_ADMA
) {
2689 if (host
->quirks
& SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
)
2690 mmc
->max_seg_size
= 65535;
2692 mmc
->max_seg_size
= 65536;
2694 mmc
->max_seg_size
= mmc
->max_req_size
;
2698 * Maximum block size. This varies from controller to controller and
2699 * is specified in the capabilities register.
2701 if (host
->quirks
& SDHCI_QUIRK_FORCE_BLK_SZ_2048
) {
2702 mmc
->max_blk_size
= 2;
2704 mmc
->max_blk_size
= (caps
[0] & SDHCI_MAX_BLOCK_MASK
) >>
2705 SDHCI_MAX_BLOCK_SHIFT
;
2706 if (mmc
->max_blk_size
>= 3) {
2707 printk(KERN_WARNING
"%s: Invalid maximum block size, "
2708 "assuming 512 bytes\n", mmc_hostname(mmc
));
2709 mmc
->max_blk_size
= 0;
2713 mmc
->max_blk_size
= 512 << mmc
->max_blk_size
;
2716 * Maximum block count.
2718 mmc
->max_blk_count
= (host
->quirks
& SDHCI_QUIRK_NO_MULTIBLOCK
) ? 1 : 65535;
2723 tasklet_init(&host
->card_tasklet
,
2724 sdhci_tasklet_card
, (unsigned long)host
);
2725 tasklet_init(&host
->finish_tasklet
,
2726 sdhci_tasklet_finish
, (unsigned long)host
);
2728 setup_timer(&host
->timer
, sdhci_timeout_timer
, (unsigned long)host
);
2730 if (host
->version
>= SDHCI_SPEC_300
) {
2731 init_waitqueue_head(&host
->buf_ready_int
);
2733 /* Initialize re-tuning timer */
2734 init_timer(&host
->tuning_timer
);
2735 host
->tuning_timer
.data
= (unsigned long)host
;
2736 host
->tuning_timer
.function
= sdhci_tuning_timer
;
2739 ret
= request_irq(host
->irq
, sdhci_irq
, IRQF_SHARED
,
2740 mmc_hostname(mmc
), host
);
2744 host
->vmmc
= regulator_get(mmc_dev(mmc
), "vmmc");
2745 if (IS_ERR(host
->vmmc
)) {
2746 printk(KERN_INFO
"%s: no vmmc regulator found\n", mmc_hostname(mmc
));
2749 regulator_enable(host
->vmmc
);
2752 sdhci_init(host
, 0);
2754 #ifdef CONFIG_MMC_DEBUG
2755 sdhci_dumpregs(host
);
2758 #ifdef SDHCI_USE_LEDS_CLASS
2759 snprintf(host
->led_name
, sizeof(host
->led_name
),
2760 "%s::", mmc_hostname(mmc
));
2761 host
->led
.name
= host
->led_name
;
2762 host
->led
.brightness
= LED_OFF
;
2763 host
->led
.default_trigger
= mmc_hostname(mmc
);
2764 host
->led
.brightness_set
= sdhci_led_control
;
2766 ret
= led_classdev_register(mmc_dev(mmc
), &host
->led
);
2775 printk(KERN_INFO
"%s: SDHCI controller on %s [%s] using %s\n",
2776 mmc_hostname(mmc
), host
->hw_name
, dev_name(mmc_dev(mmc
)),
2777 (host
->flags
& SDHCI_USE_ADMA
) ? "ADMA" :
2778 (host
->flags
& SDHCI_USE_SDMA
) ? "DMA" : "PIO");
2780 sdhci_enable_card_detection(host
);
2784 #ifdef SDHCI_USE_LEDS_CLASS
2786 sdhci_reset(host
, SDHCI_RESET_ALL
);
2787 free_irq(host
->irq
, host
);
2790 tasklet_kill(&host
->card_tasklet
);
2791 tasklet_kill(&host
->finish_tasklet
);
2796 EXPORT_SYMBOL_GPL(sdhci_add_host
);
2798 void sdhci_remove_host(struct sdhci_host
*host
, int dead
)
2800 unsigned long flags
;
2803 spin_lock_irqsave(&host
->lock
, flags
);
2805 host
->flags
|= SDHCI_DEVICE_DEAD
;
2808 printk(KERN_ERR
"%s: Controller removed during "
2809 " transfer!\n", mmc_hostname(host
->mmc
));
2811 host
->mrq
->cmd
->error
= -ENOMEDIUM
;
2812 tasklet_schedule(&host
->finish_tasklet
);
2815 spin_unlock_irqrestore(&host
->lock
, flags
);
2818 sdhci_disable_card_detection(host
);
2820 mmc_remove_host(host
->mmc
);
2822 #ifdef SDHCI_USE_LEDS_CLASS
2823 led_classdev_unregister(&host
->led
);
2827 sdhci_reset(host
, SDHCI_RESET_ALL
);
2829 free_irq(host
->irq
, host
);
2831 del_timer_sync(&host
->timer
);
2832 if (host
->version
>= SDHCI_SPEC_300
)
2833 del_timer_sync(&host
->tuning_timer
);
2835 tasklet_kill(&host
->card_tasklet
);
2836 tasklet_kill(&host
->finish_tasklet
);
2839 regulator_disable(host
->vmmc
);
2840 regulator_put(host
->vmmc
);
2843 kfree(host
->adma_desc
);
2844 kfree(host
->align_buffer
);
2846 host
->adma_desc
= NULL
;
2847 host
->align_buffer
= NULL
;
2850 EXPORT_SYMBOL_GPL(sdhci_remove_host
);
2852 void sdhci_free_host(struct sdhci_host
*host
)
2854 mmc_free_host(host
->mmc
);
2857 EXPORT_SYMBOL_GPL(sdhci_free_host
);
2859 /*****************************************************************************\
2861 * Driver init/exit *
2863 \*****************************************************************************/
2865 static int __init
sdhci_drv_init(void)
2867 printk(KERN_INFO DRIVER_NAME
2868 ": Secure Digital Host Controller Interface driver\n");
2869 printk(KERN_INFO DRIVER_NAME
": Copyright(c) Pierre Ossman\n");
2874 static void __exit
sdhci_drv_exit(void)
2878 module_init(sdhci_drv_init
);
2879 module_exit(sdhci_drv_exit
);
2881 module_param(debug_quirks
, uint
, 0444);
2883 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
2884 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
2885 MODULE_LICENSE("GPL");
2887 MODULE_PARM_DESC(debug_quirks
, "Force certain quirks.");