2 * Designware SPI core controller driver (refer pxa2xx_spi.c)
4 * Copyright (c) 2009, Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 #include <linux/dma-mapping.h>
21 #include <linux/interrupt.h>
22 #include <linux/module.h>
23 #include <linux/highmem.h>
24 #include <linux/delay.h>
25 #include <linux/slab.h>
26 #include <linux/spi/spi.h>
30 #ifdef CONFIG_DEBUG_FS
31 #include <linux/debugfs.h>
34 #define START_STATE ((void *)0)
35 #define RUNNING_STATE ((void *)1)
36 #define DONE_STATE ((void *)2)
37 #define ERROR_STATE ((void *)-1)
39 #define QUEUE_RUNNING 0
40 #define QUEUE_STOPPED 1
42 #define MRST_SPI_DEASSERT 0
43 #define MRST_SPI_ASSERT 1
45 /* Slave spi_dev related */
48 u8 cs
; /* chip select pin */
49 u8 n_bytes
; /* current is a 1/2/4 byte op */
50 u8 tmode
; /* TR/TO/RO/EEPROM */
51 u8 type
; /* SPI/SSP/MicroWire */
53 u8 poll_mode
; /* 1 means use poll mode */
60 u16 clk_div
; /* baud rate divider */
61 u32 speed_hz
; /* baud rate */
62 void (*cs_control
)(u32 command
);
65 #ifdef CONFIG_DEBUG_FS
66 static int spi_show_regs_open(struct inode
*inode
, struct file
*file
)
68 file
->private_data
= inode
->i_private
;
72 #define SPI_REGS_BUFSIZE 1024
73 static ssize_t
spi_show_regs(struct file
*file
, char __user
*user_buf
,
74 size_t count
, loff_t
*ppos
)
81 dws
= file
->private_data
;
83 buf
= kzalloc(SPI_REGS_BUFSIZE
, GFP_KERNEL
);
87 len
+= snprintf(buf
+ len
, SPI_REGS_BUFSIZE
- len
,
88 "MRST SPI0 registers:\n");
89 len
+= snprintf(buf
+ len
, SPI_REGS_BUFSIZE
- len
,
90 "=================================\n");
91 len
+= snprintf(buf
+ len
, SPI_REGS_BUFSIZE
- len
,
92 "CTRL0: \t\t0x%08x\n", dw_readl(dws
, ctrl0
));
93 len
+= snprintf(buf
+ len
, SPI_REGS_BUFSIZE
- len
,
94 "CTRL1: \t\t0x%08x\n", dw_readl(dws
, ctrl1
));
95 len
+= snprintf(buf
+ len
, SPI_REGS_BUFSIZE
- len
,
96 "SSIENR: \t0x%08x\n", dw_readl(dws
, ssienr
));
97 len
+= snprintf(buf
+ len
, SPI_REGS_BUFSIZE
- len
,
98 "SER: \t\t0x%08x\n", dw_readl(dws
, ser
));
99 len
+= snprintf(buf
+ len
, SPI_REGS_BUFSIZE
- len
,
100 "BAUDR: \t\t0x%08x\n", dw_readl(dws
, baudr
));
101 len
+= snprintf(buf
+ len
, SPI_REGS_BUFSIZE
- len
,
102 "TXFTLR: \t0x%08x\n", dw_readl(dws
, txfltr
));
103 len
+= snprintf(buf
+ len
, SPI_REGS_BUFSIZE
- len
,
104 "RXFTLR: \t0x%08x\n", dw_readl(dws
, rxfltr
));
105 len
+= snprintf(buf
+ len
, SPI_REGS_BUFSIZE
- len
,
106 "TXFLR: \t\t0x%08x\n", dw_readl(dws
, txflr
));
107 len
+= snprintf(buf
+ len
, SPI_REGS_BUFSIZE
- len
,
108 "RXFLR: \t\t0x%08x\n", dw_readl(dws
, rxflr
));
109 len
+= snprintf(buf
+ len
, SPI_REGS_BUFSIZE
- len
,
110 "SR: \t\t0x%08x\n", dw_readl(dws
, sr
));
111 len
+= snprintf(buf
+ len
, SPI_REGS_BUFSIZE
- len
,
112 "IMR: \t\t0x%08x\n", dw_readl(dws
, imr
));
113 len
+= snprintf(buf
+ len
, SPI_REGS_BUFSIZE
- len
,
114 "ISR: \t\t0x%08x\n", dw_readl(dws
, isr
));
115 len
+= snprintf(buf
+ len
, SPI_REGS_BUFSIZE
- len
,
116 "DMACR: \t\t0x%08x\n", dw_readl(dws
, dmacr
));
117 len
+= snprintf(buf
+ len
, SPI_REGS_BUFSIZE
- len
,
118 "DMATDLR: \t0x%08x\n", dw_readl(dws
, dmatdlr
));
119 len
+= snprintf(buf
+ len
, SPI_REGS_BUFSIZE
- len
,
120 "DMARDLR: \t0x%08x\n", dw_readl(dws
, dmardlr
));
121 len
+= snprintf(buf
+ len
, SPI_REGS_BUFSIZE
- len
,
122 "=================================\n");
124 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, len
);
129 static const struct file_operations mrst_spi_regs_ops
= {
130 .owner
= THIS_MODULE
,
131 .open
= spi_show_regs_open
,
132 .read
= spi_show_regs
,
133 .llseek
= default_llseek
,
136 static int mrst_spi_debugfs_init(struct dw_spi
*dws
)
138 dws
->debugfs
= debugfs_create_dir("mrst_spi", NULL
);
142 debugfs_create_file("registers", S_IFREG
| S_IRUGO
,
143 dws
->debugfs
, (void *)dws
, &mrst_spi_regs_ops
);
147 static void mrst_spi_debugfs_remove(struct dw_spi
*dws
)
150 debugfs_remove_recursive(dws
->debugfs
);
154 static inline int mrst_spi_debugfs_init(struct dw_spi
*dws
)
159 static inline void mrst_spi_debugfs_remove(struct dw_spi
*dws
)
162 #endif /* CONFIG_DEBUG_FS */
164 /* Return the max entries we can fill into tx fifo */
165 static inline u32
tx_max(struct dw_spi
*dws
)
167 u32 tx_left
, tx_room
, rxtx_gap
;
169 tx_left
= (dws
->tx_end
- dws
->tx
) / dws
->n_bytes
;
170 tx_room
= dws
->fifo_len
- dw_readw(dws
, txflr
);
173 * Another concern is about the tx/rx mismatch, we
174 * though to use (dws->fifo_len - rxflr - txflr) as
175 * one maximum value for tx, but it doesn't cover the
176 * data which is out of tx/rx fifo and inside the
177 * shift registers. So a control from sw point of
180 rxtx_gap
= ((dws
->rx_end
- dws
->rx
) - (dws
->tx_end
- dws
->tx
))
183 return min3(tx_left
, tx_room
, (u32
) (dws
->fifo_len
- rxtx_gap
));
186 /* Return the max entries we should read out of rx fifo */
187 static inline u32
rx_max(struct dw_spi
*dws
)
189 u32 rx_left
= (dws
->rx_end
- dws
->rx
) / dws
->n_bytes
;
191 return min(rx_left
, (u32
)dw_readw(dws
, rxflr
));
194 static void dw_writer(struct dw_spi
*dws
)
196 u32 max
= tx_max(dws
);
200 /* Set the tx word if the transfer's original "tx" is not null */
201 if (dws
->tx_end
- dws
->len
) {
202 if (dws
->n_bytes
== 1)
203 txw
= *(u8
*)(dws
->tx
);
205 txw
= *(u16
*)(dws
->tx
);
207 dw_writew(dws
, dr
, txw
);
208 dws
->tx
+= dws
->n_bytes
;
212 static void dw_reader(struct dw_spi
*dws
)
214 u32 max
= rx_max(dws
);
218 rxw
= dw_readw(dws
, dr
);
219 /* Care rx only if the transfer's original "rx" is not null */
220 if (dws
->rx_end
- dws
->len
) {
221 if (dws
->n_bytes
== 1)
222 *(u8
*)(dws
->rx
) = rxw
;
224 *(u16
*)(dws
->rx
) = rxw
;
226 dws
->rx
+= dws
->n_bytes
;
230 static void *next_transfer(struct dw_spi
*dws
)
232 struct spi_message
*msg
= dws
->cur_msg
;
233 struct spi_transfer
*trans
= dws
->cur_transfer
;
235 /* Move to next transfer */
236 if (trans
->transfer_list
.next
!= &msg
->transfers
) {
238 list_entry(trans
->transfer_list
.next
,
241 return RUNNING_STATE
;
247 * Note: first step is the protocol driver prepares
248 * a dma-capable memory, and this func just need translate
249 * the virt addr to physical
251 static int map_dma_buffers(struct dw_spi
*dws
)
253 if (!dws
->cur_msg
->is_dma_mapped
255 || !dws
->cur_chip
->enable_dma
259 if (dws
->cur_transfer
->tx_dma
)
260 dws
->tx_dma
= dws
->cur_transfer
->tx_dma
;
262 if (dws
->cur_transfer
->rx_dma
)
263 dws
->rx_dma
= dws
->cur_transfer
->rx_dma
;
268 /* Caller already set message->status; dma and pio irqs are blocked */
269 static void giveback(struct dw_spi
*dws
)
271 struct spi_transfer
*last_transfer
;
273 struct spi_message
*msg
;
275 spin_lock_irqsave(&dws
->lock
, flags
);
278 dws
->cur_transfer
= NULL
;
279 dws
->prev_chip
= dws
->cur_chip
;
280 dws
->cur_chip
= NULL
;
282 queue_work(dws
->workqueue
, &dws
->pump_messages
);
283 spin_unlock_irqrestore(&dws
->lock
, flags
);
285 last_transfer
= list_entry(msg
->transfers
.prev
,
289 if (!last_transfer
->cs_change
&& dws
->cs_control
)
290 dws
->cs_control(MRST_SPI_DEASSERT
);
294 msg
->complete(msg
->context
);
297 static void int_error_stop(struct dw_spi
*dws
, const char *msg
)
300 spi_enable_chip(dws
, 0);
302 dev_err(&dws
->master
->dev
, "%s\n", msg
);
303 dws
->cur_msg
->state
= ERROR_STATE
;
304 tasklet_schedule(&dws
->pump_transfers
);
307 void dw_spi_xfer_done(struct dw_spi
*dws
)
309 /* Update total byte transferred return count actual bytes read */
310 dws
->cur_msg
->actual_length
+= dws
->len
;
312 /* Move to next transfer */
313 dws
->cur_msg
->state
= next_transfer(dws
);
315 /* Handle end of message */
316 if (dws
->cur_msg
->state
== DONE_STATE
) {
317 dws
->cur_msg
->status
= 0;
320 tasklet_schedule(&dws
->pump_transfers
);
322 EXPORT_SYMBOL_GPL(dw_spi_xfer_done
);
324 static irqreturn_t
interrupt_transfer(struct dw_spi
*dws
)
326 u16 irq_status
= dw_readw(dws
, isr
);
329 if (irq_status
& (SPI_INT_TXOI
| SPI_INT_RXOI
| SPI_INT_RXUI
)) {
330 dw_readw(dws
, txoicr
);
331 dw_readw(dws
, rxoicr
);
332 dw_readw(dws
, rxuicr
);
333 int_error_stop(dws
, "interrupt_transfer: fifo overrun/underrun");
338 if (dws
->rx_end
== dws
->rx
) {
339 spi_mask_intr(dws
, SPI_INT_TXEI
);
340 dw_spi_xfer_done(dws
);
343 if (irq_status
& SPI_INT_TXEI
) {
344 spi_mask_intr(dws
, SPI_INT_TXEI
);
346 /* Enable TX irq always, it will be disabled when RX finished */
347 spi_umask_intr(dws
, SPI_INT_TXEI
);
353 static irqreturn_t
dw_spi_irq(int irq
, void *dev_id
)
355 struct dw_spi
*dws
= dev_id
;
356 u16 irq_status
= dw_readw(dws
, isr
) & 0x3f;
362 spi_mask_intr(dws
, SPI_INT_TXEI
);
366 return dws
->transfer_handler(dws
);
369 /* Must be called inside pump_transfers() */
370 static void poll_transfer(struct dw_spi
*dws
)
376 } while (dws
->rx_end
> dws
->rx
);
378 dw_spi_xfer_done(dws
);
381 static void pump_transfers(unsigned long data
)
383 struct dw_spi
*dws
= (struct dw_spi
*)data
;
384 struct spi_message
*message
= NULL
;
385 struct spi_transfer
*transfer
= NULL
;
386 struct spi_transfer
*previous
= NULL
;
387 struct spi_device
*spi
= NULL
;
388 struct chip_data
*chip
= NULL
;
397 /* Get current state information */
398 message
= dws
->cur_msg
;
399 transfer
= dws
->cur_transfer
;
400 chip
= dws
->cur_chip
;
403 if (unlikely(!chip
->clk_div
))
404 chip
->clk_div
= dws
->max_freq
/ chip
->speed_hz
;
406 if (message
->state
== ERROR_STATE
) {
407 message
->status
= -EIO
;
411 /* Handle end of message */
412 if (message
->state
== DONE_STATE
) {
417 /* Delay if requested at end of transfer*/
418 if (message
->state
== RUNNING_STATE
) {
419 previous
= list_entry(transfer
->transfer_list
.prev
,
422 if (previous
->delay_usecs
)
423 udelay(previous
->delay_usecs
);
426 dws
->n_bytes
= chip
->n_bytes
;
427 dws
->dma_width
= chip
->dma_width
;
428 dws
->cs_control
= chip
->cs_control
;
430 dws
->rx_dma
= transfer
->rx_dma
;
431 dws
->tx_dma
= transfer
->tx_dma
;
432 dws
->tx
= (void *)transfer
->tx_buf
;
433 dws
->tx_end
= dws
->tx
+ transfer
->len
;
434 dws
->rx
= transfer
->rx_buf
;
435 dws
->rx_end
= dws
->rx
+ transfer
->len
;
436 dws
->cs_change
= transfer
->cs_change
;
437 dws
->len
= dws
->cur_transfer
->len
;
438 if (chip
!= dws
->prev_chip
)
443 /* Handle per transfer options for bpw and speed */
444 if (transfer
->speed_hz
) {
445 speed
= chip
->speed_hz
;
447 if (transfer
->speed_hz
!= speed
) {
448 speed
= transfer
->speed_hz
;
449 if (speed
> dws
->max_freq
) {
450 printk(KERN_ERR
"MRST SPI0: unsupported"
451 "freq: %dHz\n", speed
);
452 message
->status
= -EIO
;
456 /* clk_div doesn't support odd number */
457 clk_div
= dws
->max_freq
/ speed
;
458 clk_div
= (clk_div
+ 1) & 0xfffe;
460 chip
->speed_hz
= speed
;
461 chip
->clk_div
= clk_div
;
464 if (transfer
->bits_per_word
) {
465 bits
= transfer
->bits_per_word
;
470 dws
->n_bytes
= dws
->dma_width
= bits
>> 3;
473 printk(KERN_ERR
"MRST SPI0: unsupported bits:"
475 message
->status
= -EIO
;
480 | (chip
->type
<< SPI_FRF_OFFSET
)
481 | (spi
->mode
<< SPI_MODE_OFFSET
)
482 | (chip
->tmode
<< SPI_TMOD_OFFSET
);
484 message
->state
= RUNNING_STATE
;
487 * Adjust transfer mode if necessary. Requires platform dependent
488 * chipselect mechanism.
490 if (dws
->cs_control
) {
491 if (dws
->rx
&& dws
->tx
)
492 chip
->tmode
= SPI_TMOD_TR
;
494 chip
->tmode
= SPI_TMOD_RO
;
496 chip
->tmode
= SPI_TMOD_TO
;
498 cr0
&= ~SPI_TMOD_MASK
;
499 cr0
|= (chip
->tmode
<< SPI_TMOD_OFFSET
);
502 /* Check if current transfer is a DMA transaction */
503 dws
->dma_mapped
= map_dma_buffers(dws
);
507 * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
509 if (!dws
->dma_mapped
&& !chip
->poll_mode
) {
510 int templen
= dws
->len
/ dws
->n_bytes
;
511 txint_level
= dws
->fifo_len
/ 2;
512 txint_level
= (templen
> txint_level
) ? txint_level
: templen
;
514 imask
|= SPI_INT_TXEI
| SPI_INT_TXOI
| SPI_INT_RXUI
| SPI_INT_RXOI
;
515 dws
->transfer_handler
= interrupt_transfer
;
519 * Reprogram registers only if
520 * 1. chip select changes
521 * 2. clk_div is changed
522 * 3. control value changes
524 if (dw_readw(dws
, ctrl0
) != cr0
|| cs_change
|| clk_div
|| imask
) {
525 spi_enable_chip(dws
, 0);
527 if (dw_readw(dws
, ctrl0
) != cr0
)
528 dw_writew(dws
, ctrl0
, cr0
);
530 spi_set_clk(dws
, clk_div
? clk_div
: chip
->clk_div
);
531 spi_chip_sel(dws
, spi
->chip_select
);
533 /* Set the interrupt mask, for poll mode just disable all int */
534 spi_mask_intr(dws
, 0xff);
536 spi_umask_intr(dws
, imask
);
538 dw_writew(dws
, txfltr
, txint_level
);
540 spi_enable_chip(dws
, 1);
542 dws
->prev_chip
= chip
;
546 dws
->dma_ops
->dma_transfer(dws
, cs_change
);
558 static void pump_messages(struct work_struct
*work
)
561 container_of(work
, struct dw_spi
, pump_messages
);
564 /* Lock queue and check for queue work */
565 spin_lock_irqsave(&dws
->lock
, flags
);
566 if (list_empty(&dws
->queue
) || dws
->run
== QUEUE_STOPPED
) {
568 spin_unlock_irqrestore(&dws
->lock
, flags
);
572 /* Make sure we are not already running a message */
574 spin_unlock_irqrestore(&dws
->lock
, flags
);
578 /* Extract head of queue */
579 dws
->cur_msg
= list_entry(dws
->queue
.next
, struct spi_message
, queue
);
580 list_del_init(&dws
->cur_msg
->queue
);
582 /* Initial message state*/
583 dws
->cur_msg
->state
= START_STATE
;
584 dws
->cur_transfer
= list_entry(dws
->cur_msg
->transfers
.next
,
587 dws
->cur_chip
= spi_get_ctldata(dws
->cur_msg
->spi
);
589 /* Mark as busy and launch transfers */
590 tasklet_schedule(&dws
->pump_transfers
);
593 spin_unlock_irqrestore(&dws
->lock
, flags
);
596 /* spi_device use this to queue in their spi_msg */
597 static int dw_spi_transfer(struct spi_device
*spi
, struct spi_message
*msg
)
599 struct dw_spi
*dws
= spi_master_get_devdata(spi
->master
);
602 spin_lock_irqsave(&dws
->lock
, flags
);
604 if (dws
->run
== QUEUE_STOPPED
) {
605 spin_unlock_irqrestore(&dws
->lock
, flags
);
609 msg
->actual_length
= 0;
610 msg
->status
= -EINPROGRESS
;
611 msg
->state
= START_STATE
;
613 list_add_tail(&msg
->queue
, &dws
->queue
);
615 if (dws
->run
== QUEUE_RUNNING
&& !dws
->busy
) {
617 if (dws
->cur_transfer
|| dws
->cur_msg
)
618 queue_work(dws
->workqueue
,
619 &dws
->pump_messages
);
621 /* If no other data transaction in air, just go */
622 spin_unlock_irqrestore(&dws
->lock
, flags
);
623 pump_messages(&dws
->pump_messages
);
628 spin_unlock_irqrestore(&dws
->lock
, flags
);
632 /* This may be called twice for each spi dev */
633 static int dw_spi_setup(struct spi_device
*spi
)
635 struct dw_spi_chip
*chip_info
= NULL
;
636 struct chip_data
*chip
;
638 if (spi
->bits_per_word
!= 8 && spi
->bits_per_word
!= 16)
641 /* Only alloc on first setup */
642 chip
= spi_get_ctldata(spi
);
644 chip
= kzalloc(sizeof(struct chip_data
), GFP_KERNEL
);
650 * Protocol drivers may change the chip settings, so...
651 * if chip_info exists, use it
653 chip_info
= spi
->controller_data
;
655 /* chip_info doesn't always exist */
657 if (chip_info
->cs_control
)
658 chip
->cs_control
= chip_info
->cs_control
;
660 chip
->poll_mode
= chip_info
->poll_mode
;
661 chip
->type
= chip_info
->type
;
663 chip
->rx_threshold
= 0;
664 chip
->tx_threshold
= 0;
666 chip
->enable_dma
= chip_info
->enable_dma
;
669 if (spi
->bits_per_word
<= 8) {
672 } else if (spi
->bits_per_word
<= 16) {
676 /* Never take >16b case for MRST SPIC */
677 dev_err(&spi
->dev
, "invalid wordsize\n");
680 chip
->bits_per_word
= spi
->bits_per_word
;
682 if (!spi
->max_speed_hz
) {
683 dev_err(&spi
->dev
, "No max speed HZ parameter\n");
686 chip
->speed_hz
= spi
->max_speed_hz
;
688 chip
->tmode
= 0; /* Tx & Rx */
689 /* Default SPI mode is SCPOL = 0, SCPH = 0 */
690 chip
->cr0
= (chip
->bits_per_word
- 1)
691 | (chip
->type
<< SPI_FRF_OFFSET
)
692 | (spi
->mode
<< SPI_MODE_OFFSET
)
693 | (chip
->tmode
<< SPI_TMOD_OFFSET
);
695 spi_set_ctldata(spi
, chip
);
699 static void dw_spi_cleanup(struct spi_device
*spi
)
701 struct chip_data
*chip
= spi_get_ctldata(spi
);
705 static int __devinit
init_queue(struct dw_spi
*dws
)
707 INIT_LIST_HEAD(&dws
->queue
);
708 spin_lock_init(&dws
->lock
);
710 dws
->run
= QUEUE_STOPPED
;
713 tasklet_init(&dws
->pump_transfers
,
714 pump_transfers
, (unsigned long)dws
);
716 INIT_WORK(&dws
->pump_messages
, pump_messages
);
717 dws
->workqueue
= create_singlethread_workqueue(
718 dev_name(dws
->master
->dev
.parent
));
719 if (dws
->workqueue
== NULL
)
725 static int start_queue(struct dw_spi
*dws
)
729 spin_lock_irqsave(&dws
->lock
, flags
);
731 if (dws
->run
== QUEUE_RUNNING
|| dws
->busy
) {
732 spin_unlock_irqrestore(&dws
->lock
, flags
);
736 dws
->run
= QUEUE_RUNNING
;
738 dws
->cur_transfer
= NULL
;
739 dws
->cur_chip
= NULL
;
740 dws
->prev_chip
= NULL
;
741 spin_unlock_irqrestore(&dws
->lock
, flags
);
743 queue_work(dws
->workqueue
, &dws
->pump_messages
);
748 static int stop_queue(struct dw_spi
*dws
)
754 spin_lock_irqsave(&dws
->lock
, flags
);
755 dws
->run
= QUEUE_STOPPED
;
756 while ((!list_empty(&dws
->queue
) || dws
->busy
) && limit
--) {
757 spin_unlock_irqrestore(&dws
->lock
, flags
);
759 spin_lock_irqsave(&dws
->lock
, flags
);
762 if (!list_empty(&dws
->queue
) || dws
->busy
)
764 spin_unlock_irqrestore(&dws
->lock
, flags
);
769 static int destroy_queue(struct dw_spi
*dws
)
773 status
= stop_queue(dws
);
776 destroy_workqueue(dws
->workqueue
);
780 /* Restart the controller, disable all interrupts, clean rx fifo */
781 static void spi_hw_init(struct dw_spi
*dws
)
783 spi_enable_chip(dws
, 0);
784 spi_mask_intr(dws
, 0xff);
785 spi_enable_chip(dws
, 1);
788 * Try to detect the FIFO depth if not set by interface driver,
789 * the depth could be from 2 to 256 from HW spec
791 if (!dws
->fifo_len
) {
793 for (fifo
= 2; fifo
<= 257; fifo
++) {
794 dw_writew(dws
, txfltr
, fifo
);
795 if (fifo
!= dw_readw(dws
, txfltr
))
799 dws
->fifo_len
= (fifo
== 257) ? 0 : fifo
;
800 dw_writew(dws
, txfltr
, 0);
804 int __devinit
dw_spi_add_host(struct dw_spi
*dws
)
806 struct spi_master
*master
;
811 master
= spi_alloc_master(dws
->parent_dev
, 0);
817 dws
->master
= master
;
818 dws
->type
= SSI_MOTO_SPI
;
819 dws
->prev_chip
= NULL
;
821 dws
->dma_addr
= (dma_addr_t
)(dws
->paddr
+ 0x60);
822 snprintf(dws
->name
, sizeof(dws
->name
), "dw_spi%d",
825 ret
= request_irq(dws
->irq
, dw_spi_irq
, IRQF_SHARED
,
828 dev_err(&master
->dev
, "can not get IRQ\n");
829 goto err_free_master
;
832 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
;
833 master
->bus_num
= dws
->bus_num
;
834 master
->num_chipselect
= dws
->num_cs
;
835 master
->cleanup
= dw_spi_cleanup
;
836 master
->setup
= dw_spi_setup
;
837 master
->transfer
= dw_spi_transfer
;
842 if (dws
->dma_ops
&& dws
->dma_ops
->dma_init
) {
843 ret
= dws
->dma_ops
->dma_init(dws
);
845 dev_warn(&master
->dev
, "DMA init failed\n");
850 /* Initial and start queue */
851 ret
= init_queue(dws
);
853 dev_err(&master
->dev
, "problem initializing queue\n");
856 ret
= start_queue(dws
);
858 dev_err(&master
->dev
, "problem starting queue\n");
862 spi_master_set_devdata(master
, dws
);
863 ret
= spi_register_master(master
);
865 dev_err(&master
->dev
, "problem registering spi master\n");
866 goto err_queue_alloc
;
869 mrst_spi_debugfs_init(dws
);
874 if (dws
->dma_ops
&& dws
->dma_ops
->dma_exit
)
875 dws
->dma_ops
->dma_exit(dws
);
877 spi_enable_chip(dws
, 0);
878 free_irq(dws
->irq
, dws
);
880 spi_master_put(master
);
884 EXPORT_SYMBOL_GPL(dw_spi_add_host
);
886 void __devexit
dw_spi_remove_host(struct dw_spi
*dws
)
892 mrst_spi_debugfs_remove(dws
);
894 /* Remove the queue */
895 status
= destroy_queue(dws
);
897 dev_err(&dws
->master
->dev
, "dw_spi_remove: workqueue will not "
898 "complete, message memory not freed\n");
900 if (dws
->dma_ops
&& dws
->dma_ops
->dma_exit
)
901 dws
->dma_ops
->dma_exit(dws
);
902 spi_enable_chip(dws
, 0);
905 free_irq(dws
->irq
, dws
);
907 /* Disconnect from the SPI framework */
908 spi_unregister_master(dws
->master
);
910 EXPORT_SYMBOL_GPL(dw_spi_remove_host
);
912 int dw_spi_suspend_host(struct dw_spi
*dws
)
916 ret
= stop_queue(dws
);
919 spi_enable_chip(dws
, 0);
923 EXPORT_SYMBOL_GPL(dw_spi_suspend_host
);
925 int dw_spi_resume_host(struct dw_spi
*dws
)
930 ret
= start_queue(dws
);
932 dev_err(&dws
->master
->dev
, "fail to start queue (%d)\n", ret
);
935 EXPORT_SYMBOL_GPL(dw_spi_resume_host
);
937 MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
938 MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
939 MODULE_LICENSE("GPL v2");