1 * Board Control and Status (BCSR)
5 - compatible : Should be "fsl,<board>-bcsr"
6 - reg : Offset and length of the register set for the device
11 compatible = "fsl,mpc8360mds-bcsr";
12 reg = <f8000000 8000>;
15 * Freescale on board FPGA
17 This is the memory-mapped registers for on board FPGA.
20 - compatible : should be "fsl,fpga-pixis".
21 - reg : should contain the address and the length of the FPPGA register
23 - interrupt-parent: should specify phandle for the interrupt controller.
24 - interrupts : should specify event (wakeup) IRQ.
26 Example (MPC8610HPCD):
28 board-control@e8000000 {
29 compatible = "fsl,fpga-pixis";
30 reg = <0xe8000000 32>;
31 interrupt-parent = <&mpic>;
35 * Freescale BCSR GPIO banks
37 Some BCSR registers act as simple GPIO controllers, each such
38 register can be represented by the gpio-controller node.
41 - compatible : Should be "fsl,<board>-bcsr-gpio".
42 - reg : Should contain the address and the length of the GPIO bank
44 - #gpio-cells : Should be two. The first cell is the pin number and the
45 second cell is used to specify optional parameters (currently unused).
46 - gpio-controller : Marks the port as GPIO controller.
53 compatible = "fsl,mpc8360mds-bcsr";
55 ranges = <0 1 0 0x8000>;
57 bcsr13: gpio-controller@d {
59 compatible = "fsl,mpc8360mds-bcsr-gpio";